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Zilog 



November 1988 

Z8000™ 

Family Data Book 



ELECTRONICS SALES PROFESSIONALS 

SU ' te 201 -5200 Dixie Rd. Miss.ssauga. Ont. L4W 1E4 



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Zilog 



November 1988 

Z8000 Family 
Data Book 



Z8000 Family Data Book 
Table of Contents 



Product Specifications Product No. 

Zilog Z8000 Family Architecture 1 

Z160™CPU Z0816010 9 

Z320™ CPU Z80320XX 44 

Z328 ICE Z8032810 54 

Z5380 SCSI Z0538010 55 

Z7220A High Performance Graphics Display Controller Z7220AXX 79 

Z765AFDC Z0765A08 101 

Z8001/Z8002 Z8000 CPU Z08001XX 

Z08002XX 128 

Z8010Z8000MMU Z08010XX 163 

Z8016Z8000Z-DTC Z08016XX 179 

Z16C20 CMOS Z-BUS GLU Z16C20XX 211 

Z80C30 CMOS Z-BUS SCC/Z85C30 CMOS SCC Z80C30XX 

Z85C30XX 222 

Z8030 Z-BUS SCC/Z8530SCC Z08030XX 

Z08530XX 253 

Z8036 Z8000 Z-CIO Z08036XX 282 

Z8536 CIO Counter/Timer and Parallel I/O Unit Z08536XX 307 

Z8038/Z8538 FIO FIFO Input/Output Interface Unit Z08038XX 

Z0853806 332 

Z8060/Z8560 FIFO Buffer Unit Z0806000 

Z0856000 363 

Z8068/Z9518 Z-DCP Z0806804 370 

Z8516/Z951 6 DMA Transfer Controller (DTC) Z08516XX 386 

Z8581 /Clock Generator and Controller Z08581XX 427 

Z80,000™ CPU Z8000010 437 



Application Notes and Technical Articles 

Interfacing Z80 CPUs to the Z8500 Peripheral Family 462 

Interfacing the Z8500 Peripherals to the 68000 485 

Design Considerations using Quartz Crystals with Zilog's Components 497 

Using Z8581 Clock Sketches in Z80 ®CPU Applications 501 

Interfacing Z-BUS 8 Peripherals to the V20 / V30 / 8086 / 8088 510 

Interfacing the Z-BUS Peripherals Article Reprint 518 

Using SCC with Z8000 In SDLC Protocol 523 

SCC In Binary Synchronous Communications 535 

Military Products 545 

Z8000 Development Support 548 

Zilog Quality and Reliabilty 553 

Literature Guide 555 

Ordering Information 556 

Package Information 561 



Zilog 



November 1988 



Zilog Z8000 Family Architecture 
A High-Performance 16-Bit 
Architecture With 32-Bit Migration 
Z8000 ™16 Bit CPU's 
Z80.000™ 32 Bit CPU's 



In the office, in the factory, even in the home-every day the 
number of people using microprocessors grows. And every 
day, these people dream of new applications and better 
systems. Systems that are faster, more reliable, easier to 
use, and yet cost less. 

To the designer, this vision of the future means building 
systems with more processing power, communications 
interfaces, efficient use of large memories, and software 
that is both more sophisticated and more reliable. To get 
these systems to market quickly and with minimal devel- 
opment costs, the designer needs powerful building 
blocks- circuits and software designed to work together. 

Zilog's Z8000 Family was born of this vision. Using 
advances in VLSI technology, the wealth of experience 
with 16-bit architecture and the overwhelming success of 
its 8-bit microprocessor family, Zilog conceived the Z8000 
Family as a bold answer to the needs of the system 
sr. 



The Established Leader 

Zilogs Z80 CPU has become synonymous with high- 
performance, low-cost computing. Its system-oriented 
instruction set, efficient use of package and pins, broad 
range of peripherals, and extensive hardware and 
software support have earned it first place in the 8-bit 
world. Used in applications that range from intelligent 
terminals to powerful microcomputer systems and 
device controllers, the Z80, Zilog's embodiment of the 
8-bit solution, has become the standard of the industry. 

16 Bits and Beyond 

With this successful precedent clearly in mind, Zilog de- 
cided to extend the Z80 tradition to 1 6 and 32 bits. The new 
processors place the power of 16 and 32 bits in the 
designer's hands. Like the Z80 they create a way to apply 
advanced architectural concepts to solve the real world 
problems of high performance microprocessor users. 
They also pave the way for new, compatible industry 
standards in the 1 6- and 32-bit CPUs, in peripherals and in 
software. By drawing on the architecture of minicomputers 
and mainframes, Zilog looked for and found a break- 
through, the Z8000 Family. 



A broad range of processing power and the need to 
manage vast amounts of memory are inherent in 1 6- and 
32-bit systems. But small systems and real-time perform- 
ance must not be penalized by these facts. It was essential, 
therefore, that each device be designed as an integral part 
of a family concept. 

The Z8000 Family is built around a defined set of intercon- 
nections and protocols called the Z-BUS, so circuit con- 
nections for present and future family members are all com- 
patible. Memory management, DMA transfer, and ex- 
tended processing have all been planned from the begin- 
ning. Atthe low end, Z80 users can now interface to 1 6- and 
32-bit processors by using the new highly integrated Z280 
CPU, a 1 6-bit CPU that has Z80 code on ZBUS. At the high 
end Z8000 users can now integrate to the Z80000 32-bit 
microprocessors and still run their 1 6-bit software. A high- 
speed, shared parallel bus, the Z-BUS provides all func- 
tions with a communication interface, as Figure 1 illus- 
trates. 



CPU 


EXTENDED 
PROCESSING 




UNIT 







Figure 1. Z-BUS Connects All Functions 



1 



System Flexibility. 

Even the smallest Z8000 systems offer high throughput 
and easy programming far superior to any existing micro- 
processor alternative. In mid-range applications, Z8000 
components offer very powerful solutions to the design 
problems of word processing, intelligent terminals, data 
communications, instrumentation, and process control. In 
a complex network of multiple processors, smart peripheral 
components, and a distributed memory configuration, the 
Z8000 Family provides performance and versatility ex- 
ceeding that of much larger-and far more expensive micro- 
processors. 

Higher Throughput 

The powerful instruction set, high execution speed, regular 
architecture, and numerous special features of the Z8000 
microprocessors dramatically increase system through- 
put. Intelligent Z8000 peripheral controllers and extended 
processing units unburden the CPU and boost throughput 
even further. 

The processing power of the Zilog Z8000 1 6-bit micropro- 
cessor can be boosted beyond its intrinsic capability by 
Extended Processing Architecture. Simply stated, EPA 
allows the Z8000 CPU to accommodate up to four Ex- 
tended Processing Units (EPUs), which perform special- 
ized functions in parallel with the CPU's main instruction 
execution stream, as Figure 2 illustrates. 
The use of extended processors to boost the main CPU's 
performance capability has been proven with large main- 
frame computers and minicomputers. In these systems, 
specialized functions such as array processing, special 
input/output processing, and data communications proc- 
essing are typically assigned to extended processor hard- 
ware. These extended processors are complex computers 
in their own right. 

An Unmatched CPU 

The Z8000 microprocessor is not just a wider data path, 
more registers, more data types, more addressing modes, 
more instructions, and more addressing space. It brings 
big-machine concepts to the level of components. 



Its general-register architecture avoids bottlenecks associ- 
ated with dedicated or implied registers. Special features 
support parallel processors, operating systems, compilers, 
and the implementation of virtual memory. 

The Z8000 CPU is also a very fast machine. Its through- 
put is greater than that of any other 1 6-bit microprocessor 
with comparable clock speeds. And the Z8000 CPU is 
available with speeds ranging from a moderate 6 MHz clock 
rate that allows you the choice of slow-access, low-cost 
memories to a high-speed 10 MHz clock rate for high- 
performance systems. From the three versions of the 
Z8000 microprocessors, you can select the one best suited 
to your needs: the Z8001 for large memory applications, 
the Z8002 for small memory applications, or the Z160 for 
the low cost, medium memory size applications. 

Peripheral Problem Solvers 

The Z8000 Peripherals offer more than simple answers to 
the basic needs of a microcomputer system. Complicated 
system tasks that previously required burdensome MSI 
circuitry can now be handled off-line. Even such highly 
specialized functions as data encryption/decryption are 
performed by Zilog peripherals. These multifunction pe- 
ripherals are extensively programmable so each can be 
precisely tailored to its application. Each can be made to 
perform complex, intelligent tasks on its own-to unburden 
the CPU, reduce bus traffic, and increase system through- 
put. 

Counting, timing, and parallel I/O, for example, are made 
easy by the Z8036 Z-CIO Counter and Parallel I/O Circuit 
with its three 16-bit counter/timers and three 8-bit parallel 
I/O ports. It can even function as a programmable inter- 
rupt-priority controller. 

Ease of implementation characterizes the interface be- 
tween the 16-bit, multiplexed Z8000 CPU and its Z-BUS 
peripherals. The Z-BUS ensures not only that communica- 
tions between Family members are consistently simple, 
but also that the resolution of interrupt priorities requires 
minimal CPU involvement. 



bJ 



DEDiCA 



DEDICATED 
E»U 
ME MO* i 




DEDICATED 
MEMORT 



Figure2. Typical Extended Processor Configuration 



2 



Data communications are deftly handled by the Z8030 Z- 
SCC Serial Communications Controller; a dual-channel 
multi-protocol component that supports all popular com- 
munications formats. Now also available in CMOS. 

Direct memory access is supported by the Z8016 DTC 
Transfer Controller, a fast dual-channel device that en- 
hances memory and I/O data transfers within stand-alone 
processor or parallel processor environments. 

Elements of asynchronous parallel-processing systems 
are interconnected by the Z8038 FIFO unit, a surprisingly 
flexible device whose buffer depth can be expanded with- 
out limit using the Z8060 FIFO Buffer Unit. 

The Z8068 Z-DCP Data Ciphering Processor, supporting 
three standard ciphering options and key parity checking, 
provides encryption and decryption of data where needed. 
The Z-DCP can input, output, and encipher simultane- 
ously. 

The Z8010 Z-MMU Memory Management Unit provides 
flexibility in code segmenter page relocation and sophisti- 
cation in memory protection rarely found in the micropro- 
cessor world. This device encourages modular software 
development-a critical factor as programs reach new 
levels of complexity. 



Universal Peripherals 

Extend the Range of Applications to increase the range of 
applications for its peripherals, Zilog selected certain of the 
multiplexed Z-BUS-compatible Z8000 Peripherals to be 
produced in a second bus version : a non-multiplexed 1 6-bit 
CPU-compatible line, called the Z8500 Universal Periph- 
eral. The Z8536 CIO, Z8530 SCC, and the Z08516 DTC 
are all "Universal" versions of their Z8000 counterparts and 
as such incorporate the same extensive features to per- 
form the same impressive functions. The Z8038 Z-FIO, 
and by extension the Z8060 FIFO, are compatible with both 
bus versions, and so endow both Families with their 
multiple strengths. 

To help meet the timing requirements of both Zilog and non- 
Zilog microprocessors, the Z8581 CGC Clock Generator 
and Controller has been added to the Z8500 Universal 
Peripherals group. The CGC outputs drive the Z80 and 
Z8000 CPUs clock inputs directly; no bus interface is 
required. Selective clock-stretching abilities provide a 
variety of timing outputs to make this a versatile chip 
suitable for VLSI and LSI devices. Table 1 summarizes the 
Z8000 CPU and peripheral offering. 

Simply put, the Z8000 Family offers more for less money. 
The Z8000 microprocessors give mid-range minicomputer 
performance at microprocessor cost. At component 
prices, Z8000 peripheral controllers perform complex 
system functions that previously required an entire PC 
board. 



AD0-AD15 

zeooo 

CPU 

AS 

DS 
WW 






s 


AD0-AO7 

Z8000 
PERIPHERAL 

CSo 

AS 

DS 








ADDRESS 
DECODE 













Figure 3. Z8000 Interface 



3 



The 32-bit Migration 

Zilog has now completed the migration from the 1 6-bit to 
the 32-bit CPU, with the Z80.000 and Z80320 or the Z320. 
Software compatible to the Z8000 CPUs, the Z80.000 and 
Z320 provide flexibility at the cost of a 16-bit CPU. Oriented 
to the applications in which high throughput is required, its 
file of 16 general-purpose 32-bit registers handles bytes, 
words, and long words with equal facility. The rich instruc- 
tion set combines powerful addressing modes and opera- 
tions in a manner that aids assembly-language coding of 
time-critical applications, and still provides the complete- 
ness desirable for efficient compiler-generated code. 

The Z320 CPU can be configured under software control to 
use 1 6-bit logical addresses (ideally suited for high-speed 
controller applications) or 32-bit addresses (for large-sys- 
tem tasks). The 32-bit address modes support both a linear 
addressing space and an alternative segmented address- 
ing space, which are selected by the user according to the 
application's requirements. 

Other system features include System and Normal modes 
of operation, a sophisticated trapping mechanism, a high- 
performance bus structure, and built-in multiprocessor 
support with global memory access arbitration signals for 
easy request and acknowledge handshaking. 

An on-chip cache and memory management unit (MMU), 
coupled with a sophisticated instruction pipeline, enable 
the Z320 to execute instructions at a rate of up to one in- 
struction per processor cycle. The 256-byte cache pro- 
vides an automatic buffering mechanism to hold the most 
recently fetched instructions and data on the chip. Thus, 
subsequent references to these items do not require 
lengthy memory transactions but instead can be fetched in 
a single processor cycle. 

The memory management unit on the chip contains all the 
information needed to translate the most recently used 
logical addresses generated by the CPU into the physical 
addresses used by the memory system. With each ad- 
dress translation, access attributes are automatically 
checked to determine whether or not the access is permit- 
ted. The MMU can be used to implement a virtual memory 
or can be disabled entirely for applications that do not need 
memory management. 



Peripheral Support. 

The Z320 uses Zilogs Z-BUS so the entire Z8000 family of 
circuits are available for use with it. Multifunction Z-BUS 
peripherals are extensively programmable, so each can be 
precisely tailored to an application. 

Z-BUS Component Interconnect 

The Z-BUS is a high-speed parallel shared bus that links 
the Z8000, Z320 microprocessor families and Extended 
Processing Units with the peripherals needed to implement 
complete systems. Through a common communications 
interface, Z-BUS peripherals and CPUs support the follow- 
ing types of transactions: 

Data Transfer. 16 or 32 bits of data can be moved 
between bus controllers (such as a CPU) and associ- 
ated peripherals. 

Interrupts. Interrupts can be generated by peripher- 
als and serviced by CPUs over the bus. 

Resource Control. A daisy chain priority mechanism 
supports distributed management of shared resources 
which includes peripheral devices and the bus itself. 

The heart of the Z-BUS is a set of multiplexed address/ data 
lines and the signals that control these lines. Multiplexing 
data and address onto the same lines makes more efficient 
use of pins and facilitates expansion of the number of data 
and address bits. Multiplexing also allows straight-forward 
addressing of a peripheral's internal registers, which 
greatly simplifies I/O programming. 

A daisy-chained priority mechanism resolves interrupt and 
resource requests, thus allowing distributed control of the 
bus and eliminating the need for separate priority control- 
lers. 

The resource-control daisy chain also allows wide physical 
separation of components. 

Furthermore, Z-BUS is asynchronous in the sense that 
peripherals need not be sychronized with the CPU clock. 
All timing information is provided by Z-BUS signals. 
As a result of a common hardware interface and protocol, 
users can be assured that adequate system support for 
their Z8000 or Z320 system design is readily available for 
the Z-BUS peripherals and Extended Processing Units: 



4 



PRIMARY SIQNALS 



^ ADo-AD^/AOa^ ) 
EXTENDED ADDRESS^ ) 

= \ 

STATUS i 



BUS 
MASTER 



PERIPHERAL 
AND MEMORY 



ADo-AD 
EXTENDED ADDRESS 
STATUS 



1S/AD31 \ 
3DRESS ) 



-BUS REQUEST SIGNALS - 



CPU 



REQUESTER 



-INTERRUPT SIGNALS - 

iSr 



CPU STATUS 



INTACK 



PERIPHERAL 



IEI ' 
• IEO - 



Z-BUS 
COMPONENT 



RESOURCE REQUEST SIONALS 

UMBO « 

MUST 

*m MM Al . 

» MMAO 



MULTI-MICRO 
REQUEST 



Figure 4. Z-BUS Signals 



\ 



TABLE - 1 Z8000 PRODUCT OFFERING 



Part No 



Device Name 



Description 



Package 



Z08001/2 



Z08160 



Z80320 
Z80000 



Z08010 



Z08016 
Z08516 



Z08030 
Z08530 



Z08036 
Z08536 



Z08038 



Z8001/ 
Z8002 
16-bit CPU 

Z160 

16-bit CPU 



Z320 
Z80K 

32-bit CPU 



MMU 



DTC 



SCC 



CIO 



FIO 



Z08060 FIFO 



Z08068 DCP 



Z08581 CGC 



Z80C30 CMOS Z-SCC 



16-bit Internal/External CPU, 16x 6,10 P,V,C,D,L 

16-bit General Purpose Registers 
8M Byte Addressing 

1 6-bit Internal/External CPU, 1 6x 6, 1 V 

16-bit General Purpose Registers 
2M Byte Addressing 

32-bit Internal/External CPU, 32x 

32-bit General Purpose Registers 8,10 V,G 

4G Byte Addressing 

Provides Dynamic Memory Segment 6,10 P 

Relocation of Blocks from 256 to 
65,532 Bytes, Protection Features 

2 Independent, Multi-functional 4,6 P, V 

Channels that Control Memory 
Transfers up to 6M Byte/sec 

2 Independent, Full Duplex Channels 4,6,8 P,D,V,C,L 

Transfer Rates from to 1 .5M 
bits/sec, Sync & Asynchronous Modes 

2 Independent 8-bit General Purpose 4,6 P,D,V,C,L 

Devices, satisfies most Counter/Timer 
and Parallel I/O needs 

128 byte, Async, Bidirectional FIFO 4* ,6 D,P,V,C,L 

Buffer with I/O Control 
Logic on Board 

128 x 8-bit Memory, Bidirectional 1 MB/sec P,C 

Asynchronous Data Transfer 

Capability 

Encrypts and Decrypts Data 4 P 

Using Three Standard Ciphering 

Modes 

2 Independent 20 MHz Oscillators 6,10 P,C,L 

Output Directly to Z80, Z8000 
and other CPUs 

CMOS Version is Pin 6,8,10 P,V,C 

Compatible with the Standard 
NMOS Device 



6 



TABLE - 1 Z8000 PRODUCT OFFERING (Cont.) 



Part No 



Device Name 



Description 



Package 



Z85C30 CMOS SCC CMOS Version is Pin 

Compatible with the Standard 
NMOS Device 



6,8,10 



P,V,C 



Z0765A 



Z7220A 



Z05380 



765A 



7220A 



SCSI 



Floppy Disk Controller (FDC) 

Floppy Disk interfaces Microprocessors to 

Control up to Four Floppy Disk Drives 

High-Performance Graphics Display 
Controller Interfaces with Micro- 
processors to Generate Displays 

CMOS, Asynchronous SCSI Protocol 



P,V 



1.0MB/sec 



P,V 



Packages: P=Plastic DIP, V=PLCC, C=Ceramic, D=Cerdip, G=Pin Grid Array, L=LCC, *=Available while 4 MHz supply 
lasts. 



7 



Zilog 



Product Specification 



Z160 CPU 

Central Processing Unit 



October 1988 



FEATURES 

■ Fully software compatible member of the Z8000® 
architecture. 

■ Instruction set more powerful than many minicomputers 

■ Directly addresses 2 Mbytes in 32 segments. 

■ Eight user-selectable addressing modes 

■ Seven data types that range from bits to 32-bit long words 
and byte and word strings 

■ System and Normal operating modes 

■ Separate code, data, and stack spaces 

■ Sophisticated interrupt structure 



Resource-shaping capabilities for multiprocessing 
systems 

Multi-programming support 
Compiler support 

32-bit operations, including signed multiply and divide 

Z-BUS compatible 

6 and 10 MHz clock rate 

Small, low-cost 44-pin PLCC package for surface 
mount applications. 



GENERAL DESCRIPTION 



The Z8000 is an advanced high-end 16-bit microprocessor 
that spans a wide variety of applications ranging from simple 
stand-alone computers to complex parallel-processing 
systems. Essentially a monolithic minicomputer central 
processing unit, the Z8000 CPU is characterized by an 
instruction set more powerful than many minicomputers; 
abundant resources in registers, data types, addressing 
modes and addressing range, and a regular architecture 
that enhances throughput by avoiding critical bottlenecks 
such as implied or dedicated registers. 

CPU resources include sixteen 16-bit general-purpose 
registers, seven data types that range from bits to 32-bit long 
words and byte and word strings, and eight user-selectable 
addressing modes. The 110 distinct instruction types can 
be combined with the various data types and addressing 
modes to form a powerful set of 414 instructions. Moreover, 
the instruction set is regular; most instructions can use any 
of the five main addressing modes and can operate on byte, 
word, and long-word data types. 

The CPU can operate in either the system or normal mode. 
The distinction between these two modes permits privileged 
operations, thereby improving operating system 
organization and implementation. Multiprogramming is 
supported by the "atomic" Test and Set instruction; 
multiprocessing by a combination of instruction and 



CPU 
CONTROL 



{ = 



MULTI-MICRO 



READ/WHITE 

NORMAL/SYSTEM 

BYTE/WORD 



Watt 

S~TC5P 



Z160 



BUSHEO 
8USACK 



»0,s 
»D„ 

«0„ 
AO,, 



AD, 
AO, 



AD, 
AD, 
AD, 



SN. 
SN, 
SN : 



m — r 

*iV QND CLK RiiJT 

Figure 1. Z160 CPU Pin Functions 



9 



hardware features; and compilers by multiple stacks, 
special instructions, and addressing modes. 

The Z160 is a segmented CPU (Figure 1). It can directly 
address 2 megabytes of memory. The two operating 
modes - system and normal - and the distinction between 



code, data, and stack spaces within each mode allows 
memory extension up to 12 megabytes. 

The Z160 is fabricated with high-density, high-perform- 
ance scaled n-channel silicon-gate depletion-load technol- 
ogy, and is housed in leadless chip carriers (LCC). 



REGISTER ORGANIZATION 

The Z1 60 CPU is a register-oriented machine that offers 

sixteen 1 6-bit general-purpose registers and a set of special 
system registers. All general-purpose registers can be used 
as accumulators and all but one as index registers or 
memory pointers. 

Register flexibility is created by grouping and overlapping 



multiple registers (Figures 2 and 3). For byte operations, the 
first eight 16-bit registers (R0... R7) are treated as sixteen 
8-bit registers (RLO, RHO..., RL7, RH7). The sixteen 16-bit 
registers are grouped in pairs (RRO... RR14) to form 32-bit 
long-word registers. Similarly, the register set is grouped in 
quadruples (RQO... RQ12) to form 64-bit registers. 



ne [TT 

A9 | 
R10 | 
R11 | 

R12 r~ 



R13 | 

R1 4 p 

fl« r~ 



R15 L 



SYSTEM STACK POINTER |SEG. NO.) 
NORMAL STACK POINTER {SEG. NO.) 



SYSTEM STACK POINTER (OFFSET) 



NORMAL STACK POINTER (OFFSET) 



Figure 2. Z160 General-Purpose Registers 



10 



STACKS 



The Z160 can use stacks located anywhere in memory. 
Call and Return instructions as well as interrupts and traps 
use implied stacks. The distinction between normal and 
system stacks separates system information from the 
application program information. Two stack pointers are 
available: the system stack pointer and the normal stack 
pointer. Because they are part of the general-purpose 



register group, the user can manipulate the stack pointers 
with any instruction available for register operations. 

The Z160 register pair RR14 is the implied stack pointer. 
Register R1 4 contains the 5-bit segment number and R1 5 
contains the 16-bit offset. 



REFRESH 



The Z160 CPU contains a counter that can be used to 
automatically refresh dynamic memory. The refresh 
counter register consists of a 9-bit row counter, a 6-bit rate 
counter, and an enable bit (Figure 4). The 9-bit row counter 
can address up to 256 rows and is incremented by two each 
time the rate counter reaches end-of-count. The rate 
counter determines the time between successive re- 
freshes. It consists of a programmable 6-bit modulo-n 



prescaler (n = 1 to 64), driven at one-fourth the CPU clock 
rate. The refresh period can be programmed by 1 to 64 fjs 
with a 4 MHz clock. Refresh can be disabled by program- 
ming the refresh enable/disable bit. 



-I L_ 



Figure 4. Refresh Counter 



PROGRAM STATUS INFORMATION 

This group of status registers contains the program counter, 
flags, and control bits. When an interrupt or trap occurs, the 
entire group is saved and a new program status group is 
loaded. 

Figure 5 illustrates the program status groups of the Z1 60. 
The program status group consists of four words: a two- 



word program counter, the flag and control word, and an 
unused word reserved for future use. Five bits of the first 
PC word designate one of the 32 memory segments. The 
second word supplies the 16-bit offset that designates a 
memory location within the segment. 



Ill I I FLAG AND 

I OA NO CONTROL 
I I I I I | WORD 



SEGMENT NUMBER 



SEGMENT OFFSET 
J I I I L. 



J L_ 



Z08001/Z160 Program Status Registers 



Z08001/Z160 Program Status Area Pointer 



Figure 5. Z160 CPU Special Registers 



11 



INTERRUPT AND TRAP STRUCTURE 



The Z160 provides a very flexible and powerful interrupt 
and trap structure. Interrupts are external asynchronous 
events requiring CPU attention and are generally triggered 
by peripherals needing service. Traps are sychronous 
events resulting from the execution of certain instructions. 
Both are processed in a similar manner by the CPU. 

The CPU supports three types of interrupts (non-mask- 
able, vectored, and non-vectored) and three traps [system 
call, Extended Process Architecture (EPA) instruction and 
privileged instructions]. The vectored and non-vectored in- 
terrupts are maskable. 

The traps occur when instructions limited to the system 
mode are used in normal mode, or as a result of the Sys- 
tem Call instruction, or for an EPA instruction. The des- 
cending order or priority for traps and interrupts is: internal 



traps, nonmaskable interrupt, vectored interrupt and non- 
vectored interrupt. 

When an interrupt or trap occurs, the current program status 
is automatically pushed on the system stack. The program 
status consists of the processor status (PC and FCW) plus a 
1 6-bit identifier. The identifier contains the reason or source 
of the trap or interrupt. For internal traps, the identifier is the 
first word of the trapped instruction. For external traps or 
interrupts, the identifier is the vector on the data bus read by 
the CPU during the interrupt-acknowledge or trap- 
acknowledge cycle. 

After saving the current program status, the new program 
status is automatically loaded from the program status area 
m system memory. This area is designated by the program 
status area pointer (PSAP). 



DATA TYPES 



Z160 instructions can operate on bits, BCD digits (4 bits), 
bytes (8 bits), words (1 6 bits), long words (32 bits), and byte 
strings and word strings (up to 64 kilobytes long). Bits can 
be set, reset, and tested; digits are used in BCD arithmetic 
operations; bytes are used for characters or small integer 
values; words are used for integer values, instructions and 
nonsegmented addresses; long words are used for long 
integer values and segmented addresses. All data ele- 



ments except strings can reside either in registers or 
memory. Strings are stored in memory only. 

The basic data element is the byte. The number of bytes 
used when manipulating a data element is either implied by 
the operation or— for strings and multiple register 
operations— explicitly specified in the instruction. 



SEGMENTATION AND MEMORY 
MANAGEMENT 



High-level languages, sophisticated operating systems, 
large programs and data bases, and decreasing memory 
prices are all accelerating the trend toward larger memory 
requirements in microcomputer systems. The Z1 60 meets 
this requirement with a two megabyte addressing space. 
This large address space is directly accessed by the CPU 
using a segmented addressing scheme. 



Segmented Addressing 

A segmented addressing space-compared with linear 
addressing-is closer to the way a programmer uses mem- 
ory because each procedure and data space resides in its 
own segment. The two megabytes of Z160 addressing 
space is divided into 32 relocatable segments up to 64 
kilobytes each. A 23-bit segmented address uses a 7-bit 
segment address to point to the segment, and a 16-bit 
offset to address any location relative to the beginning of 
the segment. The two parts of the segmented address may 
be manipulated separately. The segmented Z160 can run 
any code written for the nonsegmented Z8002 in any one 
of its 32 segments, provided it is set to the nonsegmented 
mode. 



LOGICAL ADDRESS I SEGMENT NO. 



rMEMORY 
| MANAGMENT 
UNIT 



BASE 
ADDRESS 
REGISTER 
FILE 




E3 



i 



24-BIT PHYSICAL ADDRESS 

— iT-j 1 



Figure 6. Logical-to-Physical Address 
Translation 



12 



In hardware, segmented addresses are contained in a 
register pair or long-word memory location. The segment 
number and offset can be manipulated separately or 
together by all the available word and long-word operations. 

When contained in an instruction, a segmented address 
has two different representations: long offset and short of- 



fset. The long offset occupies two words, whereas the short 
offset requires only one and combines in one word the 5- 
bit segment number with an 8-bit offset (range 0-256). The 
short offset mode allows very dense encoding of addres- 
ses and minimizes the need for long addresses required 
by direct accessing of this large address space. 



EXTENDED PROCESSING ARCHITECTURE 

TheZilog Extended Processing Architecture (EPA) provides 
an extremely flexible and modular approach to expanding 
both the hardware and software capabilities of the Z8000 
CPU. Features of the EPA include: 

■ Specialized instructions for external processors or 
software traps may be added to CPU instruction set. 

■ Increases throughput of the system by using up to four 
specialized external processors in parallel with the CPU. 

■ Permits modular design of Z8000-based systems. 

■ Provides easy management of multiple microprocessor 
configurations via "single instruction stream" 
communication. 

■ Simple interconnection between extended processing 
units and Z8000 CPU requires no additional external 
supporting logic. 

■ Supports debugging of suspect hardware against 

proven software. 

■ Standard features on all Zilog Z8000 CPUs. 
Specific benefits include: 

■ EPUs can be added as the system grows and as EPUs 
with specialized functions are developed. 

■ Control of EPUs is accomplished via a "single instruction 
stream" in the Z8000 CPU, eliminating many significant 
system software and bus contention management 
obstacles that occur in other multiprocessor (e.g., 
master-slave) organization schemes. 



The processing power of the Zilog Z8000 16-bit 
microprocessor can be boosted beyond its intrinsic 
capability by Extended Processing Architecture. Simply 
stated, EPA allows the Z8000 CPU to accommodate up to 
four Extended Processing Units (EPUs), which perform 
specialized functions in parallel with the CPU's main 
instruction execution stream (Figure 7). 

The use of extended processors to boost the main CPU's 
performance capability has been proven with large 
mainframe computers and minicomputers. In these 
systems, specialized functions such as array processing, 
special input/output processing, and data communications 
processing are typically assigned to extended processor 
hardware. These extended processors are complex 
computers in their own right. 

The Zilog Extended Processing Architecture combines the 
best concepts of these proven performance boosters with 
the latest in high-density MOS integrated-circuit design. The 
result is an elegant expansion of design capability— a 
powerful microprocessor architecture capable of 
connecting single-chip EPUs that permits very effective 
parallel processing and makes for a smoothly integrated 
instruction stream from the Z8000 programmer's point of 
view. A typical addition to the current Z8000 instruction set is 
a set of Floating Point Instructions. 

The Extended Processing Units connect directly to the 
Z8000 Bus (Z-BUS) and continuously monitor the CPU 
instruction stream. When an extended instruction is 
detected, the appropriate EPU responds, obtaining or 



13 



placing data or status information on the Z-BUS using the 
Z8000-generated control signals and performing its 
function as directed. 

The Z8000 CPU is responsible for instructing the EPU and 
delivering operands and data to it. The EPU recognizes 
instructions intended for it and executes them, using data 
supplied with the instruction and/or data within its internal 
registers. There are four classes of EPU instructions: 

■ Data transfers between main memory and EPU registers 

■ Data transfers between CPU registers and EPU registers 

■ EPU internal operations 

■ Status transfers between the EPUs and the Z8000 CPU 
Flag and Control Word register (FCW) 

Four Z8000 addressing modes may be utilized with 
transfers between EPU registers and the CPU and main 
memory: 

■ Register 

■ Indirect Register 

■ Direct Address 

■ Index 

In addition to the hardware-implemented capabilities of the 
Extended Processing Architecture, there is an extended 
instruction trap mechanism to permit software simulation of 
EPU functions. A control bit in the Z8000 FCW register 
indicates whether actual EPUs are present or not. If not, 
when an extended instruction is detected, the Z8000 traps 
on the instruction, so that a software "trap handler" can 
emulate the desired EPU function— a very useful 



development tool. The EPA software trap routine supports 
the debugging of suspect hardware against proven 
software. This feature will increase in significance as 
designers become familiar with the EPA capability of the 
Z8000 CPU. 

This software trap mechanism facilitates the design of 
systems for later addition of EPUs: initially, the extended 
function is executed as a trap subroutine; when the EPU is 
finally attached, the trap subroutine is eliminated and the 
EPA control bit is set. Application software is unaware of the 
change. 

Extended Processing Architecture also offers protection 
against extended instruction overlapping. Each EPU 
connects to the Z8000 CPU via the STOP line so that if an 
EPU is requested to perform a second extended instruction 
function before it has completed the previous one, it can put 
the CPU into the Stop/Refresh state until execution of the 
previous extended instruction is complete. 

EPA and CPU instruction execution are shown in Figure 8. 
The CPU begins operation by fetching an instruction and 
determining whether it is a CPU or an EPU command. The 
EPU meanwhile monitors the Z-BUS for its own instructions. 
If the CPU encounters an EPU command, it checks to see 
whether an EPU is present: if not. the EPU may be simulated 
by an EPU instruction trap software routine; if an EPU is 
present, the necessary data and/or address is placed on the 
Z-BUS. If the EPU is free when the instruction and data for it 
appear, the extended instruction is executed. If the EPU is 
still processing a previous instruction, it activates the CPU's 
STOP line to lock the CPU off at the Z-BUS until execution is 
complete. After the instruction is finished, the EPU 
deactivates the STOP line and CPU transactions continue. 



HI 



N | MEMORY 



rh-r 



DEDICATED 
EPU 



35 



E 



"h-n 



Z BUS COMPONENT INTERFACE 



En 



MEMORY 
MANAGEMENT 

UNIT 



35 



Figure 7. Typical Extended Processor Configuration 



14 




CPU GENERATES 
DATA/ADDRESS 
AND PLACES ON 




MONITOR Z-BUS 
INSTRUCTION 
STREAM 



EPU 
EXECUTES 
INSTRUCTION 




A DATA OR ADDRESSES ARE PLACED ON THE BUS AND USED BY THE EPU IN THE 
EXECUTION OF AN INSTRUCTION. 



Figure 8. EPA and Z8000 CPU Instruction Execution 



INPUT/OUTPUT 



A set of I/O instructions performs 8-bit or 16-bit transfers 
between the CPU and I/O devices. I/O devices are 
addressed with a 16-bit I/O port address. The I/O port 
address is similar to a memory address; however, I/O 
address space need not be part of the memory address 
space. I/O port and memory addresses coexist on the same 
bus lines and they are distinguished by the status outputs. 



Two types of I/O instructions are available: standard and 
special. Each has its own address space. The I/O 
instructions include a comprehensive set of In, Out, and 
Block I/O instructions for both bytes and words. Special I/O 
instructions are used for loading and unloading the Memory 
Management Unit. The status information distinguishes 
between standard and special I/O references. 



MULTI-MICROPROCESSOR SUPPORT 

Multi-microprocessor systems are supported in hardware 
and software. A pair of CPU pins is used in conjunction with 
certain instructions to coordinate multiple microprocessors. 
The Multi-Micro Out pin issues a request for the resource, 
while the Multi-Micro In pin is used to recognize the state of 
the resource. Thus, any CPU in a multiple microprocessor 
system can exclude all other asynchronous CPUs from a 
critical shared resource. 



Multi-microprocessor systems are supported in software by 
the instructions Multi-Micro Request, Test Multi-Micro In, Set 
Multi-Micro Out, and Reset Multi-Micro Out. In addition, the 
eight megabyte CPU address space is beneficial in multiple 
microprocessor systems that have large memory 
requirements. 



15 



ADDRESSING MODES 



The information included in Z8000 instructions consists of 
the function to be performed, the type and size of data 
elements to be manipulated, and the location of the data 
elements. Locations are designated by register addresses, 
memory addresses, or I/O addresses. The addressing 
mode of a given instruction defines the address space it 
references and the method used to compute the address 
itself. Addressing modes are explicitly specified or implied 
by the instruction. 



Figure 9 illustrates the eight addressing modes: Register 
(R), Immediate (IM), Indirect Register (IR), Direct Address 
(DA), Index (X), Relative Address (RA), Base Address (BA), 
and Base Index (BX). In general, an addressing mode 
explicitly specifies either register address space or memory 
address space. Program memory address space and I/O 
address space are usually implied by the instruction. 



Addressing Mode 



Operand Addressing 



Operand Value 



In the Instruction In a Register 



Register 



REGISTER AOORESS I OPERANO 



H. 



The content of the 
register 



IN 



Immediate I OPERAND 1 



In the instruction 



IR 



Indirect 
Register 



| REGISTER AODRESS [ — - j A0ORESs"| - 



» | OPERAN0~] 



The content of the location 
whose address is in the 



DA 



Direct 
Address 



| address | — 



The content oi the location 
whose address is in the 

instruction 



Index 



register address 



BASE ADORESS 



»» | operand""] 



The content of the loca- 
tion whose address is the 
address in the instruction 
plus the content ot the 
working register. 



Relative r- 
Address [_ 



DISPLACEMENT 



3— L, . 

**Gy "i 0PERAND I 



The content of the location 
whose address is the 
content of the program 
counter, offset by the 
displacement in the 
instruction 



BA 



Base 
Address 



REGISTER AODRESS 



H 



DISPLACEMENT 



BASE AODRESS 



» f OPERANo""| 



The content of the location 
whose address is the 
address in the register, 
offset by the displacement 
in the instruction 



BX 



Base 
Index 



REGISTER ADDRESS 



REGISTER AODRESS 



BASE ADDRESS 



3- 



The content of the loca- 
tion whose address is 
the address in a register 
plus the index value in 
another register. 



"Do not use RO or RRO as indirect, index, or base registers. 

Figure 9. Addressing Modes 



16 



INSTRUCTION SET SUMMARY 

The Z8000 provides the following types of instructions: 

■ Load and Exchange 

■ Arithmetic 

■ Logical 

■ Program Control 



LOAD AND EXCHANGE 



Bit Manipulation 
Rotate and Shift 

Block Transfer and String Manipulation 

InpuVOutput 

CPU Control 



Clock Cycles* 
Addr. Word, Byte Long Word 



Mnemonics 


Operands 


Modes 


NS 


SS 


SL NS SS SL 


Operation 


CLR 


dst 


R 


7 


7 


7 


Clear 


CLRB 




IR 


8 


8 


8 


dst— 






DA 


11 


12 


14 








X 


12 


12 


15 . 




EX 


R. src 


R 


6 


6 


6 


Exchange 


EXB 




IR 


12 


12 


12 


R — src 






DA 


15 


16 


18 








X 


16 


16 


19 





LD 


R, src 


R 


3 


3 


3 


5 


5 


5 


Load into Register 


LDB 




IM 


7 


7 


7 


11 


11 


11 


R — src 


LDL 




IM 


5 (byte only) 
















IR 


7 


7 


7 


11 


11 


11 








DA 


9 


10 


12 


12 


13 


15 








X 


10 


10 


13 


13 


13 


16 








BA 


14 


14 


14 


17 


17 


17 








BX 


14 


14 


14 


17 


17 


17 




LO 


dst. R 


IR 


8 


8 


8 


11 


11 


11 


Load into Memory (Store) 


LDB 




DA 


11 


12 


14 


14 


15 


17 


dst — R 


LDL 




X 


12 


12 


15 


15 


15 


18 








BA 


14 


14 


14 


17 


17 


17 








BX 


14 


14 


14 


17 


17 


11 





LD 


dst. IM 


IR 


11 


11 


11 


Load Immediate into Memory 


LDB 




DA 


14 


15 


17 


dst - IM 






X 


15 


15 


18 




LDA 


R. src 


DA 


12 


13 


15 


Load Address 






X 


13 


13 


16 


R — source address 






BA 


15 


15 


15 








BX 


15 


15 


15 




LDAR 


R. src 


RA 


15 


15 


15 


Load Address Relative 














R — source address 


LDK 


R. src 


IM 


5 


5 


5 


Load Constant 














R — n (n = 0... 15) 


LDM 


R. src, n 


IR 


11 


11 


11 + 3n 


Load Multiple 






DA 


14 


15 


17 + 3n 


R — src (n consecutive words) 






X 


15 


15 


18 + 3n 


(n = 1... 16) 



*NS = Non-segmented SS = Segmented Short Offset SL = Segmented Long Offset 



LOAD AND EXCHANGE (Continued) 



Clock Cycles* 
Addr. Word, Byte Long Word 



Mnemonics Operands 


Modes 


NS 


SS 


SL NS 


SS 


SL 


Operation 


LDM 


dst. R, n 


IR 


11 


11 


11 + 3n 






Load Multiple (Store Multiple) 








1 A 




I / + on 






ubi ^ n 1,11 curibcuiHivt; wurub; 






X 


15 


15 


18 + 3n 






(n = 1... 16) 


LOR 


R, src 


RA 


14 


14 


14 17 


17 


17 


Load Relative 


LORB 
















R — src 


LDHL 
















franco T?7Rfl -l. T97fi7\ 


LOR 


dst. R 


RA 


14 


14 


14 17 


17 


17 


Load Relative (Store Relative) 


LORB 
















dst-R 


LDRL 
















(range -32768... +32767) 


POP 


dst, IR 


R 


8 


8 


8 12 


12 


12 


Pop 


POPL 




IR 


12 


12 


12 19 


19 


19 


dst-IR 






DA 


16 


16 


18 23 


23 


25 


Autoincrement contents of R 






X 


16 


16 


19 23 


23 


26 




PUSH 


IR, src 


R 


9 


9 


9 12 


12 


12 


Push 


PUSHL 




IM 


12 


12 


12 19 


19 


19 


Autodecrement contents of R 






IR 


13 


13 


13 20 


20 


20 


IR — src 






DA 


14 


14 


16 21 


21 


23 








X 


14 


14 


17 21 


21 


24 




ARITHMETIC 


ADC 


R, src 


R 


5 


5 


5 






Add with Carry 


ADCB 
















R *■ R + src + carry 


ADD 


R, src 


R 


4 


4 


4 8 


8 


8 


Add 


ADDB 




IM 


7 


7 


7 14 


14 


14 


R — R + src 


ADDL 




IR 


7 


7 


7 14 


14 


14 








DA 


9 


10 


12 15 


16 


18 








X 


10 


10 


13 16 


16 


19 




CP 


R, src 


R 


4 


4 


4 8 


8 


8 


Compare with Register 


CPB 




IM 


7 


7 


7 14 


14 


14 


R - src 


CPL 




IR 


7 


7 


7 14 


14 


14 








DA 


9 


10 


12 15 


16 


18 








X 


10 


10 


13 16 


16 


19 




CP 


dst. IM 


IR 


11 


11 


11 






Compare with Immediate 


CPB 




DA 


14 


15 


17 






dst - IM 






X 


15 


15 


18 








DAB 


dst 


R 


5 


5 


5 






Decimal Adjust 


DEC 


dst, n 


R 


4 


4 


4 






Decremented by n 


DECB 




IR 


11 


11 


11 






dst *- dst - n 






DA 


13 


14 


16 






(n = 1... 16) 






X 


14 


14 


17 









•NS - Non-segmented SS = Segmented Short Offset SL - Segmented Long Offset 



18 



ARITHMETIC (Continued) 



Clock Cycles* 
Addr. Word, Byte Long Word 



mnemonics wpeitiiius 


Modes 


NS 


SS 


SL 


NS 


SS 


SL 


One ration 


DIV R, src 


R 


107 


107 


107 


744 


744 


744 


Divide (signed) 


DIVL 


IM 


107 


107 


107 


744 


744 


744 


Word: R n + 1 — R n ,n + 1 + src 




ID 

In 


107 


107 


1 U/ 


744 


7 A A 
1 44 


744 


R n *" remainder 




UA 


1 no 


iuy 


111 


/ 40 




TAQ 


Long Word: R n + 2,n+3*'" R n... n+3 + src 




X 


109 


109 


112 


746 


746 


749 


Rn n + 2 *~ remainder 

1 1, II T t 


EXTS dst 


H 


1 1 


1 1 


1 1 


1 1 


1 1 


1 1 


Extend Sign 


EXTSB 
















Extend sign of low order half of dst 


EXT5L 
















through high order halt ot dst 


INC dst. n 


R 


4 


4 


4 








Increment by n 


INCB 


IR 


11 


11 


11 








dst — dst + n 




UA 


1 o 


1 4 










/n — 1 1 CZ\ 

(n = i .., io) 




X 


14 


14 


1 7 










MULT R, src 


R 


70 


70 


70 


282t 


282t 


282t 


Multiply (signed) 


MULTL 


IM 


70 


70 


70 


282t 


282t 


282t 


Word:R nn + 1 -R n + 1 • src 




IR 


70 


70 


70 


282t 


2821" 


2821" 


Long Word. R n n + 3 ~ Rn+2,n + 3 




DA 


71 


72 


74 


283t 


284 1 


2861" 


tPlus seven cycles for each 1 in the 




X 


72 


72 


75 


284t 


284t 


287t 


multiplicand 


NEG dst 


R 


7 


7 


7 








Negate 


NEGB 


IR 


12 


1 2 


12 








dst *- - dst 




DA 


15 


16 


18 












X 


16 


16 


19 










SBC R, src 


R 


5 


5 


5 








Subtract with Carry 


SBCB 
















R — R - src - carry 


SUB R, src 


R 


4 


4 


4 


8 


8 


8 


Subtract 


SUBB 


IM 


7 


7 


7 


14 


14 


14 


R — R - src 


SUBL 


IR 


7 


7 


7 


14 


14 


14 






DA 


9 


10 


12 


15 


16 


18 






X 


10 


10 


13 


16 


16 


19 




LOGICAL 


AND R, src 


R 


4 


4 


4 








AND 


ANDB 


IM 


7 


7 


7 








R — R AND src 




IR 


7 


7 


7 












DA 


9 


10 


12 












X 


10 


10 


13 










COM dst 


R 


7 


7 


7 








Complement 


COMB 


IR 


12 


12 


12 








dst — NOT dst 




DA 


15 


16 


18 












X 


16 


16 


19 










OR R, src 


R 


4 


4 


4 








OR 


ORB 


IM 


7 


7 


7 








R — R OR src 




IR 


7 


7 


7 












DA 


9 


10 


12 












X 


10 


10 


13 










"NS = Non-segmented SS = Segmented Short Offset 


SL = 


Segmented Long Offset 







19 



LOGICAL (Continued) 



Clock Cycles* 
Addr. Word, Byte Long Word 



Mnemonics 


Operands 


Modes 


NS 


ss 


SL 


NS 


SS 


SL 


Operation 


TCC 


cc, dst 


R 


5 


5 


5 








lest condition uode 


TCCB 


















Set LSB if cc is true 


TEST 


dst 


R 


7 


7 


7 


13 


13 


13 


Test 


TESTB 




IR 


8 


8 


8 


13 


13 


13 


dst OR 


TESTL 




DA 


11 


12 


14 


16 


17 


19 








X 


12 


12 


15 


17 


17 


20 




XOR 


R, src 


R 


4 


4 


4 








Exclusive OR 


XORB 




IM 


7 


7 


7 








R - R XOR src 






IR 


7 


7 


7 














DA 


9 


10 


12 














X 


10 


10 


13 











PROGRAM CONTROL 



CALL 


dst 


IR 
DA 

X 


10 
12 
13 


15 
18 
18 


15 
20 
21 




Call Subroutine 

Autodecrement SP 
@ SP *- PC 
PC - dst 


CALR 


dst 


RA 


10 


10 


15 




Call Relative 

Autodecrement SP 
@ SP - PC 

rt*^ru + dst (range — 4U»4 to + 4uyt>j 


DJNZ 
DBJNZ 


R, dst 


RA 


11 


11 


11 




Decrement and Jump if Non-Zero 

R-R- 1 

If R * 0: PC-PC + dst(range - 254 to 9) 


IRETt 






13 


13 


16 




Interrupt Return 

PS - @ SP 
Autoincrement SP 


JP 


cc. dst 


IR 
IR 
DA 

X 


10 

7 
7 
8 


10 
7 
8 
8 


15 
7 
10 
11 


(taken) 
(not taken) 


Jump Conditional 

Ifcc is true: PC — dst 


JR 


cc, dst 


RA 


6 


6 


6 




Jump Conditional Relative 

If cc is true: PC — PC + dst 
(range - 256 to + 254) 


RET 


cc 




10 

7 


10 

7 


13 
7 


(taken) 
(not taken) 


Return Conditional 

Ifcc is true: PC — @ SP 

Autoincrement SP 


SC 


src 


IM 


33 


33 


39 




System Call 

Autodecrement SP 
@ SP — old PS 
Push instruction 
PS — System Call PS 



•NS = Non-segmented SS - Segmented Short Offset SL = Segmented Long Offset 
tPrivileged instruction. Executed in system mode only 



20 



BIT MANIPULATION 



Clock Cycles* 







Addr. 


Word, Byte 


Long Word 




IV" IICI l IUI MvO 


Operands 


Modes 


NS 


SS 


SL NS SS SL 


Operation 


BIT 


dst, b 


R 


4 


4 


4 


Test Bit Static 


Dl 1 D 




IP 


8 


8 


8 


Z flag ** NOT dst bit specified by b 






DA 


10 


1 1 


13 








x 


11 


11 


14 




BIT 


dst, R 


R 


10 


10 


10 


Test Bit Dynamic 


Dl 1 D 












7 flnn *— MOT rlct hit Qrwacifip/H hv 














contents of R 


RES 


dst, b 


Q 

n 


4 


4 


A 


Qacat Bit Ctatic 

riesei dii oiaiic 






IP 
in 


■t i 
i i 


■j ■] 


-| -| 










13 


14 


1 R 
I O 








X 


14 


14 


17 




RES 


dst, R 


Q 

n 


10 


10 


1 n 


rfeSei Dii uynamit 


RESB 












Reset dst bit specified by contents R 


SET 


dst, b 


R 


4 


A 

(| 


4 


Set oit static 


SETB 




ID 

In 


1 1 


1 1 


1 1 


Set dst bit specified by b 






DA 


13 


14 


1 6 








X 


14 


14 


17 




SET 


dst, R 


R 


10 


10 


10 


Set Bit Dynamic 


SETB 












Set dst bit specified by contents of R 


TSET 


dst 


R 


7 


7 


7 


Test and Set 


TSETB 




IR 


11 


11 


11 


S flag — MSB of dst 






DA 


14 


15 


17 


dst — all 1s 






X 


15 


15 


18 





ROTATE AND SHIFT 



RL 


dst, n 


R 


6 for n = 1 


Rotate Left 


RLB 




R 


7 for n = 2 


by n bits (n = 1,2) 


RLC 


dst. n 


R 


6 for n = 1 


Rotate Left through Carry 


RLCB 




R 


7forn = 2 


by n bits (n = 1,2) 


RLDB 


R, sre 


R 


9 9 9 


Rotate Digit Left 


RR 


dst, n 


R 


6 for n = 1 


Rotate Right 


RRB 




R 


7forn = 2 


by n bits (n = 1,2) 


RRC 


dst, n 


R 


6 for n = 1 


Rotate Right through Carry 


RRCB 




R 


7 for n = 2 


by n bits (n = 1,2) 


RRDB 


R. sre 


R 


9 9 9 


Rotate Digit Right 


SDA 


dst, R 


R 


(15 + 3n) (15 + 3n) 


Shift Dynamic Arithmetic 


SDAB 








Shift dst left or right by 


SDAL 








contents of R 


SDL 


dst, R 


R 


(15 + 3n) (15 + 3n) 


Shift Dynamic Logical 


SDLB 








Shift dst left or right by 


SDLL 








contents of R 


•NS = Non-segmented 


SS = 


Segmented Short Offset SL - Segmented Long Offset 





21 



ROTATE AND SHIFT (Continued) 



Mnemonics 


Operands 


Addr. 
Modes 


Clock Cycles* 
Word, Byte Long Word 
NS SS SL NS SS SL 


Operation 


OLM 

SLAB 
SLAL 




r 


(13 + 3 n) 


(1 o + o n) 


Shift Left Arithmetic 

by n bits 


SLLB 
SLLL 


dst, n 


D 

n 


(13 + 3 n) 


(13 + 3 n) 


Shift Left Lonical 

by n bits 


SRAB 
SRAL 


dst. n 


n 


(13 + 3n) 


(13 + 3n) 


^hift Rinht Arithmetic 

by n bits 


SRL 

SRLB 

SRLL 


dst, n 


R 


(13 + 3n) 


(13 + 3n) 


Shift Right Logical 

by n bits 


BLOCK TRANSFER AND STRING MANIPULATION 


CPD 
CPDB 


R x ,src,Ry,cc 


IR 


20 20 20 




Compare and Decrement 

Rx - src 

Autodecrement src address 
R Y — Ry - 1 


CPDR 
CPDRB 


Rx.src.Ry.cc 


IR 


(11 + 9n) 




Compare, Decrement, and Repeat 

Rx - src 

Autodecrement src address 
Ry — Ry - 1 

Repeat until cc is true or Ry = 


CPI 
CPIB 


Rx.src.Ry.cc 


IR 


20 20 20 




Compare and Increment 

Rx - src 

Autoincrement src address 
Ry — Ry - 1 


CPIR 
CPIRB 


Rx.src.Ry.cc 


IR 


(11 + 9n) 




Compare, Increment, and Repeat 

Rx - src 

Autoincrement src address 
Ry — Ry - 1 

Repeat until cc is true or Ry = 


CPSD 
CPSDB 


dst.src.R.cc 


IR 


25 25 25 




Compare String and Decrement 

dst - src 

Autodecrement dst and src addresses 
R~R - 1 


CPSDR 
CPSDRB 


dst.src.R.cc 


IR 


(11 + 14 n) 




Compare String, Decrement, and 
Repeat 

dst - src 

Autodecrement dst and src addresses 
R-R - 1 

Repeat until cc is true or R = 



*NS = Non-segmented SS = Segmented Short Offset SL = Segmented Long Offset 



22 



BLOCK TRANSFER AND STRING MANIPULATION (Continued) 



Clock Cycles* 
Addr. Word, Byte Long Word 

Mnemonics Operands Modes NS SS SL NS SS SL 



CPSI 
CPSIB 



dst,src,R.cc IR 25 25 25 



Operation 

Compare String and Increment 

dst - src 

Autoincrement dst and src addresses 
R-R - 1 



CPSIR 
CPSIRB 



dst.src.R.cc IR (11 + 14 n) 



Compare String, Increment and 
Repeat 

dst - src 

Autoincrement dst and src addresses 
R-R - 1 

Repeat until cc is true or R = 



LDD 
LDDB 



dst.src.R 



IR 



20 20 20 



Load and Decrement 

dst — src 

Autodecrement dst and src addresses 
R-R - 1 



LODR 
LDDRB 



dst.src.R 



IR 



(1 1 + 9 n) 



Load, Decrement and Repeat 

dst — src 

Autodecrement dst and src addresses 
R-R - 1 
Repeat until R = 



LDI 
LDIB 



dst.src.R 



IR 



20 20 20 



Load and Increment 

dst — src 

Autoincrement dst and src 
R-R - 1 



LDIR 
LDIRB 



dst.src.R 



IR 



(11 + 9 n) 



Load, Increment and Repeat 

dst — src 

Autoincrement dst and src addresses 
R-R - 1 
Repeat until R = 



TRDB 



dst.src.R IR 25 25 25 



Translate and Decrement 

dst — src (dst) 
Autodecrement dst address 
R-R - 1 



TRDRB 



dst.src.R IR (11 + 14 n) 



Translate, Decrement and 

dst — src (dst) 
Autodecrement dst address 
R-R - 1 
Repeat until R = 



TRIB 



it.src.R IR 25 25 25 



Translate and Increment 

dst — src (dst) 
Autoincrement dst address 
R-R - 1 



•NS = Non-segmented SS = Segmented Short Offset SL = Segmented bong Offset 
■Privileged instruction. Executed in system mode only. 



23 



BLOCK TRANSFER AND STRING MANIPULATION (Continued) 



Clock Cycles* 
Addr. Word, Byte Long Word 

Mnemonics Operands Modes NS SS SL NS SS SL Operation 

TRIRB dst.src.R IR (11 + 14 n) Translate, Increment and Repeat 

dst — src (dst) 
Autoincrement dst address 
R-R - 1 
Repeat until R = 

TRTDB srd.src2.R IR 25 25 25 Translate and Test, Decrement 

RH1 -src2(srd) 
Autodecrement src 1 address 
R-R - 1 

TRTDRB srd.src2,R IR (11 + 14 n) Translate and Test, Decrement, and 

Repeat 

RH1 -src2(srd) 
Autodecrement src 1 address 
R-R - 1 

Repeat until R = OorRHI = 

TRTIB srd,src2,R IR 25 25 25 Translate and Test, Increment 

RH1 -src2(src1) 
Autoincrement srd address 
R-R - 1 

TRTIRB srd,src2.R IR (11 + 1 4 n) Translate and Test, Increment and 

Repeat 

RH1 -src2(src1) 
Autoincrement src 1 address 
R-R - 1 

Repeat until R = OorRHI =0 



INPUT/OUTPUT 



INt 
INBT 


R.src 


IR 
DA 


10 10 10 
12 12 12 


Input 

R — src 


INDt 
INDBt 


dst.src.R 


IR 


21 21 21 


Input and Decrement 

dst — src 

Autodecrement dst address 
R-R - 1 


INDRt 
INDRBt 


dst.src.R 


IR 


(11 + 10 n) 


Input, Decrement and Repeat 

dst — src 

Autodecrement dst address 
R -R - 1 
Repeat until R = 


INIt 


dst.src.R 


IR 


21 21 21 


Input and Increment 



INIBt dst -src 

Autoincrement dst address 
R-R - 1 



"NS = Non-segmented SS = Segmented Short Offset SL = Segmented Long Offset 

privileged instruction Executed in system mode only. 



24 



INPUT/OUTPUT (Continued) 



Clock Cycles* 
Addr. Word, Byte Long Word 



Mnemonics 


Operands 


Modes 


NS SS SL NS S 


S SL 


Operation 


INIRt 
INIRBt 


dst.src.R 


IR 


(11 + 10 n) 




Input, Increment and Repeat 

dst — src 

Autoincrement dst address 
R-R - 1 
Repeat until R = 


OUTt 
OUTBt 


dst.R 


IR 
DA 


10 10 10 
12 12 12 




Output 

dst-R 


OUTDt 
OUTDBt 


dst.src.R 


IR 


21 21 21 




Output and Decrement 

dst — src 

Autodecrement src address 
R-R - 1 


OTDRt 
OTDRBt 


dst.src.R 


IR 


(11 + 10 n) 




Output, Decrement and Repeat 

dst — src 

Autodecrement src address 
R-R - 1 
Repeat until R = 


OUTIt 
OUTIBt 


dst.src.R 


IR 


21 21 21 




Output and Increment 

dst — src 

Autoincrement src address 
R — R - 1 


OTIRt 
OTIRBt 


dst.src.R 


IR 


(11 + 10 n) 




Output, Increment, and Repeat 

dst *- src 

Autoincrement src address 
R-R - 1 
Repeat until R = 


SINt 
SINBt 


R.src 


DA 


12 12 12 




Special Input 

R — src 


SINDt 
SINDBt 


dst.src.R 


IR 


21 21 21 




Special Input and Decrement 

dst — src 

Autodecrement dst address 
R-R - 1 


SINDRt 


dst.src.R 


IR 


11 + 10 n) 




Special Input, Decrement, and 



SINDRBt Repeat 

dst — src 

Autodecrement dst address 
R-R - 1 
Repeat until R = 

SINIt dst.src.R IR 21 21 21 Special Input and Increment 

SINIBt dst - src 

Autoincrement dst address 
R-R - 1 

•NS = Non-segmented SS = Segmented Short Offset SL = Segmented Long Offset 

tPrivileged instruction. Executed in system mode only. 



25 



INPUT/OUTPUT (Continued) 



Clock Cycles* 
Addr. Word, Byte Long Word 



Mnemonics 


Operands 


Modes 


NS SS 


SL NS SS SL 


Operation 


SINIRt 
SINIRBt 


dst.src.R 


IR 


(11 + 10n) 




Special Input, increment, and 

Repeat 
dst — src 

Automcrement dst address 
R ■*- R - 1 
Repeat until R = 


SOUTt 
SOUTBt 


dst.src 


DA 


12 12 


12 


Special Output 

dst *- src 


SOUTDt 
SOUTDBt 


dst.src.R 


IR 


21 21 


21 


Special Output and Decrement 

dst *- src 

Autodecrement src address 
R-R - 1 


SOTDRt 
SOTDRBt 


dst.src.R 


IR 


(11 + 10n) 




Special Output, Decrement, and 

Repeat 
dst — src 

Autodecrement src address 
R-R - 1 
Repeat until R = 


SOUTIt 
SOUTIBt 


dst.src.R 


IR 


21 21 


21 


Special Output and Increment 

dst — src 

Automcrement src address 
R-R - 1 


SOTIRt 
SOTIRBt 


dst.src.R 


R 


(11 + 10 n) 




Special Output, Increment, and 

Repeat 
dst — src 

Autoincrement src address 
R -R - 1 
Repeat until R = 


CPU CONTROL 


COMFLG 


flags 




7 7 


7 


Complement Flag 

(Any combination of C, Z. S. PA/) 


Dlt 


int 




7 7 


7 


Disable Interrupt 

(Any combination of NVI, VI) 


Elt 


int 




7 7 


7 


Enable Interrupt 

(Any combination of NVI, VI) 


HALTt 






(8 + 3 n) 




HALT 


LDCTLt 


CTLR.src 


R 


7 7 


7 


Load into Control Register 

CTLR — src 


LDCTLt 


dst.CTLR 


R 


7 7 


7 


Load from Control Register 

dst - CTLR 



" NS = Non-segmented SS = Segmented Short Offset SL - Segmented Long Offset 
T Pnvileged instruction. Executed in system mode only. 



26 



CPU CONTROL (Continued) 



Mnemonics 


Operands 


Addr. 
Modes 


\ 

NS 


Clock Cycles* 
Void, Byte Long Word 
SS SL NS SS SL 


Operation 


LDCTLB 


FLGR.src 


R 


7 


7 


7 


Load Into Flag Byte Register 

FLGR — src 


LDCTLB 


dst.FLGR 


R 


7 


7 


7 


Load from Flag Byte Register 

dst - FLGR 


LDPSt 


src 


IR 
DA 

Y 
A 


12 
16 


16 
20 
20 


16 

22 
23 


Load Program Status 

PS — src 


UDlTt 

MBI 1 






7 


7 


7 


Tact Mi lit i Uirrn Bit 

lesi niu ill- Micro on 

Set S if Ml is Low; reset S if Ml is High 


MREQt 


dst 


R 




(12 + n) 




Multi-Micro Request 


MRESt 






5 


5 


5 


Multi-Micro Reset 


MSETt 


- 


- 


5 


7 


7 


Multi-Micro Set 


NOP 






7 


7 


7 


No Operation 


RESFLG 


flag 




7 


7 


7 


Reset Flag 

(Any combination of C. Z, S. PA/) 


SETFLG 


flag 




7 


7 


7 


Set Flag 

(Any combination of C, Z. S. PA/) 



- NS = Non-segmented SS = Segmented Short Offset SL = Segmented Long Offset 
^Privileged instruction. Executed in system mode only. 



27 



CONDITION CODES 



Code 


Meaning 


Flag Settings 


CC Field 


F 


Always false 




0000 


T 


Always true 




1000 


z 


Zero 


Z = 1 


0110 


NZ 


Not zero 


Z = 


1110 


c 


Carry 


C = 1 


0111 


NC 


No Carry 


C = 


1111 


PL 


Plus 


S = 


1101 


Ml 


Minus 


S = 1 


0101 


NE 


Not equal 


Z = 


1110 


EQ 


Equal 


Z = 1 


01 10 


OV 


Overflow 


P/V = 1 


0100 


NOV 


No overflow 


P/V = 


1 100 


PE 


Parity is even 


PA/ = 1 


0100 


PO 


Parity is odd 


P/V = 


1 100 


GE 


Greater than or equal (signed) 


(S XOR P/V) = 


1001 


LT 


Less than (signed) 


(S XOR P/V) = 1 


0001 


GT 


Greater than (signed) 


[Z OR (S XOR PA/)) = 


1010 


LE 


Less than or equal (signed) 


[Z OR (S XOR PA/)] = 1 


0010 


UGE 


Unsigned greater than or equal 


C = 


1111 


ULT 


Unsigned less than 


C = 1 


0111 


UGT 


Unsigned greater than 


[(C = 0)AND(Z = 0)] = 1 


1011 


ULE 


Unsigned less than or equal 


(C OR Z) = 1 


0011 


Note that some condition codes have identical flag settings and binary fields in the instruction 




Z = EQ, NZ = NE. C = ULT, NC = UGE. OV =. PE. NOV = PO 






STATUS CODE LINES 


Note: A full list of instructions and cycle times is contained 






in the Z8000 data manual. 




ST -ST 3 


Definition 






0000 


Internal operation 






0001 


Memory refresh 






0010 


I/O reference 






0011 


Special I/O reference (e.g.. to an MMU) 






0100 


Segment trap acknowledge 






0101 


Non-maskable interrupt acknowledge 






0110 


Non-vectored interrupt acknowledge 






0111 


Vectored interrupt acknowledge 






1000 


Data memory request 






1001 


Stack memory request 






1010 


Data memory request (EPU) 






1011 


Stack memory request (EPU) 






1100 


Program reference, nth word 






1101 


Instruction fetch, first word 






1110 


Extension processor transfer 






1111 


Reserved 







28 



PIN DESCRIPTION 



AD -AD 15 . Address/Data (inputs/outputs, active High, 
3-state). These multiplexed address and data lines are used 
for I/O and to address memory. 

AS. Address Strobe (output, active Low, 3-state). The rising 
edge of AS indicates addresses are valid. 

BUSACK. Bus Acknowledge (output active Low). A Low on 
this line indicates the CPU has relinquished control of the 

bus. 

BUSREQ. Bus Request (input, active Low). This line must 
be driven Low to request the bus from the CPU. 

B/W. ByteAVord (output, Low = Word, 3-state). This signal 
defines the type of memory reference on the 16-bit 
address/data bus. 

CLK. System Clock (input). CLK is a 5V single-phase 
time-base input. 

DS. Data Strobe (output, active Low, 3-state). This line times 
the data in and out of the CPU. 

MREQ. Memory Request (output, active Low, 3-state). A 
Low on this line indicates that the address/data bus holds a 
memory address. 

Ml, MO. Multi-Micro In, Multi-Micro Out (input and output, 
active Low). These two lines form a resource- request daisy 
chain that allows one CPU in a multi-microprocessor system 
to access a shared resource. 

NMI. Non-Maskable Interrupt (edge trig gered , input, active 
Low). A high-to-low transition on NMI requests a 



non-maskable interrupt. The NMI interrupt has the highest 
priority of the three types of interrupts. 

N/S. Normal/System Mode (output, Low = System Mode, 
3-state). N/S indicates the CPU is in the normal or system 
mode. 

NVI. Non-Vectored Interrupt (input, active Low). A Low on 
this line requests a non-vectored interrupt. 

RESET. Reset (input, active Low). A Low on this line resets 
the CPU. 

R/W. Read/Write (output, Low = Write, 3-state). R/W 
indicates that the CPU is reading from or writing to memory 
or I/O. 

SN0-SN4. Segment Number (outputs, active High, 3- 
state). These lines provide the 5-bit segment number used 
to address one of 32 segments. 

ST0-ST3. Status (outputs, active High, 3-state). These lines 
specify the CPU status (see Status Code Lines). 

STOP. Stop (input, active Low). This input can be used to 
single-step instruction execution. 

VI. Vectored Interrupt (input, active Low). A Low on this line 
requests a vectored interrupt. 

WAIT. Wait (input, active Low). This line indicates to the CPU 
that the memory or I/O device is not ready for data transfer. 



29 





f 


5T0P 




Ml 




ADis 








♦ 5V 


11 


Vi 


12 


NVi 


13 


Nfifi 


14 


Iset 


15 


MO 


16 


MREO 


17 







6 5 4 3 2 



44 43 42 41 40 



Z160 
CPU 



18 19 20 21 22 23 24 25 26 27 28 









AD5 


38 


AOs 


37 


AD2 






35 


SNj 


34 


GND 


33 


CLK 


32 


AS 


31 


B/W 


30 


N/S 


29 




/ 





Figure 10b. 44-pin PLCC, Pin Assignments 



Z160 CPU TIMING 

The Z 1 6 CPU executes instructions by stepping through 
sequences of basic machine cycles, such as memory read 
or write, I/O device read or write, interrupt acknowledge, 
and internal execution. Each of these basic cycles requires 
three to ten clock cycles to execute. Instructions that re- 
quire more clock cycles to execute are broken up into 
several machine cycles. Thus no machine cycle is longer 
than ten clock cycles and fast response to a Bus Request 
is guaranteed. 

The instruction opcode is fetched by a normal memory read 
operation. A memory refresh cycle can be inserted just after 
the completion of any first instruction fetch (IF t ) cycle and 
can also be inserted while the following instructions are 
being executed: MULT, MULTL, DIV, DIVL, HALT, all Shift 
instructions, all Block Move instructions, and the Multi-Micro 



Request instruction (MREQ). 

The following timing diagrams show the relative timing 
relationships of all CPU signals during each of the basic 
operations. When a machine cycle requires additional clock 
cycles for CPU internal operation, one to five clock cycles 
are added. Memory and I/O read and write, as well as 
interrupt ac knowle dge cycles, can be extended by 
activating the WAIT input. For exact timing information, refer 
to the composite timing diagram. 

Note that the WAIT input is not synch ronize d in the Z160 
and that the setup and hold times for W AIT, re lative to the 
clock, must be met. If asynchronous WAIT signals are 
generated, they must be synchronized with the CPU clock 
before entering the Z 160 . 



30 



MEMORY READ AND WRITE 



Memory read and instruction fetch cycles are identical, ex- 
cept for the status information on the ST0-ST3 outputs. 
During a memory read cycle, a 1 6-bit address is placed on 
the AD0-AD15 outputs early in the first clock period, as 
shown in Figure 12. The 5-bit segment number is output 
on SN0-SN4 one clock period earlier than the 16-bit ad- 
dress offset.) 

A valid address is indicated by the rising edge of Address 
Strobe. Status and mode information become valid early in 
the memory ac cess c ycle and remain stable throughout. 
The state of the WAIT input is sampled in the middl e of th e 
second clock cycle by the falling edge of Clock. If WAIT is 



Low, a n additional clock period is added between T 2 and T 3 . 
WAIT is sampled again in the middle of this wait cycle, and 
additional wait states can be inserted: this allows interfacing 
slow memories. No control outputs change during wait 
states. 

Although memory is word organized, memory is 
addressed as bytes. All instructions are word-aligned, using 
even addresses. Within a 16-bit word, the most significant 
byte (D8-D15) is addressed by the low-order address (A = 
Low), and the least significant byte (D -D 7 ) is addressed by 
the high-order address (A = High). 



STATUS 

16/w. Nl5. 
STo-STj) , 



X 



X 



SEGMENT NUMBER 



SAMPLED ^WAITCYC 



XX 



X 



""WAIT CYCLES ADDED 



X 



DATA SAMPLED 
FOB READ 



x: 



AO 

BEAD 



MEMOBY ADDRESS 



V — 



^ DATA 'i*""^ 



DS 

READ 



\ 



X 



R/W 

READ 



7 



AD 

WRITE 



MEMORY ADDRESS 



X 



x: 



\ 



x 



R/W 

WHITE 



X 



Figure 12. Memory Read and Write Timing 



31 



INPUT/OUTPUT 



I/O timing is similar to memory read/write timing, except T2 and Ta (Figure 13). The segmented Z160 uses 16-bit 
that one wait state is automatically Owa) inserted between I/O addresses. 



_ST»TUS 

(B/W. STq-STjI 



IDC 



DOC 



WAIT 
SAMPLED 



WAIT CYCLES ADDED 



DATA SAMPLED 
FOR READ 



X 



ZJC 



PORT ADDRESS 



DS 

INPUT 



\ 



CDC 



PORT ADDRESS 



X 



DS 

OUTPUT 



R/W 

OUTPUT 



\ 



^ DATA IN ^ 



c 



DC 



JZ. 



Figure 13. Input/Output Timing 



32 



INTERRUPT AND SEGMENT TRAP 
REQUEST AND ACKNOWLEDGE 



The Z160 CPU recognizes three intererupt inputs (non- 
maskable, vectore d, an d nonvectored). Any High-to-Low 
transition on the NMI input is a synchronously e dge 
detected and sets the internal NMI latch. The VI and NVI 
inputs, as well as the state of the internal NMI latch, are 
sampled at the end of T2 in the last machine cycle of any 
instruction. 

In response to an interrupt or trap, the subsequent IF-| cycle 
is exercised, but ignored. The internal state of the CPU is not 
altered and the instruction will be refetched and executed 
after the return from the interrupt routine. The program 
counter is not updated, but the system stack pointer is 
decremented in preparation for pushing starting information 
onto the system stack. 

The next machine cycle is the interrupt acknowledge cycle. 



This cycle has five automatic wait states, with additional wait 
states possible, as shown in Figure 14. 

After the last wait state, the CPU reads the information on 
AD -AD 15 and temporarily stores it, to be saved on the stack 
later in the acknowledge sequence. This word identifies the 
source of the interrupt or trap. For the nonvectored and 
nonmaskable interrupts, all 1 6 bits can represent peripheral 
device status information. For the vectored interrupt, the low 
byte is the jump vector, and the high byte can be extra user 
status. 

After the acknowledge cycle, the N/S output indicates the 
automatic change to system mode. 



LAST MACHINE 
- CYCLE OF ANT - 
INSTRUCTION 



_n_r 



AUTOMATIC WAIT STATES 



J \ / V 



■Ay 



m V 

INTKRMAL "^S 



z 



y 



IT 

:a 



:zx 



a 



y 



Figure 14. Interrupt and Segment Trap Request/Acknowledge Timing 



STATUS SAVING SEQUENCE 



The machine cycles, following the interrupt acknowledge 
or segmentation trap acknowledge cycle, push the old 
status information on the system stack in the following 
order: the 1 6-bit program counter; the 5-bit segment num- 



ber; the flag control word; and finally, the interrupt/trap 
identifier. Subsequent machine cycles fetch the new 
program status from the program status area, and then 
branch to the interrupt/trap service routine. 



33 



BUS REQUEST ACKNOWLEDGE TIMING 



A Low on the BUSREQ input indicates to the CPU that 
another device is requestin g the Add ress/Data and control 
buses. The asynchronous BUSREQ input is syn chronized 
at the beginning of any machi ne cycle ( Figure 1 5). BUSREQ 
takes priority over WAI T. If BUSREQ is Low, an internal 
synchronous BUSREQ signal is generated, which— after 
completion of the current machine cycle— causes the 
BUSACK output to go Low and all bus outputs to go into the 



high-impedance state. The requesting device— typically a 
DMA— can then control the bus. 

When BUSREQ is released, it is synchronized with the rising 
clock edge; the BUSACK output goes High one clock 
period later, indicating that the CPU will again take control of 
the bus. 



MREO, DS, ' 

_ ST0-ST3, 

b;w, r/w, his . 





-« ANY M CYCLE »■ 

T, T, T, 


Tx 


BUS 

T» 


AVAILABLE — 

Tx 


Tx 


T* 


Tx 




y — 


//( 






















/ 














— 




\ 


/ 














w 


V 


J 
















— \ 

) — 


< 


























) — 


-< 
























-/same as previous cycleY 

\ — — 


_/ 









Figure 15. Bus Request/ Acknowledge Timing 



34 



STOP 



The STOP input is sampled by the last tailing clock edge 
immediately preceding any IFi cycle (Figure 16) an d befo re 
the second word of an EPA instruction is fetched. If STOP is 
found Low during the IF! cycle, a stream of m emor y refresh 
cycles is inserted after T3, again sampling the STOP input on 
each falling clock edge in the middle of theT3 states. During 
the EPA instruction, both EPA instruction words are fetched 
but any data transfer or subsequent instruction fetch is 



postponed until STOP is sampled High. This refresh 
operation does not use the refresh prescaler or its 
divide-by-four clock prescaler; rather, it double-inc remen ts 
the refresh counter every three clock cycles. When STOP is 
found High again, the next refresh cycle is completed, any 
remaining T states of the cycle are then executed, and 
the CPU continues its operation. 




xz 



xx: itx 




\ r 



X 



z 



MEMORY REFRESH 



3d 



XZ 



Figure 16. Stop Timing 



35 



INTERNAL OPERATION 



Certain extended instructions, such as Multiply and Divide, 
and some special instructions need additional time for the 
execution of internal operations. In these cases, the CPU 
goes through a sequence of internal operation machine 



cycles, each of which is three to eight clock cycles long 
(Figure 17). This allows fast response to Bus Request and 
Refresh Request, because bus request or refresh cycles 
can be inserted at the end of any internal machine cycle. 



WAIT 



STo-ST, 



INTERNAL OPERATION 



X 



UNDEFINED )- ■ 

—f 



SAME AS PREVIOUS CYCLE 



Figure 17. Internal Operation Timing 



HALT 



A HALT instruction executes an unlimited number of 3-cycle 
internal operations, interspersed with memory refresh 
cycles whenever requested. An interrupt, segmentation 
trap, or reset are the only exits from a HALT instruction. 



The CPU samples the VI, NVI and NMI inputs at the begin- 
ning of every T3 cycle. If an input is found active during two 
consecutive samples, the subsequent IF1 cycle is exer- 
cised, but ignored, and the normal interrupt acknowledge 
cycle is started. 



36 



MEMORY REFRESH 



When the 6-bit prescaler in the refresh counter has been 
decremented to zero, a refresh cycle consisting of three 
T-states is started as soon as possible (that is, after the next 
IF-| cycle or Internal Operation cycle). 

The 9-bit refresh counter value is put on the low-order side of 
the address bus (AD -AD 8 ); AD 9 -AD 15 are undefined 
(Figure 18). Since the memory is word-organized, A is 
always Low during refresh and the refresh counter is always 



incremented by two, thus stepping through 256 consecutive 
refresh addresses on AD1-AD8. Unless disabled, the 
presettable prescaler runs continuously and the delay in 
starting a refresh cycle is therefore not cumulative. 

While the STOP input is Low, a continuous stream of memory 
refresh cycles, each three T-states long, is executed without 
using the refresh prescaler. 



CLOCK 



ST0-ST3 



R/W, B/W, HIS 



X 



X 



\ 



REFRESH ADDRESS 



/ 



SAME AS PREVIOUS CYCLE 



-C 



Figure 18. Memory Refresh Timing 



RESET 



A Low on the RESET input causes the following results within 
five clock cycles (Figure 19): 

■ AD -AD 15 are3-stated 



AS, DS, MREQ, ST -ST 3 , BUSACK, and MO are forced 
High 

SN0-SN4 are forced Low 

Refresh is disabled 

R/W, B/W and N/S are not affected 



When RESET has been High for three clock periods, three 
consecutive memory read cycles are executed in the sys- 
tem mode. The first cycle reads the flag and control word 
from location 0002, the next reads the 7-bit program 
counter segment number from location 0004, the next 
reads the 1 6-bit PC offset from location 0006, and the fol- 
lowing IF1 cycle starts the program. 



37 



COMPOSITE AC TIMING DIAGRAM 



This composite timing dia- 
gram does not show actual 
liming sequences. Reter to 
this diagram only lor the 
detailed timing relationships 
of individual edges Use the 
preceding illustrations as an 
explanation of the various 
timing sequences 



Timing measurements are 


maae al [he following 


voltages 








High 


Low 


Clock 


A OV 


8V 


Output 


20V 


08V 


Input 


2.0V 


8V 


Float 


V 


i0 5V 




AD -»D15 



STj-STj, 
REA D/WBlTE , 
NORMAL/SYSTEM, 
BYTE/WORD 



AC CHARACTERISTICS! 



Z160 Z160 
6 MHz 10 MHz 



Number 


Symbol 


Parameter 


Mln 


Max 


Min 


Max 


1 


TcC 


Clock Cycle Time 


165 


2000 


100 


2000 


2 


TwCh 


Clock Width (High) 


70 


1930 


40 


1960 


3 


TwCI 


Clock Width (Low) 


70 


1930 


40 


1960 


4 


TfC 


Clock Fall Time 




10 




10 


5 


TrC 


Clock Rise Time 




15 




10 


6 


TdC(SNv) 


Clock t to Segment Number Valid (50 pf load) 




110 




90 


7 


TdC(SNn) 


Clock t to Segment Number Not Valid 


10 









8 


TdC(Bz) 


Clock t to Bus Float 




55 




50 


9 


TdC(A) 


Clock t to Address Valid 




75 




55 


10 


TdC(Az) 


Clock t to Address Float 




55 




50 


11 


TdA(DR) 


Address Valid to Read Data Required Valid 




305* 




180" 


12 


TsDR(C) 


Read Data to Clock 1 Setup time 


20 




10 




13 


TdDS(A) 


DS t to Address Active 


45" 




20" 




14 


TdC(DW) 


Clock t to Write Data Valid 




75 




60 


15 


ThDR(DS) 


Read Data to DS t Hold Time 












16 


TdDW(DS) 


Write Data Valid to DS t Delay 


195* 




110" 




17 


TdA(MR) 


Address Valid to MREQ i Delay 


35* 




20" 




18 


TdC(MR) 


Clock J to MREQ J Delay 




70 




50 


19 


TwMRh 


MREQ Width (High) 


135* 




80* 




20 


TdMR(A) 


MREQ i to Address Not Active 


35* 




20* 




21 


TdDW(DSW) 


Write Data Valid to DS 1 (Write) Delay 


35* 




15" 




22 


TdMR(DR) 


MREQ J to Read Data Required Valid 




230* 




140* 


23 


TdC(MR) 


Clock* MREQ t Delay 




60 




50 


24 


TdC(ASf) 


Clock t to AS t Delay 




60 




45 


25 


TdA(AS) 


Address Valid to AS t Delay 


35* 




20" 




26 


TdC(ASr) 


Clock 1 to AS t Delay 




80 




45 


27 


TdAS(DR) 


AS t to Read Data Required Valid 




220" 




140* 


28 


TdDS(AS) 


DS t to AS I Delay 


35* 




15" 




29 


TwAS 


AS Width (Low) 


55" 




30" 




30 


TdAS(A) 


AS t to Address Not Active Delay 


45" 




20" 




31 


TdAz(DSR) 


Address Float to DS (Read) * Delay 












32 


TdAS(DSR) 


AS T to DS (Read) * Delay 


55" 




30" 




33 


TdDSR(DR) 


DS (Read) I to Read Data Required Valid 




130" 




70* 


34 


TdC(DSr) 


Clock i to DS t Delay 




65 




50 


35 


TdDS(DW) 


DS t to Write Data Not Valid 


45* 




25" 




36 


TdA(DSR) 


Address Valid to DS (Read) i Delay 


110* 




65" 




37 


TdC(DSR) 


Clock t to DS (Read) * Delay 




85 




65 


38 


TwDSR 


DS (Read) Width (Low) 


185" 




1 io- 




39 


. TdC(DSW) 


Clock i to DS (Write) i Delay 




80 




65 


40 


TwDSW 


DS (Write) Width (Low) 


110" 




75" 





"Clock-cycle time-dependent characteristics. See Footnotes to AC Characteristics. 
tUnits m nanoseconds (ns). 



40 



AC CHARACTERISTICSf (Continued) 



Number 


Symbol 


Parameter 


Z160 
6 MHz 
Mln Max 


Z160 
10 MHz 
Mfn Max 


41 
42 
43 
44 
45 


TdDSI(DR) 

TdC(DSf) 

TwDS 

TdAS(DSA) 
TdC(DSA) 


DS (I/O) i to Read Data Required Valid 

Clock t to DS (I/O) i Delay 

DS (I/O) Width (Low) 

AS t to DS (Acknowledge) i Delay 

Clock t to DS (Acknowledge) J Delay 


210* 
90 

255* 
690" 

85 


120* 
65 

160* 
410* 

70 


46 

47 
48 
49 
50 


TdDSA(DR) 

TdC(S) 
TdS(AS) 
TsR(C) 
ThR(C) 


DS (Acknowledge) 1 to Read Data Required 

Delay 

Clock t to Status Valid Delay 
Status Valid to AS t Delay 
RESET to Clock t Setup Time 
RESET to Clock t Hold Time 


295* 
85 

30* 
70 



165* 
65 

20* 
50 



51 
52 
53 
54 
55 


TwNMI 
TsNMI(C) 
TsVI(C) 
ThVI(C) 


NMI Width (Low) 
NmI to Clock t Setup Time 
VI. NVI to Clock t Setup Time 
VI, NVI to Clock t Hold Time 


70 
70 
50 
20 


50 
50 
40 
10 


56 
57 
58 
59 
60 


TsMI(C) 
ThMI(C) 
TdC(MO) 
TsSTP(C) 


Ml to Clock t Setup Time 
Ml to Clock t Hold Time 
Clock t to MO Delay 
STOP to Clock 1 Setup Time 


140 


85 

100 


80 


80 

50 


61 
62 
63 
64 
65 


ThSTP(C) 

TsW(C) 

ThW(C) 

TsBRQ(C) 

ThBRQ(C) 


STOP to Clock i Hold Time 
WAIT to Clock i Setup Time 
WATT to Clock I Hold Time 
BUSREQ to Clock t Setup Time 
BUSREQ to Clock t Hold Time 



30 
10 
80 
10 



20 

5 
60 

5 


66 

68 
69 


TdC(BAKr) 
TdC(BAKf) 
TwA 

TdDS(S) 


Clock t to BUSACK t Delay 
Clock f to BUSACK I Delay 
Address Valid Width 
DS t to STATUS Not Valid 


75 
75 

95* 
55* 


65 
65 

50* 
30* 


"Clock-cycle time-dependent characteristics. See Footnotes to AC Characteristics 



fUnits in nanoseconds (ns). 



41 



FOOTNOTES TO AC CHARACTERISTICS 







Z160 


Z160 






6 MHz 


10 MHz 


Number 


Symbol 


Equation 


Equation 


11 


TdA(DR) 


2ToC + TwCh - 95 ns 


2TcC + TwCh - 60 ns 


13 


TdDS(A) 


TwCI - 25 ns 


TwCI - 20 ns 


16 


TdDW(DS) 


TcC + TwCh - 40 ns 


TcC + TwCh - 30 ns 


17 


TdA(MR) 


TwCh - 35 ns 


TwCh - 20 ns 


19 


TwMRh 


TcC - 30 ns 


TcC - 20 ns 


20 


TdMR(A) 


TwCI - 35 ns 


TwCI - 20 ns 


21 


TdDW(DSW) 


TwCh - 35 ns 


TwCh - 25 ns 


22 


TdMR(DR) 


2TcC - 100 ns 


2TcC - 60 ns 


25 


TdA(AS) 


TwCh - 35 ns 


TwCh - 20 ns 


27 


TdAS(DR) 


2TcC - 110 ns 


2TcC - 60 ns 


28 


TdDS(AS) 


TwCI - 35 ns 


TwCI - 25 ns 


29 


TwAS 


TwCh - 15 ns 


TwCh - 10 ns 


30 


TdAS(A) 


TwCI - 25 ns 


TwCI - 20 ns 


32 


TdAS(DSR) 


TwCI - 1 5 ns 


TwCI - 1 ns 


33 


TdDSR(DR) 


TcC + TwCh - 105 ns 


TcC + TwCh - 70 ns 


35 


TdDS(DW) 


TwCI - 25 ns 


TwCI - 1 5 ns 


36 


TdA(DSR) 


TcC - 55 ns 


TcC - 35 ns 


38 


TwDSR 


TcC + TwCh - 50 ns 


TcC + TwCh - 30 ns 


40 


TwDSW 


TcC - 55 ns 


TcC - 25 ns 


41 


TdDSI(DR) 


2TcC - 120 ns 


2TcC - 80 ns 


43 


TwDS 


2TcC - 75 ns 


2TcC - 40 ns 


44 


TdAS(DSA) 


4TcC + TwCI - 40 ns 


4TcC + TwCI - 30 ns 


46 


TdDSA(DR) 


2TcC + TwCh - 105 ns 


2TcC + TwCh - 75 ns 


48 


TdS(AS) 


TwCh - 40 ns 


TwCh - 30 ns 


68 


TwA 


TcC - 70 ns 


TcC - 50 ns 


69 


TdDS(s) 


TwCI - 15 ns 


TwCI - 10 ns 



AC Timing Test Conditions 



V OL = 0.8V 
V 0H = 2.0V 
V| L = 0.8V 
V| H = 2.4V 
V, LC = 0.45V 
V|HC = V CC -0.4V 



42 



ABSOLUTE MAXIMUM RATINGS 



Voltages on all pins with respect 

toGND .-0.3V to +7.0V 

Operating Ambient 

Temperature See Ordering Information 

Storage Temperature - 65 °C to + 1 50°C 



Stresses greater than those listed under Absolute Maximum Ratings may 
cause permanent damage to the device. This is a stress rating only; 
operation of the device at any condition above those indicated in the 
operational sections ot these specifications is not implied. Exposure to 
absolute maximum rating conditions for extended periods may affect 
device reliability. 



STANDARD TEST CONDITIONS 

The DC characteristics below apply for the following test 
conditions, unless otherwise noted. All voltages are 
referenced to GND (0V). Positive current flows into the 
referenced pin. 

Available operating temperature ranges are: 

■ S = 0°Cto +70°C, + 4.75V« V cc < +5.25V 

■ E = -40 - C to +1 00"C, +4.75V5 Vcc < +5.25V 

All ac parameters assume a total load capacitance 
(including parasitic capacitances) or 100 pf max, except for 
parameter 6 (50 pf max). Timing references between two 
output signals assume a load difference of 50 pf max. 



DC CHARACTERISTICS 



+ 5V 




The Ordering Information section lists package temperature 
ranges and product numbers. 



Symbol 


Parameter 


Min 


Max 


Unit 


Condition 


VCH 


Clock Input High Voltage 


Vcc-0.4 


V C C + 0.3 


V 


Driven by External Clock Generator 


VCL 


Clock Input Low Voltage 


-0.3 


0.45 


V 


Driven by External Clock Generator 


VlH 


Input High Voltage 


2.0 


V CC + 03 


V 




V|H RESET 


Input High Voltage on RESET pin 


2.4 


V CC + 03 


V 




V IH NMI 


Input High Voltage on NMI pin 


2.4 


V CC + 0.3 


V 




V|L 


Input Low Voltage 


-0.3 


0.8 


V 




VOH 


Output High Voltage 


2.4 




V 


l H = -250 M A 


Vol 


Output Low Voltage 




0.4 


V 


Iol = +2.0 mA 


Iil 


Input Leakage 




±10 


MA 


0.4<V| N < + 2.4V 


'iLSEGT 


Input Leakage on SEGT pin 


-100 


100 


ma 




lOL 


Output Leakage 




±10 


HA 


0.4<V| N < + 2.4V 


! cc 


Vcc Power Supply Current 




300 


mA 


4 MHz and 6 MHz commercial 








400 


mA 


Extended temperature range 








400 


mA 


10 MHz speed range 



43 



Zilog 



PRELIMINARY 
Product Specification 



October 1988 



FEATURES 

■ Full 32-bit architecture and implementation 

■ 4G (billion) bytes of directly addressable memory in each 
ot tour address spaces 

■ Linear or segmented address space 

■ Virtual memory management integrated with CPU 

■ On-chip cache memory 

■ General-purpose register file with sixteen 32-bit registers 

■ Nine general addressing modes 

■ Numerous datatypes include bit, bitfield, logical value, 
signed integer, and string 



GENERAL DESCRIPTION 

The Z320 CPU is an advanced, high-end 32-bit 
microprocessor that integrates the architecture of a 
mainframe computer into a single chip. While maintaining 
full compatibility with Z8000 family software and 
hardware, the Z320 CPU offers greater power and 
flexibility in both its architecture and interface capability. 
Operating systems and compilers are easily developed in 
the Z320 CPU's high-quality environment, and the 
hardware interface provides for connection to a wide 
variety of system configurations. 

Adddresses in the Z320 CPU are 32 bits. This allows 
direct addressing of 4G bytes in each of four address 
spaces: system-mode data, system-mode instruction, 
normal-mode data, and normal-mode instruction. The 
CPU supports three modes of address representation. 
The 16-bit compact addresses are compatible with 
Z80O0 nonsegmented mode. The 32-bit segmented 
addresses include both 16-bit offset, which is compatible 
with Z8000 segmented mode, and 24-bit offset. In 
addition, a full 32-bit linear address space is provided. 

The CPU features a general-purpose register file with 
sixteen 32-bit registers and nine operand addressing 
choices for compact representation or for full 32-bit 



Z320™ CPU 



■ Regular use of operations, addressing modes, and data 
types in instruction set 

■ System and normal modes of operation with separate 
stacks 

■ Sophisticated interrupt and trap handling 

■ Software is a binary-compatible extension of Z8000® 
software, totally compatible with the Z80.000® 

■ Small, low cost 68-pin plastic leaded chip carrier 
package for surface mount applications 

■ Hardware is compatible with other Z-BUS® bus 
components with multiplexed address and data 

■ Mainframe performance at a micro price 



addressing. The instruction set can operate on bit, bit 
field, logical value, signed integer, unsigned interger, 
address, string, stack, and packed decimal byte data 
types. Logical and arithmetic instructions operated on 
bytes (8 bits), words (16 bits) and longwords (32 bits). 
The Extended Processing Architecture (EPA) supports 
highly regular in combining operations, data types, and 
addressing modes. High-level language compilation is 
supported with instructions for procedure linkage, array 
index calculation, and bounds checking. Other 
instructions provide operating system functions such as 
system call and control of memory management. 

There are two main operating modes, system and 
normal, supported by separate stacks. User programs 
operate in normal mode, while sensitive operating 
system functions are performed in system mode. This 
protects critical parts of the operating system from user 
access. In addition, some instructions are priveleged, 
and execute only in system mode. Memory management 
functions protect both system memory from user 
programs, and user memory from other users. Vectored, 
nonvectored, and nonmaskable interrupts support 
realtime operating systems. 



44 



Memory managmement is fully integrated with the CPU; 
no external support circuitry is necessary. A paging 
address translation mechanism is implemented. 
Registers in the CPU point to address translation tables 
located in memory; the most recently used table entries 
are kept in a Translation Lookaside Buffer (TLB) in the 
CPU. The CPU performs logical to physical address 
translation and access protection for each memory 
reference. When a logical memory reference causes a 
translation or protection violation, the state of the CPU is 
automatically restored to restart the instruction. I/O ports 
can be referenced either by dedicated instructions or by 
the memory management mechanism mapping logical 
memory addresses to I/O port addresses. 

Extensive trapping facilities, such as integer overflow, 
subrange out of bounds, and subscript out of bounds, 
catch common run-time errors. Software debuggers can 
use trace and breakpoint traps. Privileged instruction 
traps and memory protection violation traps secure the 
operating system from user programming errors or 
mischief. The overflow stack allows recovery from 
otherwise fatal errors. 



The CPU has full 32-bit internal address and data paths. 
Externally, 32 pins time-multiplex the address and data. 
The interface is compatible with the complete line of 
Z-BUS peripherals. The hardware interface features 
16-bit or 32-bit memory data path and programmable 
wait states. Burst transfers and an on-chip cache for 
instructions and data help develop high-performance 
systems. The interface supports multiprocessing 
configurations with interlocked memory references and 
two types of bus request protocols. The system designer 
can tailor the Z320 based system to cost and 
performance needs. 

In summary, the Z320 CPU meets and surpasses the 
requirements of medium and high-end microprocessor 
systems for the 1 980s. Software program development is 
easily accomplished with the CPU's sophisticated 
architecture. The highly pipelined design, on-chip cache, 
and external interface support systems ranging from 
dedicated controllers to mainframe computers. While 
Zilog continues to develop support for the Z320 CPU, 
Z8000 peripherals and development software are fully 
compatible with this latest in Zilog's line of 
high-performance microprocessors. 



REGISTERS 



The Z320 CPU is a register-oriented processor offering 
sixteen 32-bit general-purpose registers, a 32-bit Program 
Counter (PC), a 16-bit Flag and Control Word (FCW), and 
nine other special-purpose registers. 

The general-purpose register file (Figure 1) contains 64 

bytes of storage. The first 16 bytes (RL0.RH0 RL7.RH7) 

can be used as accumulators for byte data. The first 1 6 
words (R0,R1,...,R15) can be used as accumulators for 
word data, as index registers (except R0), or for memory ad- 
dresses in compact mode (except R0). Any longword regis- 
ter (RR0.RR2 RR30) can be used as an accumulator for 

longword data, an index register in linear or segmented 
mode (except RRO), or for memory addresses in linear or 
segmented mode (except RRO). Quadword registers 
(RQ0.RQ4 RQ28) can be used as accumulators for Multi- 
ply, Divide, and Extend Sign instructions. This unique regis- 
ter organization allows bytes and words of data to be 
manipulated conveniently while leaving most of the register 
file free to hold addresses, counters, and any other data. 

Two registers are dedicated to the Stack Pointer (SP) and 
Frame Pointer (FP) used by Call, Enter, Exit, and Return 



and R14 the Frame Pointer. In linear or segmented 
mode, RR14 is the Stack Pointer and RR12 is the Frame 
Pointer. 



RO0 


RRO 


7 RHO 





7 


RLO 





7 


RH1 





7 


RL1 





R0. R1 


RR2 


7 RM2 





7 


RL2 





7 


RH3 





7 


RL3 





R2, R3 


RQ4 


RR4 


7 RM4 





7 


RL4 





7 


RH5 





7 


RLS 





R4, R5 


RR6 


7 RH6 





7 


RLf. 





7 


RH7 





7 


RL7 





R6, R7 


R08 


RRfi 


15 


R8 









IS 




R9 









RR10 


15 


R10 







15 




R11 









R012 


RR12 


15 


R12 







15 




R13 









RR14 


15 


R14 




o 


15 




R15 









RQ16 


RR16 


31 

























RR1« 


31 

























RQ20 


RR20 


31 



























RR22 


31 

























R024 


RR24 


31 

























RR26 


31 

























RQ28 


RR28 


31 

























RR30 


31 


























Figure 1. General-Purpose Register File 



45 



CACHE 



The CPU implements a cache mechanism to keep on-chip 
copies of the most recently referenced memory locations 
(Figure 12). The CPU examines the cache on memory 
fetches to determine if the addressed data are located in the 
cache. If the information is in the cache (a hit), then the CPU 
fetches from the cache, and no transaction is necessary on 
the external interface. If the information is not in the cache (a 
miss), then the CPU performs a memory read transaction to 
fetch the missing information. 

The cache stores data in blocks of 1 6 bytes. Each data word 
in the cache has an associated validity bit to indicate 
whether or not the word is a valid copy of the corresponding 
main memory location. The cache contains 16 blocks, pro- 
viding 256 bytes of storage. 

The cache is fully associative, so that a block currently 
needed and missing in the cache can replace any block in 
the cache. Moreover, when a block miss occurs, the least 



ADDRESS TAG 
ASSOCIATIVE 
MEMORY 
(16 x 28) 


MATCH 
LINES 


CACHE DATA 
MEMORY 
(16x128) 


VALIDITY 
BITS 
(16x8) 




LRU 
STACK 
(16x«| 


J-16 





TAG 
HIT 



J, 



PHYSICAL 
ADDRESS 



WORD 
HIT 



recently used (LRU) block in the cache is replaced. When a 
cache miss occurs on an instruction fetch, the CPU fetches 
the missing instruction from memory and prefetches the fol- 
lowing words in the block using a burst transaction. When a 
cache miss occurs on an operand fetch, the CPU fetches 
the missing data from memory. (The CPU uses burst trans- 
actions only for fetching operands when more than one data 
transfer is necessary: longword operands on a 16-bit bus, 
unaligned operands, string instructions, Load Multiple in- 
structions, and loading Program Status.) 

On store references, the data is written to memory (store 
through), and if the reference hits in the cache, the data is 
also written to the cache. If the store reference misses in the 
cache, the cache is unaffected. 

Software has some control over the cache. The cache can 
be selectively enabled for instruction and data references by 
bits CI and CD in the SCCL control register. The memory 
management mechanism allows cacheing to be inhibited 
for individual pages. The Pcache instruction can be used to 
invalidate all information in the cache. 

The cache has an option, controlled by bit CR in SCCL, to 
inhibit block replacement on a miss. This option can be 
used to lock fixed locations into the cache for fast, onchip 
access. To do this, the cache is first enabled for block re- 
placement of data references only. Selected blocks are read 
into the cache. The block replacement algorithm is then dis- 
abled, while the cache is enabled for instruction and data 
references. 



Figure 2. Cache Organization 



PIN DESCRIPTIONS 

The CPU has 58 signal lines and additional power supply- 
connections. Pin functions are shown in Figure 3a, b, c. 

AD -AD 31 . Address/Data (Bidirectional, active High, 
3-state). These 32 lines are time-multiplexed to transfer ad- 
dress and data. At the beginning of each transaction the 
lines are driven with the 32-bit address. After the address 
has been driven, the lines are used to transfer one or more 
bytes, words, or longwords of data. 

AS. Address Strobe (Output, active Low, 3-state). The falling 
edge of AS indicates the beginning of a transaction 
and_shows_that the a ddress and ST0-ST3, are valklR/W, 
BL/W, BW/L, and BRST are valid on the rising edge of AS. 

BL/W; BW/L. Byte, LongwordArVord; Byte, Word/Long- 
word (Output, 3-state). These two lines specify the data 
transfer size. 



BL/W 


BW/L 


Size 


High 


High 


Byte 


Low 


High 


Word 


High 


Low 


Longword 


Low 


Low 


Reserved 



BRST. Burst (Output, active Low, 3-state). A Low on this line 
indicates that the CPU is performing a burst transfer; i.e, 
multiple Data Strobes following a single Address Strobe. 

BRSTA. Burst Acknowledge (Input, active Low). A Low on 
this line indicates that the responding device can support 
burst transfers. 

BUSACK. Bus Acknowledge (Output, active Low). A Low on 
this line indicates that the CPU has relinquished control of 
the local bus in response to a bus request. 

BUSREQ. Bus Request (Input, active Low). A Low on this 
line indicates that a bus requestor has obtained or is trying to 
obtain control of the local bus. 



46 



CLK. Clock (Input). This is the clock used to generate all 
CPU timing. 

DS. Dafa Strobe (Output, active Low, 3-state). DS is used for 
timing data transfers. 

EPUABORT. EPU Abort (Output, active High). A 
High on this line indicates that the CPU is aborting 
execution of an EPA instruction, typically because an 
Address Translation trap has occurred. 

EPUBSY. EPU Busy (Input, active Low). A Low on this line 
indicates that an EPU is busy. This line is used to synchro- 
nize the operation of the CPU with an EPU during execution 
of an EPA instruction. 

GACK. Global Acknowledge (Input, active Low). A Low on 
this line indicates the CPU has been granted control of a 
global bus. 

GREQ. Global Request (Output, active Low, 3-state). A Low 
on this line indicates the CPU has obtained or is trying to ob- 
tain control of a global bus. 

IE. Input Enable (Output, active Low, 3-state). A Low on this 
line can be used to enable buffers on the AD lines to drive 
toward the CPU. 

NMI. Non-Maskable Interrupt (Input, Edge activated). A 
High-to-Low transition on this line requests a nonmaskable 
interrupt. 

NVI. Non-Vectored Interrupt (Input, active Low). A Low on 
this line requests a non-vectored interrupt. 



OE. Output Enable (Output, active Low, 3-state). A Low on 
this line can be used to enable buffers on the AD lines to 
drive away from the CPU. 

RESET. Reset (Input, active Low). A Low on this line resets 
the CPU. 



RSPn-RSP-|. Response (Input). These lines encode the re- 
sponse to transactions initiated by the CPU. N ote tha t RSPo 
and RSPi can be connected together for Z-BUS WAIT timing. 



RSP 


RSP, 


Response 


High 


High 


Ready 


Low 


High 


Bus Error 


High 


Low 


Bus Retry 


Low 


Low 


Wait 



R/W. Read/Write (Output, Low = Write, 3-state). This signal 
indicates the direction of data transfer. 



ST0-ST3. Status (Output, active High, 3-state). These lines 
specify the kind of transaction occurring on the bus. (See 
Table 5.) 

VBB. Substrate Bias Generator (Output, for internal biasing 
only). 

VI. Vectored Interrupt (Input, active Low). A Low on this line 
requests a vectored interrupt. 



INTERRUPT 
REQUESTS 



EXTENDED 
PROCESSOR 
CONTROL 

LOCAL BUS 
CONTROL 



GLOBAL BUS 
CONTROL 



SUBSTRATE BIAS 
GENERATOR 



RESET 

NMI 

VI 
NVi 



EPUBSY 
EPUABORT 



BUSREO 
BUSACK 



GREQ 

Sack 



Z320 CPU 



AD 

AS 
DS 
R/W 
BUW 
BW/L 
STATUS 
RESPONSE 



OE 

II 

BEST 
BRSTA 
CLK 



jl \z \s ^3 

+ 5 *5 GNO GND CLOC 

CIRCUIT OUTPUT CIRCUIT OUTPUT 

DRIVERS DRIVERS 



ADDRESS/DATA 



BUS STATUS 
AND TIMING 



BUFFER 
CONTROL 



BURST TRANSFER 
CONTROL 



Figure 3a. Pin Functions 



47 



///////////////// 









4D2V 


10 


M 


ADJO 


f 1 




St 


•031 


12 




gf 


SfO 


13 




57 


icscf 


14 




§t 


CND (I/O) 


15 




55 


CND (CCD 


1* 




54 


cm 


17 




53 


•)V (CCD 


It 


Z320 MPU 


52 


CND 


It 




51 


SI1 


20 




50 


ST2 


21 




41 


SI3 


22 




4t 


BUST * 


23 




47 


tSPt 


24 




46 


KSfO 


25 




45 


DS 


2t 


44 



ton 

•D11 

«nio 

40* 

MM 
un 
•ot 

CND (CCT) 

CNO (I/O) 

405 

404 

Ml 

402 

401 

400 

VI 

»HB4SUBSI««I( 



Figure 3b. 



PIN ASSIGNMENT FOR Z320 IN 68-PIN PLCC PACKAGE 



PIN I 


f UNCI ION 


PIN 4 | 


FUNCTION 


PIN t | rUNCIIOM 


PIN 1 


roNCMON 




402* 




IC 


44 IVBB4SUBS1P4TC 


41 


4013 




40)0 




4S 


4) | VI 


12 


1014 




40)1 




r.RCQ 


44 | 4D0 


4) 


4015 




510 




oc 


47 | 401 


44 


4014 




DC SCI 




I4SI 


41 j 402 


13 


4017 




END (I/O) 




BUS ACK 


4) | 40) 


44 


4011 




CNO (CCD 




mi 


SO I 404 


47 


401* 




et« 




C4CK 


SI | 405 


II 


4020 




.»» (CCD 




P.US4CI 


SI 1 CNO (I/O) 


1 | 


•*« 




CND 




*»t 


S3 | CNO (CCD 


2 | 


4021 




SM 




tPUBSV 


54 j 404 


3' : .| 


4012 




512 




mi 


55 j 4D7 


1 | 


4023 




It] 




RNIL 


54 | 401 


S | 


4024 




MS 14 




PL IN 


57 | 40* 


1 | 


4025 




I3P1 




CPII4R041 


SI j 4010 


7 | 


4024 




■ SPO 




■/« 


59 j 401 1 


I | 


4027 




OS 




CND (I/O) 


40 | 4012 


» | 


4021 



1.17 



Figure 3c. 



ABSOLUTE MAXIMUM RATINGS 

Voltages on all inputs and outputs 

with respect to GND -0.3V to + 7.0V 

Operating Ambient 

Temperature See ordering information 

Storage Temperature - 65 °C to + 1 50 °C 



STANDARD TEST CONDITIONS 

The DC characteristics below apply for the following 
standard test conditions, unless otherwise noted. All 
voltages are referenced to GND (0V). Positive current flows 
into the referenced pin. 

Available operating temperature ranges are: 

■ S = 0°Cto +70°C, + 4.75V <V CC < + 5.25V 

All ac parameters assume a total load capacitance (C), 
including parasitic capacitances, of 100 pf max. 



Stresses greater than those listed under Absolute Maximum 
Ratings may cause permanent damage to the device. This 
is a stress rating only: operation of the device at any 
condition above those indicated in the operational sections 
of these specifications is not implied. Exposure to absolute 
maximum rating conditions for extended periods may affect 
device reliability. 



+ 5V 




2.1 K 



DC CHARACTERISTICS 



Symbol Parameter Mln Typ Max Unit Condition 



V C H 


Clock Input High Voltage 


3.0 


V C C + 0.3 


V 


Driven by External Clock Generator 


VCL 


Clock Input Low Voltage 


-0.3 


0.6 


V 


Driven by External Clock Generator 


VlH 


Input High Voltage 


2.0 


V C C + 0.3 


V 




V(L 


Input Low Voltage 


-0.3 


0.8 


V 




V H 


Output High Voltage 


2.4 




V 


I h - -500,iA 


Vol 


Output Low Voltage 




0.4 


V 


'OL = + 4.0 mA 


IlL 


Input Leakage 




±10 


MA 


0.4 < V| N < +2.4V 


ice 


V CC Supply Current 




700 


rhA 


8 MHz Clock Frequency 




VCC Supply Current 




800 


mA 


10 MHz Clock Frequency 



49 



AC CHARACTERISTICS* 

8 MHz 10 MHz 



Number 


Symbol 


Parameter 


Mln 


Max 


Min 


Max 


1 


TcC 


PCIock Cycle Time 


125 


500 


100 


500 


2 


TwCh 


Width (High) 


52 




40 




3 


TwCI 


Width (Low) 


52 




40 




4 


TfC 


PCIock Fall Time 




10 




10 


5 


TrC 


PCIock Rise Time 




10 




10 


6 


\Q\S\OZ) 


rulOCk T to DUS rloat 




47 




47 


7 


TsA(C) 


Address Valid to PCtock t Setup Time 







o 




g 


TdC(Az) 


PCIock t to Address Float 




40 




tin 


g 




AnVirp*;^ Valid tn Rpad ("lata Rpm lirpd Valid /^inrilp mpmnru 

nUUi Coo voiiLi l\J ncou l_/ d Let ncv^Uli V ct 1 1 <-J ^ou iu(C7 1 1 id 1 hji y 














read timing with one wait, without wait is 280) 


605t 




480 1 




10 


TsDR(C) 


Read Data to PCIock t Setup Time 


20 








■ ■ 




t tn Addrpcc Artivp 


yoT 




1 UT 




12 


TdC(DW) 


PCIock t to Write Data Valid 




65 




65 


13 


ThDR(C) 


Read Data Valid to PCIock t Hold Time 


5 




5 




14 


ThDR(DS) 


Read Data Valid to DS t Hold Time 












15 


TdDW(DS) 


Write Data Valid to DS t Delay 


330 T 




255 1 




16 


TdDW(DSW1 


Writp Data Valid to DS i (Writpl Dplav 


oyj I 




OD 1 




17 


TdC(ASf) 


PCIock t to 1 Delay 




50 




50 


18 


TsS<C) 


Status Valid tn PCAnrk t Sptnn Timp 


o 









19 


TdCfASrl 


PCInrk t tn AS t DpIav 




50 






20 




AS f tn Rpad Plata Rpm lirpd Valid ^cinnlo momnrv rpad 














timing with one wait; without wait is 120) 


420 1 




320 1 




21 


TdDS(AS) 


DSttoASiDelay 


335 1 




260t 




22 


TwAS 


AS Width (Low) 


110t 




85 1 




23 


TdAS(A) 


AS t tn AdnVp^^ Nnt Antivp FJplav 






IV 1 




24 


TdAzfDSRl 


Addrp<;^ Flnat tn nS 1 fRpad^ Hplau 


o 









25 


TdBz(BUS> 


Bus Float to BUSACK 1 Dplav 


g 




a 




26 


TdAS(DSR) 


AS" t to DSi (Read) Delay 


95t 




70t 




27 




uo \ncau) ♦ to neau udia nequirecj vana (single memory 














1 cdu III 1 II I ly Willi Ulle wall, WIlMUUl Wdll lb £.\J) 


«iyo t 








28 




PCInrk t to t nplau 




ou 






29 




rjc: t tn Writp Data Mnt ValiH 

UO 1 VJ VVIIlt? Udld INUl VdMU 


yoi 




70 T 




31 




njiuw i lu uo tnedu/ + ucidy 




^n 




50 




IWUon 


Uo (Head) Width (Low) (single memory read timing with one 














wait, without wait is 85) 


360 f 




285t 




33 


TdQDSW) 


PCIock t to D5 (Write) i Delay 




50 




50 


34 


TwDSW 


D5 (Write) Width (bow) 


235t 




185t 




35 


TdDSI(DR) 


DS" (1 10) i to Read Data Required Valid 


95 1 




120t 




36 


TdC(DSI) 


PCIock t to DS(l/0)i Delay 




50 




50 



• Units in nanoseconds. See Footnotes to AC Characteristics. 
tClock-cycle time-dependent characteristics. 



50 



AC CHARACTERISTICS* (Continued) 



8 MHz 



10 MHz 



Number 


Symbol 


Parameter 


Mln 


Max 


Min 


Max 


37 


TwDSI 


DS (I/O) Width (Low) 


235 1 




185t 




38 


TdAS(DSA) 


AS t to DS i (Acknowledge) Delay 


95t 




70t 




39 


TdC(DSA) 


PCIock t to DS (Acknowledge) J Delay 




50 




50 


40 


TdDSA(DR) 


DS (Acknowledge) i to Read Data Required Valid 


170t 




120t 




41 


TdC(S) 


PCIock t to Status Valid Delay 




60 




60 


42 


TdS(AS) 


Status Valid to AS t Delay 


85 1 




60t 




43 


TsR(C) 


RESET to PCIock 1 Setup Time 


20 




20 




44 


ThR(C) 


RESET to PCIock* Hold Time 


25 




25 




45 


TwNMII 


NMT Width (Low) 


365T 




2901 




46 


TwNMIh 


NMT Width (High) 


240t 




190t 




47 


TsNMI(C) 


NMl i to PCIock t Setup Time 


40 




40 




48 


TsVI(C) 


VT, NVT to PCIock t Setup Time 


40 




40 




49 


ThVI(C) 


VI, NVI to PCIock t Hold Time 


20 




20 




50 


TwVI 


VT.NVT Width (Low) 


365t 




290t 




51 


TsBREQ(C) 


BUSREQ Change to PCIock t Setup Time 


40 




40 




52 


TwBREO 


BUSREQ Width (Low) 


365 1 




290t 




53 


ThBREQ(C) 


BUSREQ to PCIock t Hold Time 


20 




20 




54 


TdC(BACKr) 


PCIock t to BUSACKt Delay 




65 




65 


55 


TdC(BACKf) 


PCIock t to BUSACK i Delay 




65 




65 


57 


TdC(IEr) 


PCIock t to TP t Dplav 




65 




DO 


58 


TdC(IEf) 


PCIock t to IE i Delay 




65 




65 


59 


TsBRSTA(C) 


BRSTA to PCIock t Setup Time 


25 




25 




60 


TsEPUBSY(C) 


EPUBSY to PCIock t Setup Time 


20 




20 




61 


ThBRSTA(C) 


BRSTA to PCIock t Hold Time 


5 




5 




62 


ThEPUBSY(C) 


EPUBSY to PCIock t Hold Time 


5 




5 




63 


TsRSP(C) 


RSP Chanap to POInrk t Sptun Timp 


20 




on 




64 


ThRSP(C) 


RSP to PCIock t Hold Time 


5 




5 




65 


TdlE(OE) 


OE Change to IE Change Delay 


295 1 




270t 




66 


TwGACK 


GACK Width (Low) 


365t 




290t 




67 


TsGACK(C) 


GACK Change to PCIock t Setup time 


40 




40 




68 


ThGACK(C) 


GACK to PCIock t Hold Time 


20 




20 




69 


TdC(OEf) 


PCIock t to OE i Delay 




50 




50 


70 


TdC(OEr) 


PCIock t to OE t Delay 




50 




50 


71 


TdC(BRSTf) 


PCIock t to BRST J Delay 




65 




65 


72 


TdC(BRSTr) 


PCIock t to BRST t Delay 




65 




65 


73 


TdC(GREQt) 


PCIock t to GREQi Delay 




50 




50 


74 


TdQGREQr) 


PCIock t to GREQ t Delay 




50 




50 



•Units in nanoseconds. See Footnotes to AC Characteristics. 
tClock-cycle time-dependent characteristics. 



51 



FOOTNOTES TO AC CHARACTERISTICS 



No. 


Symbol 


Equation 




9 


TdA(DR) 


5TcC 






11 


TdDS(A) 


TcC - 


- TdC(DS) + TdC(Az) - 


20ns 


15 


TdDW(DS) 


3TcC 


- TdC(DW) + TdQDS) 


- 30ns 


16 


TdDW(DSW) 


TcC - 


- TdQDW) + TdQDSW) 


- 30ns 


20 


TdAS<DR) 


** 1 CO 


iuo\rto)j ~~ i bunyo^ 


- TrC 


21 


TdDS(AS) 


3TcC 


- TdQDS) + TdQASf) • 


- 40ns 


22 


TwAS 


TcC - 


- 15ns 




23 


TdAS(A) 


TcC - 


- TdQASr) + TdQAz) - 


20ns 


26 


TdAS(DSR) 


TcC - 


- TdC(ASr) + TdQDSR) 


- 30ns 


27 


TdDSR(DR) 


1 CO 




- TrC 


29 


TdDS(DW) 


1 CO - 


- TdC(DS) + TdQAz) - 


20ns 


32 


TwDSR 


3TcC 


- 15ns 




34 


TwDSW 


2TcC 


- 15ns 




35 


TdDSI(DR) 


<; 1 CO 


- TdC(DSI) - TsDR(C) 


- TrC 


37 


TwDSI 


I CO 


- 15ns 




38 


TdAS(DSA) 


1 CO 


■ TdQASr) + TdC(DSA) 


- 30ns 


40 


TdDSA(DR) 


2TcC 


- TdC(DSA) - TsDR(C) 


- TrC 


42 


TdS(AS) 


TcC - 


• TdC(S) + TdQASr) - 30ns 


45 


TwNMII 


3TcC 


- 10ns 




46 


TwNMIh 


2TcC 


- 10ns 




50 


TwVI 


3TcC 


- 10ns 




52 


TwBREQ 


3TcC 


- 10ns 




65 


TdlE(OE) 


TcC - 


■ TdQOEr) + TdQIEf) - 


45ns 


66 


TwGACK 


3TcC 


- 10ns 





AC Timing Test Conditions 



V 0L = 0.8V 
V 0H = 2.0V 
V| L = 0.8V 
V IH = 2.4V 
V ILC = 0.6V 
V,hc = 3.0V 



52 



AC TIMING 




53 



Zilog 



Advanced Information 
Product Specification 



October 1988 



Z328 In Circuit Emulator 



FEATURES: 

■ Z320 Support Chip ■ Break Request and Break Acknowledge Signals 

■ Full Z320 instruction Set ■ Easy Solution to System Debugging 

■ Real Time Execution ■ 84 Pin Ceramic Grid Array Package 

■ Single Step Operation 



GENERAL DESCRIPTION: 

Emulator chip is support chip that gives users the hard- 
ware control of the internal instruction execution micro- 
cycles performed by the pipelined structure. 

Access to breakpoint request for breakpoint acknowledge 
signals of the Z80328 chip allows real time execution with 
external control of the breakpoint trap feature. 



Continual exertion of a breakpoint request will result in 
single-step operation where access to read or modify 
CPU registers for memory in the CPU and the target 
offers the ability to trace. 

The Z328 is an easy solution to system debugging. The 
Z328 is available in an 84-pin ceramic grid-array package. 



N M L K 



D C B A 



Abbreviations 
O = Output Driver 
C = Circuit 
S = Substrate 



13C 



nnnnnnnnnnnnn 



113 



GND AD AD AD AO AD AD AD AO AD AD AD 

AD AD +5.0 AD GND.C GND.O GND.O .5.0 AD VI VBB+S RW ^) 1 2 
AD 



AD 
AD 
AD 
AD 
AD 
AD 
AD 
AD 
AD 
AD 
AD 



GND.O 
AD 

+5,C 
.5.0 
♦5.0 



GND.O 
AD 

AD +5,0 GND.O GND.C CLK GND.C GND.O BRSTA ♦50GND.o"iE 
AD AD ST RESET +5.C ST ST ST RSP RSP DS 



EPUABORT BUW Z] 1 1 

GND.O BW/L ^] t J) 

+5,0 iivT ^] 9 

+5.C EPUBSY ^] 8 

□ 7 

□ 6 

□ 5 

□ 4 

□ 3 

□ 2 

□ 1 



+5.0 
BRKACK GACK 
NW BRKREO 



BRST BUSACK 
GREO 0€ 



uuuuuuuuuuuuu 

NMLKJHGFEDCBA 

84-pin Pin Grid Array (PGA), Pin Assignments, 
Preliminary View of Pin Side 



54 



Zilog 



PRELIMINARY 

Product Specification 



October 1988 

Z5380 SCSI 

Small Computer System 



FEATURES: 

• Compatible 5380 Pinout 

• CMOS - Typical Ice 2.5 mA 

• Asynchronous Interface, Supports 1.5 MB/s 

• Direct SCSI Bus Interface with On-Board 48 mA 
Drivers 

• Supports Target and Initiator Roles 



• Arbitration Support 

• DMA or Programmed I/O Data Transfers 

• Supports Normal or Block Mode DMA 

• Memory or I/O Mapped CPU Interface 



GENERAL DESCRIPTION: 



Zilog's Z5380 SCSI (Small Computer System Interface) 
controller, is a 40 pin DIP or 44 pin PLCC CMOS device. 
It was designed to implement the SCSI protocol as defined 
by the ANSI X3T9.2 Committee, and is a plug-in replace- 
ment of the industry standard - the NMOS 5380. The Z5380 
is capable of operating both as a Target and an Initiator. 
This enables the Z5380 to find its use in Bus Host Adap- 
tors, Formatters, and Host Port designs. Special high-cur- 
rent open-drain outputs enable it to directly interface to, 
and drive, the SCSI bus. These drivers are capable of sink- 
ing 48 mA at 0.5V. The Z5380 has the necessary interface 
hook-ups so the system CPU can communicate with it like 



with any other peripheral device. The CPU can read from, 
or write to the SCSI registers which may be addressed as 
standard or memory-mapped l/O's. The Z5380 increases 
the system performance by minimizing the CPU interven- 
tion in DMA operations which the Z5380 controls. The CPU 
will be interrupted by the Z5380 when it detects a bus con- 
dition that requires that attention. It also supports arbitra- 
tion and reselection. The Z5380 has the proper 
hand-shake signals to support normal and block mode 
DMA operations with most of the popular DMA controllers 
available. 



DB0-7.P 



10R 

ibw 

cs 

RESET - 
A0-A2- 

D0-D7 





CPU 




BUS 








INTER- 




FACE 


6 





ACK ATN BSY MSG 176 C7D REQ RST SEL 

ftl 1 1 1 1 11 1 1 

48mA SCSI TRANSCEIVERS 



DMA 

LOGIC 



« a 

Q < 



r 











i 






INTERFACE 
CONTROL 
LOGIC 






DATA 
INPUT 
REGISTER 




DATA 

OUTPUT 
REGISTER 










o 








INTERRUPT 
LOGIC 




CONTROL 
REGISTERS 







BLOCK DIAGRAM 



55 



LOGIC SYMBOL 



■a 



AO- A2 




IOR 




low 




CS 




RESET 




DSCK 




hot 




DRg 




READY 




IRQ 




GND 






CONNECTION DIAGRAMS 



Do C 

db; c 2 

DBl C3 

DBi C5 

DB~2 C 7 
Dffi C8 
DB~ H9 
DIP C 
GNDC 

sTlQ 

BSY □ 

ackC 

ATN C 
RST □ 
I/O C 
C75 C 

msgC 



Z5380 



34 

33 b 
32 □ 
31 

30 b 

29 □ 



REO C 20 



25 
24 
23 
22 
21 



40 □ D, 
39DD 2 
38 □ D 3 
37 3D* 
36 DDs 
3SDD 6 

□ d 7 

A 2 
A, 

□ Voo 
Ao_ 
IOW 



28 □ RESET 

27DEOP 
26 □ 



DACK 

□ READY 

□ IOR 

□ IRQ 

□ DRQ 

□ CS 



Id Id l§ Id o°z o'D"tf o" d" 

nnnnnnnnnnn 

6 5 4 3 2 1 44 43 42 41 40 



DB 3 
DB 2 
fJB, 

Bio 

DBP 
GND 
GND 
STL 
BSY 



ACK Q 16 
ATN □ 17 



7 
8 

9 

10 
11 
12 
13 
14 
15 



Z5380 



39 □ D 6 

38 □ D 7 

37 □ Aj 

36 □ A, 

35 □ V DD 

34 □ NO 

33 □ Ap 

32 □ OW 

31 □ RESET 

30 □ EOP 

29 □ DACK 



18 19 20 21 22 23 24 2526 27 28 



uuuuuuuuuuu 



IO ID IO io o i» o o 
lo |« IS z ° " 



g I IS I 



TOP VIEW 



56 



PIN DESCRIPTION 

Microprocessor Bus 

A0-A2. Address Lines (Input). Address lines are used with 
CS, IOR or IOW to address all internal registers. 

ClT Chip Selec t ( Input, Active LOW). CS in conjunction 
with IOR or IOW, enables the internal register selected by 
A0-A2, to be read from or written to. 

BACK: DMA Acknowledge (Input, Active LOW). DACK 
resets DRQ and s elects the data register for input or out- 
putdata transfers. DACK is used by DMA controller instead 
of CS. 

DRQ. DMA Request (Output Active High). DRQ indicates 
that the data register is ready to be read or written. DRQ 
is asserted only if DMA m ode is set in the Command 
Register. DRQ is cleared by DACK. 

D0-D7. Data Lines (Bidirectional; Three-State, Active 
HIGH). Bidirectional microprocessor data bus lines. 

EOP. End of Process (Input, Active LOW). EOP is used to 
terminate a DMA transfer. If asserted during a DMA cycle, 
the current byte will be transferred, but no additional bytes 
will be requested. 



IOR. //Oflead(lnput, Active LOW). IOR is used in conjunc- 
tion with CS and A0-A2. to write an internal register It also 
selects the input Data Register when used with DACK. 



IOW. I/O Write (Input, Active LOW). IOW is used in con- 
junction with CS and A0-A2, to write an internal register. It 
also selects the Output Data Register when used with 
DACK. 

IRQ. Interrupt Request (Output, Active HIGH). IRQ alerts 
a microprocessor of an error condition or an event comple- 
tion. 

READY. Ready (Output Active HIGH). READY is used to 
control the speed of Block mode DMA transfers. This sig- 
nal goes active to indicate the chip is ready to send/receive 
data and remains FALSE after a transfer until the last byte 
is sent or until the DMA MODE bit is reset. 

RESET. Reset (Input, Active LOW). R ESET clears all 
registers. It has no effect upon the SCSI RST signal. 

Power Signals 

VDD. + 5- Volt Power Supply 

GND. Ground 



SCSI Bus 

The following signals are all bidirectional, active-LOW, 
open-drain, with 48-mA sink capability. All pins interface 
directly with the SCSI Bus. 



ACK. Acknowledge (Bidire ctional ; Open Drain, Active 
LOW). Driven by an Initiator, ACK indicates an acknow- 
ledgement f oraR EQ/ACK data-transfer handsh ake. In the 
Target role, ACK is received as a response to the REQ sig- 
nal. 

ATN. Attention (Bidirectional; Open Drain, Activ e LOW). 
Driven by an Initiator, received by the target. ATN indicates 
an Attention condition. 

BSY. Busy (Bidirectional; Open Drain, Active LOW). This 
signal indicates that the SCSI Bus is being used and can 
be driven by both the Initiator and the Target device. 

C/D. Control/Data (Bidirectional; Open Drain, Active 
LOW). Driven by the Target and received by the Initiator. 
C/D indicates whether Control or Data information is on the 
Data Bus. 



I/O. Input/Output (Bidirectional; Open Drain, Active LOW). 
I/O is a signal driven by a Target which controls the direc- 
tion of data movement on the SCSI Bus. TRUE indicates 
input to the Initiator. This signal is also used to distinguish 
between Selection and Reselection phases. 

MSG. Message (Bidirectional; Open Drain, Active LOW). 
MSG is a signal driven by the Target during the Message 
phase. This signal is received by the Initiator. 



REQ. Request (Bidirectional; Open Drain, Active LOW). 
Driven by a Target a nd received by the initator, REQ indi- 
cates a request for a REQ/ACK data-transfer handshake. 



RST. SCSI Bus RESET(Bidirectional; Open Drain, Active 
LOW). The RST signal indicates a SCSI Bus RESET con- 
dition. 

DBo-DB7,DBP. Data Bits Parity Bit (Bidirectional; Open 
Drain, Active LOW). These eight data bits (DBQ-DB7), plus 
a parity bit (DBP) form the Data Bus. DB7 is the most sig- 
nificant bit (MSB) and has the highest priority during the 
Arbitration phase. Data parity is odd. Parity is always 
generated and optionally checked. Parity is not valid during 
Arbitration. 

SEL. Setecf (Bidirectional; Open Drain, Active LOW). SEL 
is used by an Initiator to select a Target, or by a Target to 
reselect an Initiator. 



57 



FUNCTIONAL DESCRIPTION 



General: The Z5380 Small Computer System Interface 
(SCSI) device has a set of eight registers that are control- 
led by the CPU. By reading and writing the appropriate 
registers, the CPU may initiate any SCSI Bus activity or 
may sample and assert any signal on the SCSI Bus. This 
allows the user to implement all or any of the SCSI protocol 
in software. These registers are read (written) by act ivat- 
i ng C S with an address on A0-A2 and then issuing an IOR 
(IOW) pulse. This section describes the operation of the 
internal registers (Reference Table 1) 

REGISTER SUMMARY 

Address 



A2 


At 


AO 


R/W 


Register Name 











R 


Current SCSI Data 











W 


Output Data 








1 


R/W 


Initiator Command 





1 





R/W 


Mode 





1 


1 


R/W 


Target Command 


1 








R 


Current SCSI Bus Status 


1 








W 


Select Enable 


1 





1 


R 


Bus and Status 


1 





1 


W 


Start DMA Send 


1 


1 





R 


Input Data 


1 


1 





W 


Start DMA Target Receive 


1 


1 


1 


R 


Reset Parity/Interrupts 


1 


1 


1 


W 


Start DMA Initiator Receive 



TABLE 1. REGISTER SUMMARY 



Data Registers :The data registers are used to transfer 
SCSI commands, data, data, status, and message bytes 
between the microprocessor Data Bus and the SCSI Bus. 
The Z5380 does not interpret any information that passes 
through the data registers. The data registers consist of the 
transparent Current SCSI Data Register, the Output Data 
Register, and the Input Data Register. 

Current SCSI Data Register - Address (Read Only): 
The Current SCSI Data Register (Reference Figure 1 ) is a 
read-only register which allows the microprocessor to read 
the active SCSI Data Bus. This is accomplished by activat- 
ing CS with an address on A2-A0 of 000 and issuing an IOR 
pulse. If parity checking is enabled, the SCSI Bus parity is 
checked at the beginning of the read cycle. This register is 
used during a programmed I/O data read or during Arbitra- 
tion to check for higher priority arbitrating devices. Parity 
is not guaranteed valid during Arbitration. 

7 6 5 4 3 2 1 



asserts the proper ID bits on the SCSI Bus during the Ar- 
bitration and Selection phases. 

7 6 5 4 3 2 1 



DB, DB, DB S DB, DB, DB, DB, DB, 

Figure3.0: Output Data Register 

Input Data Register - Address 6 (Read Only):The Input 
Data Register (Reference Figure 3) is a read-only register 
that is used to read latched data from the SCSI Bus. Data 
is latched either during a DMA Target receive operation 
when ACK goes active or during a DMA Initiator receive 
when REQ goes active. The DMA MODE bit (port 2, bit 1) 
must be set before data can be latched in the Input Data 
Reg ister . This register is read under DMA control using 
IOR and DACK. Parity is optionally checked when the Input 
Data Register is loaded. 

7 6 5 4 3 2 1 



DB. DB 6 OB s DB 4 DB 3 DB, DB, DB Q 

Figure 4.0: Input Data Register 

Initiator Command Register - Address 1 (read/write): 
The Initiator Command Register (Reference Figures 5.0, 
5. 1 ) is a read/write register which asserts certain SCSI Bus 
signals, monitors those signals, and monitors the progress 
of bus arbitration. Many of these bits are significant only 
when being used as an Initiator; however, most can be 
used during Target role operation. 

7 6 5 4 3 2 1 



ASSERT AIP LA ASSERT ASSERT ASSERT ASSERT ASSERT 

RST ACK BSY SEL ATf4 DATA 

BUS 

Figure 5.0: Initiator Command Register - Register Read 



7 6 5 4 3 2 1 



OB 7 DB 6 DB 6 DB 4 DB, DB. DB, DB ri 

Figure 2.0: Current SCSI Data Register 

Output Data Register - Address (Write Only ):The Out- 
put Data Register (Reference Figure 2) is a write-only 
register that is used to send data to the SCSI Bus. This is 
accomplished by either using a normal CPU write, or under 
DMA control, by using IOW and DACK. This register also 



ASSERT TEST DIFF ASSERT ASSERT ASSERT ASSERT ASSERT 

RST MODE ENBL ACK BSV SEL ATN DATA 

BUS 

Figure 5.1 : Initiator Command Register - Register Write 

The following describes the operation of all bits in the In- 
itiator Command Register. 



58 



Bit -ASSERT DATA BUS: The ASSERT DATA BUS bit, 
when set, allows the contents of the Output Data Register 
to be enabled as chip outputs on the signals DB0-DB7. 
Parity is also generated and asserted on DBP. 

When connected as an Initiator, the outputs are only 
enabled if the TARGETMODE bit (port 2, bit 6) is FALSE, 
the received si gnal I/O is FALSE, and the phase signals 
(C/D , I/O, and MSG) match the conte nts of the ASSERT 
C/D, ASSERT I/O, and ASSERT MSG in the Target Com- 
mand Register. 

This bit should also be set during DMA send operations. 

Bit 1 - ASSERT ATN ATN may be asserted on the SCSI 
Bus by setting this bit to a one (1 ) if the TARGETMODE bit 
(port 2, bit 6) is FALSE. ATN is normally asserted by the 
initiator to requ est a Message Out bus phase. Note that 
since ASSERT SEL and A SSERT ATN are in the same 
register, a selec t with ATN may be implemented with one 
CPU write. ATN may be deasserted by resetting this bit to 
zero. A read of this register simply reflects the status of this 
bit. 

Bit 2 - ASSERT SEL Writing a one (1 ) into this bit position 
asserts SEL onto the SCSI Bus. SEL is normally ass erted 
after Arbitration has been successfully completed. SEL 
may be disabled by resetting bit 2 to a zero. A read of this 
register reflects the status of this bit. 

Bit 3 - ASSERT BSY Writing a one (1 ) into this bit position 
ass erts B SY onto the SCSI Bus. C onversely, a zero resets 
the BSY signal. Asserting BSY indicates a successful 
selection or reselection. Resetting this bit creates a Bus- 
Disconnect condition. Reading this register reflects bit 
status. 

Bit 4 - ASSERT ACK Bit 4 is used by the bus initiator to 
assert ACK on the SCSI Bus. In order to assert ACK, the 
TARGETMODE bit (port 2, bit 6) must be FALSE. Writing 
a zero to this bit deasserts ACK. Reading this register 
reflects bit status. 

Bit 5 - DIFF ENBL (Differential Enable) (WRITE Bit) 
Bit 5 should be written with a zero for proper operation. 

Bit 5 - LA (Lost Arbitration) (Read Bit) Bit 5, when ac- 
tive, indicates that the Z5380 detected a Bus-Free condi- 
tion, arbitrated for use of the bus by asserting BSY and its 
ID on the Data Bus, and lost Arbitration due to SEL being 
asserted by another bus device. This bit is active only when 
the ARBITRATE bit (port 2, bit 0) is active. 

Bit 6 - TEST MODE (Write Bit) Bit 6 is written during a test 
environment to disable all output drivers, effectively remov- 
ing the Z5380 from the circuit. Resetting this bit returns the 
part to normal operation. 

Bit 6 - AIP (Arbitration in Progress) (Read Bit) Bit 6 is 

used to determine if Arbitration is in progress, for this bit to 
be active, the ARBITRATE bit (port 2, bit 0) must have been 



set previously. It indicates that a Bus-Free condition has 
been detected and that the chip has asserted BSY and put 
the contents of the Output Data Register (port 0) onto the 
SCSI Bus. AIP will remain active until the ARBITRATE bit 
is reset. 

Bit 7 - ASSERT RST Whenever a one is written to bit 7 of 
the Initiator Command Register, the RST signal is asserted 
on the SCSI Bus. The RST signal will rem ain asserted until 
this bit is reset or until an external RESET occurs. After this 
bit is set (1 ), IRQ goes active and all internal logic and con- 
trol registers are reset (except for the interrupt latch and 
the ASSERT RST bit). Writing a ze ro to bit 7 of the Initiator 
Command Register deasserts the RST signal. The status 
of this bit is monitored by reading the Initiator Command 
Register. 

Mode Register - Address 2 (Read/Write): The Mode 
Register controls the operation of the chip. This register 
determines whether the Z5380 operates as an Initiator or 
a Target, whether DMA transfers are being used, whether 
parity is checked, and whether interrupts are generated on 
various external conditions. This register is read to check 
the value of these internal control bits (Reference Figure 
6.0) 

7 6 5 4 3 2 1 



BLOCK TAR- ENABLE ENABLE ENABLE MONI- DMA ARBI- 

MODE GET PARITY PARITY EOP TOR MODE TRATE 

DMA MODE CHECK- INTER- INTER- BUSY 

ING RUPT RUPT 

Figure 6.0: Mode Register 

Bit - ARBITRATE The ARBITRATE bis is set (1 ) to start 
the Arbitration process. Prior to setting this bit, the Output 
Data Register should contain the proper SCSI device ID 
value. Only one data bit should be active for SCSI Bus Ar- 
bitration. The Z5380 waits for a Bus-Free condition before 
entering the Arbitration phase. The results of the Arbitra- 
tion phase is determined by reading the status bits LA and 
AIP (port 1 , bits 5 and 6, respectively). 

Bit 1 - DMA MODE The DMA MODE bit is normally used 
to enable a DMA transfer and must be set (1 ) prior to writ- 
ing ports 5 through 7. Ports 5 through 7 are used 

to start DMA transfers. The TARGETMODE bit (port 2, bit 
6) must be consistent with writes to port 6 and 7 [i.e., set 
(1 ) for a write to port 6 and reset (0) for a write to port 7]. 
The control bit ASSERT DATA BUS (port 1 , bit 0) must be 
TRUE (1) for all DMA send operations. In the DMA mode, 
REQ and ACK are automatically controlled. 

The DMA MODE bit is not reset upon the receipt of an EOP 
signal. Any DMA transfer is stopped by writing a zero into 
this bit location; however, care must be taken not to cause 
CS and DACK to be active simultaneously. 

Bit 2 - MONITOR BUSY The MONITOR BUSY bit, when 
TRUE (1), causes an interrupt to be generated for an un- 
expected loss of BSY. When the interrupt is generated due 



59 



to loss ol BSY, the lower six bits ot the Initiator Command 
Register are reset (0) and all signals are removed from the 
SCSI Bus. 

Bit 3 - ENABLE EOP INTERRUPT The enable EOP inter- 
rupt, when set (1), causes an interrupt to occur when the 
EOP (End of Process) signal is received from the DMA 
controller logic. 

Bit 4 - ENABLE PARITY INTERRUPT The ENABLE 
PARITY INTERRUPT bit, when set (1 ), will cause an inter- 
rupt (IRQ) to occur if a parity error is detected. A parity in- 
terrupt will only be generated if the ENABLE PARITY 
CHECKING bit (bit 5) is also enabled (1 ). 

Bit 5 - ENABLE PARITY CHECKING The ENABLE 
PARITY CHECKING bit determines whether parity errors 
are ignored or saved in the parity error latch. If this bit is 
reset (0), parity is ignored. Conversely, if this bit is set (1 ), 
parity errors are saved. 

Bit 6 - TARGETMODE The TARGETMODE bit allows the 
Z5380 to operate as either a SCSI Bus Initiator, bit reset 
(0), or as a SCSI Bus Target device, bit set (1). If the sig- 
nals ATN and ACK are to be asserted on the SCSI Bus, 
the TARG ETM ODE b it must be reset (0). If the signals C/D, 
I/O, MSG, and REQ are to be asserted on the SCSI Bus, 
the TARGETMODE bit must be set (1 ). 

Bit 7 - BLOCK MODE DMA The BLOCK MODE DMA bit 
controls the characteristics of the DMA DRQ-DACK hand- 
shake. When this bit is reset (0) and the DMA MODE bit is 
active (1 ), the DMA handshake uses t he nor mal interlock- 
ed handshake, and the rising edge of DACK indicates the 
end of each byte being transferred. In block mode opera- 
tions, BLOCK MODE DMA bit set (1) and DMA MODE bit 
set (1), the end of IOR or IOW signifies the end of each 
byte transferred and DACK is allowed to remain active 
throughout the DMA operation. READY can then be used 
to request the next transfer. 

Target Command Register - Address 3 (Read/Write) 
When connected as a target device, the Target Command 
Register (Reference Figure 7) allows the CPU to control 
the SCSI Bus Information Transfer phase and/or to assert 
REQ by writing this register. The TARGETMODE bit (port 
2, bit 6) must be TRUE (1 ) for bus assertion to occur. The 
SCSI Bus phases are described in Table 2 



SCSI INFORMATION TRANSFER PHASES 



Bus Phase 


ASSERT 


ASSERT 


ASSERT 




175 


C/D 


MSG 


Data Out 











Unspecified 








1 


Command 





1 





Message Out 





1 


1 


Data In 


1 








Unspecified 


1 





1 


Status 


1 


1 





Message In 


1 


1 


1 



TABLE 2. SCSI INFORMATION TRANSFER PHASES 



When connected as an Initiator with D MA Mode TRUE, If 
the phase lines (I/O, C/D, and MSG) do not match the 
phase bits in the Target Command Regist er, a phase-mis- 
match interrupt is generated when REQ goes activ e. To 
send data as an Ini tiator, the ASSERT I/O, ASSERT C/D, 
and ASSERT MSG bits must match the corresponding bits 
in the Curre nt SCSI Bus Status Register (port 4). The AS- 
SERT REQ bit (bit 3) has no meaning when operating as 
an Initiator. 



7 6 5 4 3 2 1 



X X X X ASSERT ASSERT ASSERT ASSERT 

REO MSG C'O I/O 

Figure 7.0: Target Command Register 

Current SCSI Bus Status Register - Address 4 (Read 
Only): The Current SCSI Bus Register is a read-only 
register which is used to monitor seven SCSI Bus control 
signals, plus the Data Bus parity bit. For example, an In- 
itiator device can use this register to determine the current 
bus phase and to poll REQ for pending data transfers. This 
register may also be used to determine why a particular in- 
terrupt occurred. Figure 8.0 describes the Current SCSI 
Bus Status Register. 



7 6 5 4 3 2 t 



RST BSY REO MSG C D 10 SEL DBP 



Figure 8.0: Current SCSI Bus Status Register 

Select Enable Register - Address 4 (Write Only) The 
Select Enable Register (Reference Figure 8) is a write-only 
register which is used as a mask to monitor a signal ID 
during a selection attempt. The simultaneous occurrence 
of the correct ID bit, BSY FALSE, and SEL TRUE will cause 
an interrupt. This interrupt can be disabled by resetting all 
bits in this register. If the ENABLE PARITY CHECKING bit 
(port 2, bit 5) is active (1), parity is checked during selec- 
tion. 



7 6 5 4 3 2 1 



DB. DB 6 OB 5 DB t D8 3 DB Z OB , DB Q 



Figure 9.0: Select Enable Register 



60 



Bus and Status Register - Address 5 (Read Only) The 

Bus and Status Register (Reference Figure 1 0.0) is a read- 
only register which can be used to monitor the remaining 
SCSI control signals not found in the Current SCSI Bus 
Status Register (ATN and ACK), as well as six other status 
bits. The following describes each bit of the Bus Status 
Register individually. 

7 6 5 4 3 2 1 



END DMA PARITY INTER PHASE BUSY ATN ACK 

OF RE- ERROR RUPT MATCH ERROR 

DMA OUEST RE- 
QUEST 
ACTIVE 

Figure 10.0: Bus and Status Register 

Bit - ACK Bit reflects the condition of the SCSI Bus 
control signal ACK. This signal is normally monitored by 
the Target device. 

Bit 1 - ATN Bit 1 reflects the condition of the SCSI Bus con- 
trol signal ATN. This signal is normally monitored by the 
Target device. 

Bit 2 - BUSY ERROR The BUSY ERROR bit is active if an 
unexpected loss of the BSY signal has occurred. This latch 
is set whenever the MONITOR BUSY bit (port 2, bit 2) is 
TRUE and BSY is FALSE. An unexpected loss of BSY dis- 
ables any SCSI outputs and resets the DMA MODE bit 
(port 2, bit 1). 

Bit 3 - PHASE MATCH The SCSI signals, MSG, CTD, and 
I/O, represent the current information Transfer phase. The 
PHASE MATCH bit indicates whether the current SCSI 
Bus phase matches the lower 3 bits of the Target Com- 
mand Register. PHASE MATCH is continuously updated 
and is only significant when operating as a Bus Initiator. A 
phase match is required for data transfers to occur on the 
SCSI Bus. 

Bit 4 - INTERRUPT REQUEST ACTIVE Bit 4 is set if an 
enabled interrupt condition occurs. It reflects the current 
state of the IRQ output and can be cleared by reading the 
Reset Parity/Interrupt Register (port 7). 

Bit 5 - PARITY ERROR Bit 5 is set if a parity error occurs 
during a data receive or a device selection. The PARITY 
ERROR bit can only be set (1) if the ENABLE PARITY 
CHECK bit (port 2, bit 5) is active (1). This bit may be 
cleared by reading the Reset Parity/Interrupt Register (port 
7). 

Bit 6 - DMA REQUEST The DMA REQUEST bit allows the 
CPU to sam ple the output pin DRQ. DRQ can be cleared 
by asserting DACK or by resetting the DMA MODE bit (bit 
1 ) in the Mode Register (port 2). The DRQ signal does not 
reset when a phase-mismatch interrupt occurs. 

Bit 7 - END OF DMA TRANSFER The END Or DMA 
TRANSFER bit is set if EOP, DACK, and either IOR or IOW 
are simultaneously active for at least 1 00ns. Since the EOP 



signal can occur during th e last byt e sen t to the Output 
Data Register (Port 0), the REQ and ACK signals should 
be monitored to ensure that the last byte has been trans- 
ferred. This bit is reset when the DMA MODE bit is reset 
(0) in the Mode Register (port 2). 

DMA Registers Three write-only registers are used to in- 
itiate all DMA activity. They are: Start DMA Send (port 5), 
Start DMA Target Receive (port 6), and Start DMA Initiator 
Receive (port 7). Performing a write operation into one of 
these registers starts the desired type of DMA transfer. 
Data presented to the Z5380 on signals D0-D7 during the 
register write is meaningless and has no effect on the 
operation. Prior to writing these registers; the BLOCK 
MODE DMA bit (bit 7), the DMA MODE bit (bit 1), and the 
TARGETMODE bit (bit 6) in the Mode Register (port 2) 
must be appropriately set. The individual registers are 
briefly described as follows: 

Start DMA Send - Address 5 (Write Only) This register 
is written to initiate a DMA send, from the DMA to the SCSI 
Bus, for either Initiator or Target role operations. The DMA 
MODE bit (port 2, bit 1 ) is set prior to writing this register. 

Start DMA Target Receive - Address 6 (Write Only)This 
register is written to initiate a DMA receive - from the SCSI 
Bus to the DMA, for Target operation only. The DMA 
MODE bit (bit 1) and the TARGETMODE bit (bit 6) in the 
Mode Register (port 2) must both be set (1 ) prior to writing 
this register. 

Start DMA Initiator Receive - Address 7 (Write 
Only )This register is written to initiate a DMA receive - from 
the SCSI Bus to the DMA, for Initiator operation only. The 
DMA MODE bit (bit 6) must be FALSE (0) in the Mode 
Register (port 2) prior to writing this register. 

Reset Parity/Interrupt - Address 7 (Read 
Only): Reading this register resets the PARITY 
ERROR bit (bit 5), the INTERRUPT REQUEST bit 
(bit4), and the BUSY ERROR bit (bit 2) in the Bus 
and Status Register (port 5). 

On-Chip SCSI Hardware Support: The Z5380 is easy to 
use because of its simple architecture. The chip allows 
direct control and monitoring of the SCSI Bus by providing 
a latch for each signal. However, portions of the protocol 
define timings which are much too quick for traditional 
microprocessors to control. Therefore, hardware suppport 
has been provided for DMA transfers, bus arbitration, 
phasechange monitoring, bus disconnection, bus reset, 
parity generation, parity checking, and device selec- 
tion/reselection. 

Arbitration is acc ompli sh ed us ing a Bus-Free filter to con- 
tinuously monitor BSY. If BSY remains inactive for at least 
400ns, the SCSI Bus is considered free and Arb itratio n 
may begin. Arbitration will begin if the bus is free, SEL is 
inactive, and the ARBITRAT ION b it (port 2, bit 0) is active. 
Once arbitration has begun (BSY asserted), an arbitration 



61 



may begin. Arbitration will begin if the bus is free, SEL is 
inactive, and the ARBITRAT ION b it (port 2, bit 0) is active. 
Once arbitration has begun (BSY asserted), an arbitration 
delay of 2.2 us must elapse before the Data Bus can be 
examined to determine if Arbitration is enabled. This delay 
is implemented in the controlling software driver. 

The ZS380 is a clockwise device. Delays such as bus-free 
delay, bus-set delay, and bus-settle delay are imple- 
mented using gate delays. These delays may differ be- 
tween devices because of inherent process variations, but 
are well within the proposed ANSI X3T9.2 specification. 

INTERRUPTS The Z5380 provides an interrupt output 
(IRQ) to indicate a task completion or an abnormal bus oc- 
currence. The use of interrupts is optional and may be dis- 
abled by resetting the appropriate bits in the Mode Register 
(port 2) or the Select Enable Register (port 4). 

When an interrupt occurs, the Bus and Status Register and 
the Current SCSI Bus Status Register (Reference Figures 
10 & 11) must be read to determine which condition 
created the interrupt. IRQ can be reset simply by reading 
the Reset Pari ty/Interru pt Register (port 7) or by an exter- 
nal chip reset (RESET active for 200 ns). 

Assuming the Z5380 has been properly initialized, an in- 
terrupt will be gene rated; if the chip is selected or 
reselected, if an EOP signal occurs during a DMA transfer, 
if a SCSI Bus reset occurs, if a parity error occurs during 
a data transfer, if a bus phase mismatch occurs, or if a 
SCSI Bus disconnection occurs. 

Selection/Reselection The Z5380 generates a select in- 
terrupt if SEL is TRUE (1), its device ID is TRUE (1), and 
BSY is FALSE for at least a bus-settle delay (400 ns). If 
I/O is active, this is considered a reselect interrupt. The cor- 
rect ID bit is determined by a match in the Select Enable 
Register (port 4). Only a single bit match is required to 
generate an interrupt. This interrupt may be disabled by 
writing zeros into all bits of the Select Enable Register. 

If parity is supported, parity should be good during the 
selection phase. Therefore, if the ENABLE PARITY bit 
(port 2, bit 5) is active, the PARITY ERROR bit is checked 
to ensure that a proper selection has occurred. The 
ENABLE PARITY INI tRUPT bit need not be set for this 
interrupt to be generated. 

The proposed SCSI specification also requires that no 
more than two device ID s be active during the selection 
process. To ensure this, the Current SCSI Data Register 
(port 0) is read. 

The proper values forthe Bus and Status Register (port 5) 
and the Current SCSI Bus Status Register (port 4) are dis- 
played in Figures 1 1 .0 and 1 2.0, respectively. 



7 6 5 4 3 2 1 



1 x x0 



END DMA PARITY INTER- PHASE BUSY ATN ACK 

OF RE- ERROR RUPT MATCH ERROR 

DMA QUEST RE- 

OUEST 

ACTIVE 

Figure 1 1 .0: Bus and Status Register 

7 6 5 4 3 2 10 



o x x x 1 x 



RST BSY REQ MSG CD I/O SEL DBP 

Figure 12.0: Current SCSI Bus Status Register 

End of Process (EOP) Interrupt : An End of Process sig- 
nal (EOP) which occurs during a DMA transfer 
(DMAMODE TRUE) will set the END OF DMA Status bit 
(port 5, bit 7) and will optionally generate an interrupt if 
ENABLE EOP INTERRUPT bit (port 2, bit 3) is TRUE. The 
EOP p ulse will not be recognized (END OF DMA bit set) 
unless EOP, DACK, and either IOR or IOW are concurrent- 
ly activ e for at least 100 ns. DMA transfers can still occur 
if EOP was not asserted at the correct time. This interrupt 
is disabled by resetting the ENABLE EOP INTERRUPT bit. 

The proper values for the Bus and Status Register (port 5) 
and the Current SCSI Bus Status Register (port 4) for this 
interrupt are shown in Figures 13.0 and 14.0. 

7 6 5 4 3 2 1 



1 1 



END DMA PARITY INTER- PHASE BUSY ATN ACK 

OF RE- ERROR RUPT MATCH ERROR 

DMA OUEST RE- 
OUEST 
ACTIVE 

Figure 13.0: Bus and Status Register 

7 6 5 4 3 2 1 



1 1 x X x o X 



RST BSY REO MSG C/D I/O SEL DBP 

Figure 14.0: Current SCSI Bus Status Register 

The END OF DMA bit is used to determine when a block 
transfer is complete. Receive operations are complete 
when there is no data left in the chip and no additional 
handshakes occurring. The only exception to this is receiv- 
ing data as an Initiator and the Target opts to send addi- 
tional data for the same phase. In this case, REQ goes 
active and the new data is present in the Input Data 
Regis ter. Since a phase-mismatch interrupt will not occur, 
REQ and ACK need to be sampled to determine that the 
Target is attempting to send more data. 

For send operations, the END OF DMA bit is set when the 
DMA finishes its transfer, but the SCSI tra nsfer m ay s till be 
in progress. If connected as a Target, REQ and ACK 
should be sampled until both are FALSE. If connected as 
an Initiator, a phase change interrupt is used to signal the 



62 



completion of the previous phase. It is possible for the Tar- 
get to request additional data for the same pha se. In this 
case, a phase change will not occur and both REQ and 
ACK are sampled to determine when the last byte was 
transferred. 

SC SI Bu s Reset:The Z5380 generates an interrupt when 
the RST signal transitions to TRUE. The device releases 
all bus signals within a bus-clear delay (800 ns) of this tran- 
sition. This interrupt also occurs after setting the ASSERT 
RST bit (po rt 1 , bit 7). This interrupt cannot be disabled, 
(note: RST is not latched in bit 7 of the Current SCSI Bus 
Status Register and is not active when this port is read. For 
this case, the Bus Reset interrupt is determined by default). 

The proper values for the Bus and Status Register (port 5) 
and the Current SCSI Bus Status Register (port 4) are dis- 
played in Figures 15.0 and 16.0, respectively. 

7 6 5 4 3 2 10 



Ox 1 X X X 



END DMA PARITY INTER- PHASE BUSY ATN ACK 

OF re ERROR RUPT MATCH ERROR 

0MA OUEST RE 

QUEST 

ACTIVE 

Figure 15.0: Bus and Status Register 



7 6 5 4 3 2 1 



xx X x X X X 



RST 8SY REQ MSG C/D I/O SEL DBP 



Figure 16.0: Current SCSI Bus Status Register 

Parity Error.An interrupt is generated for a received parity 
error if the ENABLE PARITY CHECK (bit 5) and the 
ENABLE PARITY INTERRUPT (bit 4) bits are set (1); in 
the Mode Register (port 2). Parity is checked during a read 
of the Current SCSI Data Register (port 0) and during a 
DMA receive operation. A parity error can be detected 
without generating an interrupt by disabling the ENABLE 
PARITY INTERRUPT bit and checking the PARITY 
ERROR flag (port 5, bit 5). 

The proper values for the Bus and Status Register (port 5) 
and the Current SCSI Bus Status Register (port 4) are dis- 
played in Figures 17.0 and 18.0, respectively. 

7 6 5 4 3 2 1 



OX 1 1 1 X X 



END DMA PARITY INTER. PHASE BUSY ATN ACK 

OF RE. ERROR RUPT MATCH ERROR 

DMA OUEST RE- 

OUEST 

ACTIVE 

Figure 17.0: Bus and Status Register 



6 5 4 3 2 1 



1 1 X X x o x 



RST BSY REQ MSG C/D l-O SEL DBP 

Figure 18.0: Current SCSI Bus Status Register 

Bus Phase Mismatch:The SCSI phase lines are com- 
prised of the signals I/O, C/D, and MSG. These signals are 
compared with the corresponding bits in the Target Com- 
mand Registe r: ASS ERT I/O (bit 0), ASSERT C/D (bit 1), 
and ASSERT MSG (bit 2). The comparison occurs con- 
tinually and is reflected in the PHASE MATCH bit (bit 3) of 
the Bus and Status Register (port 5). If the DMA MODE bit 
(port 2, bit 1 ) is active and a phase mismatch occurs when 
REQ transitions from FALSE to TRUE, an interrupt (IRQ) 
is generated. 

A phase mismatch prevents the recognition of REQ and 
removes the chip from the bus during an Initiator send 
operation (DB0-DB7 and DBP will not be driven even 
though the ASSERT DATA BUS bit (port 1 , bit 0) is active). 
This may be disabled by resetting the DMA MODE bit 
(Note: it is possible for this interrupt to occur when con- 
nected as a Target if another device is driving the phase 
lines to a different state). 

The proper values for the Bus and Status Register (port 5) 
and the Current SCSI Bus Status Register (port 4) are dis- 
played in Figures 19.0 and 20.0, respectively. 



7-6 5 4 3 2 1 












1 








X 





END 
OF 
DMA 


DMA 

RE- 
QUEST 


PARITY 
ERROR 


INTER 
RUPT 
RE- 
QUEST 
ACTIVE 


PHASE 
MATCH 


BUSY 
ERROR 


ATN 


ACK 




Figure 19.0 


: Bus and Status Re< 


jister 




7 


6 


5 


4 


3 


2 


i 








1 


X 


X 


X 


X 





X 


RST 


BSY 


REQ 


MSG 


C/D 


I/O 


SEL 


DBP 



Figure 20.0: Current SCSI Bus Status Register 

Loss of BSY:ff the MONITOR BUSY bit (bit 2) in the Mode 
Register (port 2) is active, an interrupt is generated if the 
BSY signal goes FALSE for at least a bus-settle delay (400 
ns). This interrupt is disabled by resetting the MONITOR 
BUSY bit. Register values are displayed in Figures 21.0 
and 22.0. 



1X10 



END DMA PARITY INTER- PHASE BUSY Jf^ JT^ 

OF RE ERROR RUPT MATCH ERROR 

OMA OUEST RE 

QUEST 
ACTIVE 

Figure 21.0: Bus and Status Register 



63 



7 6 5 4 3 2 1 



oooxxxoo 



nST BSV REO MSG CfO I/O SEL OBP 

Figure 22.0: Current SCSI Bus Status Register 

Reset Conditions: Three possible reset situations exist 
with the Z5380, as follows: 

Hardware Chip Reset When the signal RST is active for 
at least 200 ns, the Z5380 device is re-initialized and all in- 
ternal logic and control registers are cleared. This is a chip 
reset only and does not create a SCSI Bus-Reset condi- 
tion. 

SCSI Bus Reset(RST)Recelved: When a SCSI RST sig- 
nal is received, an IRQ interrupt is generated and a chip 
reset is performed. All internal logic and registers are 
clear ed, except for the IRQ interrupt latch and the ASSERT 
RST bit (b it 7) i n the Initiator Command Register (port 1 ). 
(Note: the RST signal may be sampled by reading he Cur- 
rent SCSI Bus Status Register (port 4); however, this sig- 
nal is not latched and may not be present when this port is 
read.) 

SCSI Bus Reset (RST) Issued : If the CPU sets the AS- 
SERT RST bit (bit 7) in the Initiator Command Register 
(port 1), the RST signal goes active on the SCSI Bus and 
an internal reset is performed. Again, all internal logic and 
registers are c leare d except for the IRQ interrupt latch and 
the ASSERT RST b it (bi t 7) in the Initiator Command 
Register (port 1 ). TheRST signal will continue to be active 
until the ASSERT RST bit is reset or until a hardware reset 
occurs. 

Data Transfers: Data is transferred between SCSI Bus 
devices in one of four modes: 1) Programmed I/O, 2) Nor- 
mal DMA, 3) Block Mode DMA, or 4) Pseudo DMA. The 
following sections describe these modes in detail (Note: for 
all data transfer operations DACK and CS should never be 
active simultaneously). 

Programmed l/OTransfers: Programmed I/O is the most 
primitive form of data transfer. The REQ and ACK hand- 
shake signals are individually monitored and asserted by 
reading and writing the appropriate register bits. This type 
of transfer is normally used when transferring small blocks 
of data such as command blocks or message and status 
bytes. An Initiator send operation would begin by setting the 
C/D, I/O, and MSG bits in the Target Command Register 
to the correct state so that a phase match exists. In addi- 
tion to the phase match condition, it is necessary for the 
ASSERT DATA BUS bit (port 1 , bit 0) to be TRUE and the 
received I/O signal to be FALSE for the Z5380 to send 
data. For each transfer, the data is loaded into the Output 
Data Register (port 0). The CPU the n waits for the REQ bit 
(port 4, bit 5) to become active. Once REQ goes active, the 
PHASE Match bit (port 5, bit 3) is ch ecked and the AS- 
SERT ACK bit (port 1 , bit 4) is set. The REQ bit is sampled 



until it becomes FALSE and the CPU resets the ASSERT 
ACK bit to complete the transfer. 

Normal DMA Mode: DMA transfers are normally used for 
large block transfers. The SCSI chip outputs a DMA re- 
quest (DRQ) whenever it is ready for a byte transfer. Ex- 
ternal DMA logic uses this DRQ signal to generate DACK 
and an IOR or an IO W pulse to the Z5380. DRQ goes in- 
active when DACK is asserted and DACK goes inactive 
some time after the minimum read or write pulse width. 
This p rocess is repeated for every byte. For this mode, 
DACK should not be allowed to cycle unless a transfer is 
taking place. 

Block Mode DMA: Some popular DMA controllers, such 
as the 951 7A, provide a Block Mode DMA transfer. This 
type of transfer allows the DM A controller to transfer blocks 
of data without relinquishing the use of the Data Bus to the 
CPU after each byte is transferred; thus, faster transfer 
rates are achieved by eliminating the repetitive access and 
release of the CPU Bus. If the BLOCK MODE DMA bit (port 
2, bit 7) is active, the Z5380 begins the tran sfer by assert- 
ing DRQ. The DMA controller then asserts DACK for the 
remainder of the block transfer. DRQ goes inactive for the 
duration of the transfer. The READY output is used to con- 
trol th e trans fer rate. Non-Block Mode DMA transfers end 
when DA CK go e s FAL SE, whereas Block Mode transfers 
end when IOR or IOW becomes inactive. Since this is the 
case, DMA transfers may be started sooner in a Block 
Mode transfer.To obtain optimum performance in Block 
Mode operation, the DMA logic optionally uses the normal 
DMA mode interlocking handshake. READY is still avail- 
able to throttle the DMA transfer, but DRQ is 30 to 40 ns 
faster than READY and is used to start the cycle 
sooner.The methods described under "Halting a DMA 
Operation" apply for all DMA operations. 

Pseudo DMAMode:To avoid the tedium of monitoring and 
asserting the request/acknowledge handshake signals for 
programmed I/O transfers, the system may be designed to 
implement a pseudo DMA mode. This mode is imple- 
mented by programming the Z5380 to operate in the DMA 
mode, but using the CPU to emulate the DMA handshake. 
DRQ may be detected by polling the DMA REQUEST bit 
(bit 6) in the Bus and Status Register (port 5), by sampling 
the signal through an external port, or by using it to 
generate a CPU interrupt. Once DRQ is detected, the CPU 
can perform a read or write data transfer. This CPU 
read/writ e is e xter nally d ecode d to generate the ap- 
propriate DACK and IOR or IOW signals.. 

Often, external decoding logic is necessary to generate the 
Z5380 CS signal. This same logic may be used to generate 
DACK at no extra system cost and provide an increased 
performance in programmed I/O transfers. 

Halting a DMAOperation: The EOP signal is not the only 
way to halt a DMA transfer. A bus phase mismatch or a 
reset of the DMA MODE bit (port 2, bit 1 ) can also terminate 
a DMA cycle for the current bus phase. 



64 



Using the EOP Signal If EOP is use d-it s ho uld b e asserted 
for at least 1 00 ns while DACK and TOR or IO W are simul- 
taneously active. Note, however, that if IOR or IOW is not 
active, an i nterru pt is generated, but the DMA activity con- 
tinues. Th e EOP signal does not reset the DMA MODE bit. 
Since the EOP signal can occur durin g the last bytt' sent 
to the Output Data Register (port 0), the REQ and ACK sig- 
nals are monitored to ensure that the last byte has trans- 
ferred. 

Bus Phase Mismatch Interrupt : A bus phase mismatch 
interrupt is used to halt the transfer if operating as an In- 
itiator. Using this method frees the host from maintaining 
a data length counter and frees the DMA logic from provid- 
ing the EOP signal. If performing an Initiator send opera- 
tion, the Z5380 requires DACK to cycle before ACK goes 
inactive. Since phase changes cannot occur if ACK is ac- 
tive, either DACK must be cycled after the last byte is sent 
or the DMA MODE bit must be reset in order to receive the 
phase mismatch interrupt. 



Resetting the DMA MODE Bit: A DMA operation may be 
halted at any time simply by resetting the DMA MODE bit. 
It is recomm ended that the DMA MODE bit be reset after 
receiving an EOP or bus phase-mismatch interrupt. The 
DMA MODE bit must then be set before writing any of the 
start DMA registers for subsequent bus phases. 

If resetting the DMA MODE bit is used instead of EOP for 
Target role operation, then care must be taken to reset this 
bit at the proper time. If receiving data as a Target device, 
the DMA MODE bit must b e reset once the last DRQ is 
recei ved an d before DACK is asserted to prevent an addi- 
tional REQ from occurring. Resetting this bit causes DRQ 
to go inactive. However, the last byte received remains in 
the Input Data Register and may be obtain ed eith er b y per - 
forming a norm al CP U read or by cycling DACK and IOR. 
In most cases, EOP is easier to use when operating as a 
Target device. 



65 



READ 

CURRENT SCSI DATA (00) 
7 6 5 4 3 



CURRENT SCSI BUS STATUS (04) 
210 76543210 



DB 7 



DB„ 



INITIATOR COMMAND REGISTER (01) 
7 6 5 4 3 2 1 



DBP 



SEL 



MSG 



C/D 



I/O 



REQ 



RST 



BSY 



As sert D ata Bus 
Assert ATN 

Assert SEL 
Assert BSY 



Assert ACK 
Lost Arbitration 
Arbitration in Progress 

Assert RST 



MODE REGISTER (02) 
7 6 5 4 



BUS & STATUS REGISTER (05) 
7 6 5 4 3 2 



ACK 



ATN 
Busy Error 
Phase Match 
Interrupt Request 
Parity Error 



Arbitration 
DMA M ode 
Monitor BSY 
Enable EOP Interrupt 
Enable Parity Interrupt 
Enable Parity Checking 
Target Mode 
Block Mode DMA 



DMA Request 
End of DMA 



INPUT DATA REGISTER (06) 
7 6 5 4 3 



DB 7 



DB„ 



TARGET COMMAND REGISTER (03) 



7 


6 


5 


4 


3 


2 


1 

































| Assert I/O 
Assert C/D 



RESET PARITY/INTERRUPT (07) 
7 6 5 4 3 2 



Assert MSG 



Assert REQ 



Figure 27.0 Register Reference Chart 



66 



WRITE 

OUTPUT DATA REGISTER (00) SELECT ENABLE REGISTER (04) 

7654 3 210 76543210 



DB, 



DB„ 



DB, 



DB. 



INITIATOR COMMAND REGISTER (01) 
7 6 5 4 3 2 1 



START DMA SEND (05) 

7 6 5 4 3 2 1 



Assert ACK 

Los! Arbitration 

Test Mode 



Assert Data Bus 
Asser t ATN 

Assert SEL START DMA TARGET RECEIVE (06) 

Assert BSY 

7 6 5 4 3 2 1 



Assert RST 



MODE REGISTER (02) 

7 6 5 4 3 2 



START DMA INITIATOR RECEIVE (07) 
7 6 5 4 3 2 1 



Arbitration 

DMA Mode 
Monitor BSY 
Enable EOP Interrupt 
Enable Parity Interrupt 
Enable Parity Checking 
Target Mode 
Block Mode DMA 



TARGET COMMAND REGISTER (03) 
7 6 5 4 3 2 1 



X 


X 






















Assert I/O 
Assert cTd 



NOTE: X = DONT CARE 



Assert MSG 



Assert REQ 



Figure 27.0 Register Reference Chart 



67 



ABSOLUTE MAXIMUM RATINGS 

Store Temperature -65 to + 1 50 deg C 

Supply Voltage on Any Pin 

with Respect to Ground -0.5 to + 7.0 V 
Power Dissipation 0.2 W 

Stresses above those listed under ABSOLUTE MAXIMUM 
RATINGS may cause permanent device failure. 
Functionality at or above these limits is not implied. Ex- 
posure to absolute maximum ratings tor extended periods 
may affect device reliability. 



OPERATING RANGE 

Commercial (C) Devices 

Temperature (Ta) Oto + 70 C 

Supply Voltage (VCC) + 4.74 to + 5.25 V 

Operating ranges define those limits between which the 
functionality of the device is gauranteed. 



DC CHARACTERISTICS over operating range unless otherwise specified 



Parameter Description 


Test Conditions 


Min. 


Max. 




Input Signal Requirements 


HIGH-Level, Input VI H 




2.0 


5.25 


V 


LOW-Level, Input V IL 




-0.3 


0.8 


V 


HIGH-Level, Input 
Current, l IH on: 
SCSI Bus Pins 


V 5.25 V. 

v 1L = o 




50 


/uA 


All Other Pins 






10 




LOW-Level Input 
Current, l IL on: 
SCSI Bus Pins 


V IH = 5.25 V. 




-50 




All Other Pins 


V |L = 




-10 




Output Signal Requirements 


HIGH-Level Output 
on All Pins 


V DD =4.75V. 
\ w = 3.0 mA 


2.4 




V 


LOW-Level Output on: 
SCSI Bus Pins 


V DD =4.75V. 
I^ = 48.0 mA 




0.5 


V 


All Other Pins 


Vod=4.75V. 
1^ = 7.0 mA 




0.5 


V 



68 



SWITCHING TEST CIRCUIT 



From Output 
Under Test 




SWITCHING TEST WAVEFORM 



2.4 



0.4 



Test 
Points 



SWITCHING CHARACTERISTICS/WAVEFORMS (Cont.) 

CPU Write Cycle 







Z0538010 


Z053801 5 


Name 


Description 


Min. Max. 


Min. Max. Units 


T1 


Address Setup to Write Enable' 


20 


ns 


T2 


Address Hold from End Write Enable* 


20 


ns 


T3 


Write Enable Width* 


70 


ns 


T4 


Chip Select Hold from End of iOW 





ns 


T5 


Data Setup to end of Write Enable* 


50 


ns 


T6 


Data Hold Time from End of IOW 


30 


ns 



'Write Enable is the occurrence of IOW and DACK 
*o* 2 7777X 



X///////// 



°0-D 7 



////////////A 



i/m/im/ 



CPU Read Cycle 



Z0538010 



Z0538015 



Name Description 



Min. Max. 



Min. 



Max. Units 



T1 


Address Setup to Read Enable* 


20 


ns 


T2 


Address Hold from End Read Enable* 


20 


ns 


T3 


Chip Select Hold from End of (OR 





ns 


T4 


Data Access Time from Read Enable* 


130 


ns 


T5 


Data Hold Time from End of iOR 


20 


ns 



•Read Enable is the occurrence of IOR and CS 

v* 7777* 



X ///////// 



-TI- 



CS 



X. 



-•07 2ZZZZZZZZZZZZZZZZZZX 



xzzzzzzzzzz 



70 



SWITCHING CHARACTERISTICS/WAVEFORMS (Cont.) 



DMA Write (Non-Block Mode) Target Send Cycle 

Z0538010 Z0538015 



Name Description 



Min. Max. 



Min. 



Max. Units 



T1 

T2 

T3 

T4 

T5 

T6 

T7 

T8 

T9 

T10 

T11 

T12 

T13 



DRQ FALSE from DACK TRUE 
DACR FALSE to DRQ TRUE 
Write Enable Width* 
DACK Hold from End of iOW 
Data Setup to End of Write Enable* 
Data Hold Time from End of IOW 
Width of EOP Pulse (Note 1) 
ACK TRUE to REQ FALSE 



REQ from End of DACK (ACK FALSE) 
ACK TRUE to DRQ TRUE (Target) 
REQ from End of ACK (DACK FALSE) 
Data Hold from Write Enable 
Data Setup to REQ TRUE (Target) 





130 


ns 


30 




ns 


100 




ns 


o 




ns 


50 




ns 


40 




ns 


100 




ns 


25 


125 


ns 


30 


150 


ns 


15 


110 


ns 


20 


150 


ns 


15 




ns 


60 




ns 



*Write Enable is the occurrence of IOW and DACK 

Notes: 1. EOP, IOW, and DACK must be concurrently TRUE for at least T7 
for proper recognition of the EOP pulse. 



*** 7 2ZZZZZ2ZZZZZX 



X 



« T3- 



> mm mm 



-T9- 



SWITCHING CHARACTERISTICS/WAVEFORMS (Cont'd.) 



DMA Write (Non-Block Mode) Initiator Send Cycle 

Z0538010 Z0538015 



Name Description 



Min. Max. Min. Max. Units 



T1 

T2 

T3 

T4 

T5 

T6 

T7 

T8 

T9 

T10 

T11 

T12 



DRQ FALSE from DACK TRUE 



DACK FALSE to DRQ TRUE 
Write Enable Width* 
DACK Hold from End of IOW 
Data Setup to End of Write Enable* 
Data Hold Time from End of IOW 
Width of EOP Pulse (Note 1) 
REQ TRUE to ACK TRUE 
REQ FALSE to DRQ TRUE 



DACK FALSE to ACK FALSE 
iOW FALSE to Valid SCSI Data 
Data Hold from Write Enable 





130 


ns 


30 




ns 


100 




ns 







ns 


50 




ns 


40 




ns 


100 




ns 


20 


160 


ns 


20 


110 


ns 


25 


150 


ns 




100 


ns 


15 




ns 



'Write Enable is the occurrence of IOW and DACK 

Notes: 1 . EOP, IOW, and DACK must be concurrently TRUE for at least T7 
for proper recognition of the EOP pulse. 



A 



00°, //////////// , 



M 



-T1— U— T2^^~ 



\ / 



pBo-DB 7 

DBP 



> //////////// 



y m mK 



72 



SWITCHING CHARACTERISTICS/WAVEFORMS (Cont'd.) 



DMA Read (Non-Block Mode) Target Receive Cycle 



Z0538010 



Z0538015 



Name Description 



Min. Max. Min. Max. Units 



T1 

T2 

T3 

T4 

T5 

T6 

T7 

T8 

T9 

T10 

T11 

T12 



DRQ FALSE from DACK TRUE 



DACK FALSE to DRQ TRUE 



DACK Hold Time from End of IOR 
Data Access Time from Read Enable* 
Data Hold Time from End of iOR 
Width of EOP Pulse (Note 1) 
ACK TRUE to DRQ TRUE 



ACK TRUE to REQ FALSE 
ACK FALSE to REQ TRUE l 
Data Setup Time to ACK 
Data Hold Time from ACK 





130 


ns 


30 




ns 







ns 




115 


ns 


20 




ns 


100 




ns 


15 


110 


ns 


30 


150 


ns 


25 


125 


ns 


20 


150 


ns 


20 




ns 


50 




ns 



•Read Enable is the occurrence of IOR and DACK 

Notes: 1 . EOP, IOR, and DACK must be co ncurrently TRUE for at least T6 
for proper recognition of the EOP pulse. 



V 



y 



y 



n -D 7 



//////////////>///> 



y 



y 



x ////////// 



— \ 

-T10 



DB g -DB 7 ^ 



^niiiiin/niiiinnnunnn 



73 



SWITCHING CHARACTERISTICS/WAVEFORMS (Cont'd.) 



DMA Read (Non-Block Mode) Initiator Receive Cycle 

Z0538010 Z0538015 



Name Description 



Min. Max. Min. Max. Units 



T1 

T2 

T3 

T4 

T5 

T6 

T7 

T8 

T9 

T10 

T11 

T12 



DRQ FALSE from DACK TRUE 



DACK FALSE to DRQ TRUE 
DACK Hold Time from End of IOR 
Data Access Time from Read Enable* 
Data Hold Time from End of iOR 
Width of EOP Pulse (Note 1) 
RETT TRUE to DRQ TRUE 



30 


20 
100 
20 

DACK FALSE to ACK FALSE (REQ FALSE)25 
REQ TRUE to ACK TRUE 20 



REQ FALSE to ACK FALSE (DACK FALSE)15 
Data Setup Time to REQ 20 
Data Hold Time from REQ 50 



130 



115 



150 
160 
160 
140 



ns 
ns 
ns 
ns 
ns 
ns 
ns 
ns 
ns 
ns 
ns 
ns 



'Read Enable is the occurrence of IOR and DACK 

Notes: 1 . EOP, IOR, and DACK must be concurrently TRUE for at least T6 
for proper recognition of the EOP pulse. 



A 



DACK 



°o-°7 //////////// 7777, 



DBq DB 7 ,f 
DBP N 



a 



zzzx 



A 



A 



y j/uii/// 



A 



x////////////////// ////////////// 



74 



SWITCHING CHARACTERISTICS/WAVEFORMS (Cont'd.) 

DMA Write (Block Mode) Target Send Cycle 



Z0538010 



Z0538015 



Name 


Description 


Min. 


Max. 


Min. Max. Units 


T1 


DRQ FALSE from DACK TRUE 




130 


ns 


T2 


Write Enable Width* 

fill I™ i_i lauic itiuui 


100 




ns 


T3 


WritP Rprovprv Timp 

wine ncuuvtsijr imic 


120 




ns 


T4 


Data Sptiin tn Fnri nf WritP Fnahlp* 

L/ala <JCIU(J IU 1— 1 >\J \JI WHIG 1— 1 IQUIv 


50 




ns 


T5 


Data HnlH Timp frnm FnH nf IOW 

L-SCllCl 1 IwlU 1 II 1 1X7 II UMI L— 1 IVJ Ul lw»l 


40 




ns 


T6 


Width of EOP Pulse (Note 1) 


100 




ns 


T7 


ACK TRUE to REQ FALSE 


25 


125 


ns 


T8 


REQ from End of iOW (ACK FALSE) 


40 


180 


ns 


T9 


REQ from End of ACK (iOW FALSE) 


20 


170 


ns 


T10 


ACK TRUE to READY TRUE 


20 


140 


ns 


T11 


READY TRUE to IOW FALSE 


70 




ns 


T12 


IOW FALSE to READY FALSE 


20 


140 


ns 


T13 


Data Hold from ACK TRUE 


40 




ns 


T14 


Data Setup to REQ TRUE 


60 




ns 



•Write Enable is the occurrence of IOW and DACK 

Notes: 1. EOP, IOW, and DACK must be c oncurrently TRUE for at least T6 
for proper recognition of the EOP pulse. 



•a*, / //////////// )< 



■« T6 ► 



\ / 



mnimm 



y 



-T12 tX 

X- 



4 T13- 



DBq-DB 7 
DBP 



4 T14 ► 



SWITCHING CHARACTERISTICS/WAVEFORMS (Cont.) 

DMA Read (Block Mode) Target Receive Cycle 



Z0538010 Z0538015 



Name 


Description 


Mtn. 


Max. 


Min. Max. Units 




DRO FAI from nAPK TRI IF 




ion 
1 ou 


ns 




iv^n neuuvcjiy i m it? 


1 C\J 




nc 

1 lb 


TO 
1 O 


ua\a Muutsoo i line? Hum ntJciu tzi iduicr 




1 1 u 


nc 
l lo 


T4 


Datn hnlH Timp frnm FnH nf (OR 


20 




ns 


T5 


Width of EOP Pulse (Note 1) 


100 




ns 


T6 


IOR FALSE to REQ TRUE (ACK FALSE) 


30 


190 


ns 


T7 


ACK TRUE to REQ FALSE 


25 


125 


ns 


T8 


ACK FALSE to REQ TRUE (IOR FALSE) 


20 


170 


ns 


T9 


ACK TRUE to READY TRUE 


20 


140 


ns 


T10 


READY TRUE to Valid Data 




50 


ns 


T11 


TOR FALSE to READY FALSE 


20 


140 


ns 


T12 


Data Setup Time to ACK 


20 




ns 


T13 


Data Hold Time from ACK 


50 




ns 



'Read Enable is the occurrence of IOR and DACK 

Notes: 1 . EOP, IOR, and DACK must be concurrently TRUE for at least T5 
for proper recognition of the EOP pulse. 



— s L 



-0 07 nn/ii/mmn. 



zzzz>: 



DB -DB 7 
DBP 





< T13 t 






< > 



7 



xzzzzzzzzz 



-T6- 



_y — 

« T11 >j^ ^ 



X//////////////// //////////////// 



76 



SWITCHING CHARACTERISTICS/WAVEFORMS (Cont.) 



Arbitration 



Z0538010 Z0538015 



Name 


Description 


Min. 


Max. 


Min. Max. Units 


T1 


Bus Clear from SEL. TRUE 




600 


ns 


T2 


Arbitrate Start drom BSY FALSE 


1200 


2200 


ns 


T3 


Bus Clear from BSY FALSE 




1100 


ns 



rst 

SEL 
BS* 



y 



WIMUHHMlJl 



BSY (IN) 











r mnti/h 


\ 









Name Description 



Reset 



Z0538010 



Z0538015 



Min. Max. Min. Max. Units 



T1 



Minimum Width of Reset 



200 



ns 



* T1 » 



Z5380 NOTES 



Edge triggered RST Interrupt - If the SCSI Bus is not 6) A phase-mismatch interrupt is not gauranteed after a 
terminated, the RST interrupt is continually generates. Reselection for the following reasons: 



1) 



2) TRUE End of DMA Interrup - The Am5380 generated 
an interrupt when it receives the last byte from the 
DMA, not when the last byte is transferred to the SCSI 

Bus. 

3) Return to READY after EOP Interrupt When operating 
in Block mode DMA, the Z5380 does nor return the 
READY signal to a Ready condition. This locks up the 
bus and prevents the CPU from executing. 

4) SCSI handshake after EOP occurs - If an EOP occurs 
when receiving data, a subsequent REQ wil cause 
ACK to be asserted even though no DRQ is issued. 

5) During Reselection, if the Target Command Register 
does not reflect the current bus phase (most likely Data 
Out), the Reselection interrupt may get reset. 



-DMA MODE bit must be set in order to receive a phase 
mismatch interrupt 

-DMA MODE bit cannot be set unless BSY is active 

-BSY cannot be asserted until after the Reselection 
has occured 

-Once BSY is asserted, the Target may assert REQ in 
less than 500 ns 

-The phase-mi smat ch interrupt is generated on the 
active edg e of R EQ. If the DMA MODE bit is not set 
before the REQ goes active, the phase-mismatch 
interrupt will not occur. 



78 



Zilog 



Product Specification 



October 1988 



Z7220A 

High-Performance 
Graphics Display Controller 



Description 

The Z7220A High-performance Graphics Display Con- 
troller (HGDC) is an intelligent microprocessor peripheral 
designed to be the heart of a high-performance raster- 
scan computer graphics and character display system. 
Positioned between the video display memory and the 
microprocessor bus, the HGDC performs the tasks 
needed to generate the raster display and manage the 
display memory. Processor software overhead is mini- 
mized by the HGDC's sophisticated instruction set, 
graphics figure drawing, and DMA transfer capabilities. 
The display memory supported by the HGDC can be 
configured in any number of formats and sizes up to 
256K 1 6-bit words. The display can be zoomed and 
panned, while partitioned screen areas can be indepen- 
dently scrolled. With its light pen input and multiple con- 
troller capability, the HGDC is ideal for advanced 
computer graphics applications. 

System Considerations 

The HGDC is designed to work with a general purpose 
microprocessor to implement a high-performance com- 
puter graphics system. Through the division of labor 
established by the HGDC's design, each of the system 
components is used to the maximum extent through a 
six-level hierarchy of simultaneous tasks. At the lowest 
level, the HGDC generates the basic video raster timing, 
including sync and blanking signals. Partitioned areas 
on the screen and zooming are also accomplished at this 
level. At the next level, video display memory is modified 
during the figure drawing operations and data moves. 
Third, display memory addresses are calculated pixel by 
pixel as drawing progresses. Outside the HGDC at the 
next level, preliminary calculations are done to prepare 
drawing parameters. At the fifth level, the picture must 
be represented as a list of graphics figures drawable by 
the HGDC. Finally, this representation must be manipu- 
lated, stored, and communicated. By handling the first 
three levels, the HGDC takes care of the high-speed and 
repetitive tasks required to implement a graphics system. 



Features 

□ Microprocessor Interface 
DMA transfers 

FIFO Command Buffering 

□ Display Memory Interface 
Up to 256K words of 1 6 bits 

Read-Modify-Write (RMW) Display Memory cycles as 
fast as 500ns 

Dynamic RAM refresh cycles for nonaccessed 
memory 

□ Light Pen Input 

□ Drawing Hold Input 



□ 
O 

□ 

□ 



□ 



□ 



□ 



□ 



C 



□ 



External video synchronization mode 
Graphics Mode 

Four megabit, bit-mapped display memory 
Character Mode 

8K character code and attributes display memory 

Mixed Graphics and Character Mode 

64K if all characters 

1 megapixel if all graphics 

Graphics Capabilities 

Figure drawing of lines, arc/circles, rectangles, and 

graphics characters in 500ns per pixel 

Display 1 024-by-1 024 pixels with 4 planes of color or 

grayscale 

Two independently scrollable areas 

Character Capabilities 

Auto cursor advance 

Four independently scrollable areas 

Programmable cursor height 

Characters per row: up to 256 

Character rows per screen: up to 1 00 

Video Display Format 

Zoom magnification factors of 1 to 16 

Panning 

Command-settable video raster parameters 
Technology 

Single +5V, NMOS, 40-pin DIP 

DMA Capability 

Byte or word transfers 

4 clock periods per byte transferred 

On-ch ip pull-up resistor for VSYNC/EXT, HSYNC and 

DACK, and a pull-down resistor for LPEN/DH 



Pin Configuration 



2XWCLK L" 1 

DBiNC 2 

HSYNC C 3 

V/EXTSVNCC 4 

BLANK [ 5 

ALE C 6 

DRQC 7 

DACRC 8 

RD[ 9 

wHC 10 

AoC 11 
DB.C 12 
OB, Z 13 
DB, L" 14 
DBjL" 15 
DB, L" 16 
DB.L" 17 
DB, C 18 
DB 7 C 19 
GNO C 20 



40] 
39 3 
38 3 
37 ] 
36 3 
35 5 
34 J t 
33 3 I 
32 3 I 
31 3 I 
30 3 
29 3 
28 3 

27 : 

26 3 
25 3 
24 D 
23 3 
22 3 
21 3 



A„ 
A,. 
AD 15 
AD„ 
AD, 3 



AD. 
AD, 
AD. 
AD 5 
AD, 
AD 3 
AD 2 
AD, 
AO. 

LPEN/DH 



79 



1 I § i i i i 



cm 
daq< 



6 5 4 3 2 1 44 



41 40 \ 



AD 13 
AD 12 
AD11 
AD10 



am 



18 19 2D 21 22 23 24 25 26 27 



44-Pin Plastic Chip Carrier (PCC) 
Pin Assignments 



Pin Identification 





Pin 






No. 




Direct! 


Ml Function 


1 


2xWCLK 


In 


Clock Input 


2 


DBIN 


Out 


Display Memory Read Input Flag 


3 


HSYNC 


Out 


Honzontal Video Sync Output 


4 


V/EXTSYNC 


In/Out 


Vertical Video Sync Output or External VSVNC Input 


5 


BLANK 


Out 


CRT Blanking Output 


6 


aleiras") 


Out 


Address Latch Enable Output 


7 


DRQ 


Out 


DMA Request Output 


S 


DACK 


In 


DMA Acknowledge Input 


9 


HO 


In 


Read Strobe Input tor Microprocessor Interlace 


10 


WR 


In 


Write Strobe Input for Microprocessor Interlace 


11 


*0 


k 


Address Select Input tor Microprocessor Interface 


12-19 


Da -OB r 


In/Out 


Bidirectional Data Bus to Host Microprocessor 


20 


QND 




Ground 


21 


LPENVOH 


In 


Light Pen Detect Input/Drawing Hold Input 


22-34 


AD.-AD,, 


In/Out 


Address and Data Lines to Display Memory 


35-37 


AD„-AD„ 


In/Out 


Utilization Varies with Mode ol Operation 


38 


*M 


Out 


Utilization Vanes with Mode of Operation 


39 


*17 


Out 


Utilization Varies with Mode of Operation 


40 


Vcc 




+5V ± 10% Power Supply 



Character Mode Pin Utilization 



35-37 AD,,-AD, S 



Una Counter Bits to 2 Outputs 



Line Counter Bit 3 Output 



Cursor Output and Una Counter Bit 4 



Mixed Mode Pin Utilization 



35-37 AD„-AO, 5 



Address and Data Bits 13 to 15 



Attribute Blink end Clear Line Counter Output 



*17 



Graphics Mode Pin Utilization 



35-37 AO„-AD, i 



Address snd Data Bits 13 to 15 



Address Bit 16 Output 



Block Diagram 



DREQ C-*- 
DACK. 



DMA 

Control 



DB-Oto7<3£) 



A-Oo 
HBo 
WRO 



Microprocessor 
Interface 



Status Reg. 
DATA READ Reg 



FIFO 
Buffer 
16x9 



Video Sync 
Generator 



' HSYNC 
-t-OV/EXT SYNC 
i BLANK 



Command 
Processor 
with 
Control ROM 
128x14 



Memory 
Timing 
Generator 



—P ALE 
DBIN 



Zoom & Pan 
Controller 



Parameter 
RAM 
16x8 



Drawing 
Controller 



+ SVo 
GNDo 
2xWCLKO 



Display 
Memory 
Controller 
with 
Refresh Counter 
Line Counter 
RMW Data Path 



A-17 
A-16 
AD- 15 
AD-14 
— OAD-13 

j?>AD-0to12 



Light Pen 
Deglitch a 



Logic 



HGDC Components 

Microprocessor Bus Interface 

Control of the HGDC by the system microprocessor is 
achieved through an 8-bit bidirectional interface. The 
status register is readable at any time. Access to the 
FIFO buffer is coordinated through flags in the status 
register and operates independently of the various inter- 
nal HGDC operations, due to the separate data bus con- 
necting the interface and the FIFO buffer. 
Command Processor 

The contents of the FIFO are interpreted by the command 
processor. The command bytes are decoded, and the 
succeeding parameters are distributed to their proper 
destinations within the HGDC. The command processor 
yields to the bus interface when both access the FIFO 
simultaneously. 
DMA Control 

The DMA control circuitry in the HGDC coordinates trans- 
fers over the microprocessor interface when using an 
external DMA controller. The DMA Request and Acknowl- 
edge handshake lines directly interface with a DMA con- 
troller, so that display data can be moved between the 
microprocessor memory and the display memory. 
Parameter RAM 

The 1 6-byte RAM stores parameters that are used repeti- 
tively during the display and drawing processes. In char- 
acter mode, this RAM holds four sets of partitioned 
display area parameters; in graphics mode, the drawing 
pattern and graphics character take the place of two of 
the sets of parameters. 



80 



Video Sync Generator 

Based on the clock input, the sync logic generates the 
raster timing signals for almost any interlaced, non- 
interlaced, or "repeat field" interlaced video format. The 
generator is programmed during the idle period following 
a reset. In video sync slave mode, it coordinates timing 
between multiple HGDCs. 
Memory Timing Generator 

The memory timing circuitry provides two memory cycle 
types: a two-clock period refresh cycle and the read- 
modify-write (RMW) cycle which takes four clock periods. 
The memory control signals needed to drive the display 
memory devices are easily generated from the HGDCs 
ALE and DBIN outputs. 

Zoom and Pan Controller 

Based on the programmable zoom display factor and the 
display area entries in the parameter RAM, the zoom and 
pan controller determines when to advance to the next 
memory address for display refresh and when to go on to 
the next display area. A horizontal zoom is produced by 
slowing down the display refresh rate while maintaining 
the video sync rates. Vertical zoom is accomplished by 
repeatedly accessing each line a number of times equal 
to the horizontal repeat. Once the line count for a display 
area is exhausted, the controller accesses the starting 
address and line count of the next display area from the 
parameter RAM. The system microprocessor, by modify- 
ing a display area starting address, can pan in any direc- 
tion, independently of the other display areas. 
Drawing Controller 

The drawing processor contains the logic necessary to 
calculate the addresses and positions of the pixels of the 
various graphics figures. Given a starting point and the 
appropriate drawing parameters, the drawing controller 
needs no further assistance to complete the figure 
drawing. 

Display Memory Controller 

The display memory controller's tasks are numerous. Its 
primary purpose is to multiplex the address and data 
information in and out of the display memory. It also con- 
tains the 1 6-bit logic unit used to modify the display mem- 
pry contents during RMW cycles, the character mode 
line counter, and the refresh counter for dynamic RAMS. 
The memory controller apportions the video field time 
between the various types of cycles. 
Light Pen Deglitcher/Drawing Hold 
Only if two rising edges on the light pen input occur at 
the same point during successive video fields are the 
pulses accepted as a valid light pen detection. A status 
bit indicates to the system microprocessor that the light 
pen register contains a valid address. If this input is held 
high for a period greater than four 2xWCLK cycles, draw- 
ing execution is halted. 

Programmer's View of HGDC 

The HGDC occupies two addresses on the system micro- 
processor bus through which the HGDCs status register 
and FIFO are accessed. Commands and parameters are 
written into the HGDCs FIFO and are differentiated 



based on address bit Ao- The status register or the FIFO 
can be read as selected by the address line. 



Status Register 



I I I I I I 



-J I I I I I l_ 



Parameter Into FIFO 



J I I I I L_ 



Command Into FIFO 



HGDC Microprocessor Bus Interface Registers 

Commands to the HGDC take the form of a command 
byte followed by a series of parameter bytes as needed 
for specifying the details of the command. The command 
processor decodes the commands, unpacks the parame- 
ters, loads them into the appropriate registers within the 
HGDC, and initiates the required operations. 

The commands available in the HGDC can be organized 
into five categories as described in the following section. 

HGDC Commands Summary 

Video Control Commands 

1. RESET1 Resets the HGDC to its idle state. 

Resynchronizes video timing. Blanks 
the display. 

2. RESET2 Resets the HGDC to its idle state. 

Does not resynchronize video timing. 
Blanks the display. 

3. RESET3 Resets the HGDC to its idle state. 

Does not resynchronize video timing. 
Does not blank the display. 

4. SYNC Specifies the video display format. 

5. VSYNC Selects master or slave video synchro- 

nization mode. 

6. CCHAR Specifies the cursor and character 

row heights. 
Display Control Commands 

1. START Ends Idle mode and unblanks the 

display. 

2. BLANK1 Controls the blanking and unblanking 

of the display, along with video resyn- 
chronization. 

3. BLANK2 Controls the blanking and unblanking 

of the display. Does not blank the 
display. 

4. ZOOM Specifies zoom factors for the display 

and graphics characters writing. 

5. CURS Sets the position of the cursor in dis- 

play memory. 

6. PRAM Defines starting addresses and 

lengths of the display areas and speci- 
fies the eight bytes for the graphics 
character. 

7. PITCH Specifies the width of the X dimension 

of display memory. 



81 



Drawing Control Commands 



memory. 



1. 


WDAT 


2. 


MASK 


3. 


FIGS 


4. 


FIGD 


5. 


GCHRD 



Specifies the parameters for the draw- 
ing controller. 

Draws the figure as specified above. 



display memory. 
Data Read Commands 

1. RDAT Reads data words or bytes from dis- 

play memory. 

2. CURD Reads the cursor position. 

3. LPRD Reads the light pen address. 
DMA Control Commands 

1 . DMAR Requests a DMA read transfer. 

2. DMAW Requests a DMA write transfer. 



Status Register Flags 



- FIFO Full 

- FIFO Empty 

- Drawing in Progress 

- DMA Execute 

- Vertical Sync Active 



il Blank Active. 



Vertical Blank Active 
- Light P 



Status Register (SR) 

SR-7: Light Pen Detect 

When this bit is set to 1 , the light pen address (LAD) reg- 
ister contains a deglitched value that the system micro- 
processor may read. This flag is reset after the 3-byte 
LAD is moved into the FIFO in response to the light pen 
read command. 

SR-6: Horizontal Blank Active/Vertical Blank Active 

A 1 value for this flag signifies that horizontal retrace 
blanking or vertical retrace blanking is currently under- 
way dependent on the status of the VH bit in SYNC or the 
RESETx parameter 6. 
SR-5: Vertical Sync 

Vertical retrace sync occurs while this flag is a 1 . The 

vertical sync flag coordinates display format modifying 

commands to the blanked interval surrounding vertical 

sync. This eliminates display disturbances. 

SR-4: DMA Execute 

This bit is a 1 during DMA data transfers. 

SR-3: Drawing in Progress 

While the HGDC is drawing a graphics figure, this status 
bit is a 1 . 



SR-2: FIFO Empty 

This bit and the FIFO-full flag coordinate system micro- 
processor accesses with the HGDC FIFO. When it is 1 , 
the Empty flag ensures that all the commands and pa- 
rameters previously sent to the HGDC have been 
interpreted. 
SR-1:FIFO Full 

A 1 at this flag indicates a full FIFO in the HGDC. A 
ensures that there is room for at least one byte. This flag 
needs to be checked before each write into the HGDC. 
SR-0: Data Ready 

When this flag is a 1 , it indicates that a byte is available to 
be read by the system microprocessor. This bit must be 
tested before each read operation. It drops to a while 
the data is transferred from the FIFO into the micropro- 
cessor interface data register. 

FIFO Operation and Command Protocol 

The first-in, first-out buffer (FIFO) in the HGDC handles 
the command dialogue with the system microprocessor. 
This flow of information uses a half-duplex technique, in 
which the single 16-location FIFO is used for both direc- 
tions of data movement, one direction at a time. The 
FIFO's direction is controlled by the system microproces- 
sor through the HGDC's command set. The host micro- 
processor coordinates these transfers by checking the 
appropriate status register bits. 
The command protocol used by the HGDC requires dif- 
ferentiation of the first byte of a command sequence from 
the succeeding bytes. The first byte contains the opera- 
tion code and the remaining bytes carry parameters. 
Writing into the HGDC causes the FIFO to store a flag 
value alongside the data byte to signify whether the byte 
was written into the command or the parameter address. 
The command processor in the HGDC tests this bit as it 
interprets the entries in the FIFO. 

The receipt of a command byte by the command proces- 
sor marks the end of any previous operation. The number 
of parameter bytes supplied with a command is cut short 
by the receipt of the next command byte. A read opera- 
tion from the HGDC to the microprocessor can be termi- 
nated at any time by the next command. 

The FIFO changes direction under the control of the 
system microprocessor. Commands written into the 
HGDC always put the FIFO into write mode if it was not in 
it already. If it was in read mode, any read data in the 
FIFO at the time of the turnaround is lost. Commands 
which require an HGDC response, such as RDAT, CURD 
and LPRD, put the FIFO into read mode after trie com- 
mand is interpreted by the HGDC's command processor. 
Any commands and parameters behind the read-evoking 
command are discarded when the FIFO direction is 
reversed. 



82 



Read-Modify-Write Cycle 

Data transfers between the HGDC and the display mem- 
ory are accomplished using a read-modify-write (RMW) 
memory cycle. The four-clock period timing of the RMW 
cycle is used to: 1 ) output the address, 2) read data from 
the memory, 3) modify the data, and 4) write the modified 
data back into the initially selected memory address. 
This type of memory cycle is used for all interactions with 
display memory including DMA transfers, except for the 
two-clock period display and RAM refresh cycles. 

The operations performed during the modify portion of 
the RMW cycle merit additional explanation. The circuitry 
in the HGDC uses three main elements: the Pattern regis- 
ter, the Mask register, and the 1 6-bit Logic unit. The Pat- 
tern register holds the data pattern to be moved into 
memory. It is loaded by the WDAT parameters or, during 
drawing, from the parameter RAM. The Mask register 
contents determine which bits of the read data will be 
modified. Based on the contents of these registers, the 
Logic unit performs the selected operations of REPLACE, 
COMPLEMENT, SET, or CLEAR on the data read from 
display memory. 

The Pattern register contents are ANDed with the Mask 
register contents to enable the actual modification of the 
memory read data, on a bit-by-bit basis. For graphics 
drawing, one bit at a time from the Pattern register is 
combined with the Mask. When ANDed with the bit set to 
a 1 in the Mask register, the proper single pixel is modi- 
fied by the Logic unit. For the next pixel in the figure, the 
next bit in the Pattern register is selected and the Mask 
register bit is moved to identify the pixel's location within 
the word. The Execution word address pointer register, 
EAD, is also adjusted as required to address the word 
containing the next pixel. 

In character mode, all of the bits in the Pattern register 
are used in parallel to form the respective bits of the mod- 
ify data word. Since the bits of the character code word 
are used in parallel, unlike the one-bit-at-a-time graphics 
drawing process, this facility allows any or all of the bits 
in a memory word to be modified in one RMW memory 
cycle. The Mask register must be loaded with ones in the 
positions where modification is to be permitted. 

The Mask register can be loaded in either of two ways. In 
graphics mode, the CURS command contains a 4-bit 
dAD field to specify the dot address. The command pro- 
cessor converts this parameter into the 1-of-1 6 format 
used in the Mask register for figure drawing. A full 1 6 bits 
can be loaded into the Mask register using the MASK 
command. In addition to the character mode use men- 
tioned above, the 16-bit MASK load is convenient in 
graphics mode when all of the pixels of a word are to be 
set to the same value. 

The Logic unit combines the data read from display mem- 
ory, the Pattern register, and the Mask register to gener- 
ate the data to be written back into display memory. Any 
one of four operations can be selected: REPLACE, COM- 
PLEMENT, CLEAR or SET. In each case, if the respective 
Mask bit is 0, that particular bit of the read data is re- 
turned to memory unmodified. If the Mask bit is 1 , the 
modification is enabled. With the REPLACE operation, 
the Pattern register data simply takes the place of the 
read data for modification enabled bits. For the other 



three operations, a in the modify data allows the read 
data bit to be returned to memory. A 1 value causes the 
specified operation to be performed in the bit positions 
with set Mask bits. 

Figure Drawing 

The HGDC draws graphics figures at the rate of one pixel 
per read-modify-write (RMW) display memory cycle. 
These cycles take four clock periods to complete. At a 
clock frequency of 8MHz, this is equal to 500ns. During 
the RMW cycle the HGDC simultaneously calculates the 
address and position of the next pixel to be drawn. 
The graphics figure drawing process depends on the 
display memory addressing structure. Groups of 16 hor- 
izontally adjacent pixels form the 16-bit words which are 
handled by the HGDC. Display memory is organized as a 
linearly addressed space of these words. Addressing of 
individual pixels is handled by the HGDC's internal RMW 
logic. 

During the drawing process, the HGDC finds the next 
pixel of the figure which is one of the eight nearest neigh- 
bors of the last pixel drawn. The HGDC assigns each of 
these eight directions a number from to 7, starting with 
straight down and proceeding counterclockwise. 



Drawing Directions 



Q'OO 

■\'i /' 
O-O'-O 

o o o 



Figure drawing requires the proper manipulation of the 
address and the pixel bit position according to the draw- 
ing direction to determine the next pixel of the figure. To 
move to the word above or below the current one, it is 
necessary to subtract or add the number of words per 
line in display memory. This parameter is called the pitch. 
To move to the word to either side, the Execute word 
address cursor, EAD, must be incremented or decre- 
mented as the dot address pointer bit reaches the LSB or 
the MSB of the Mask register. To move to a pixel within 
the same word, it is necessary to rotate the dot address 
pointer register to the right or left. The table below sum- 
marizes these operations for each direction. 



Dir 


Operations to Address the Next Pixel 


000 


EAD - P— *EAD 




001 


EAD - P— 'EAD 
dAD (MSB) = l:EAO - 


1— 'EAD dAD— LR 


010 


dAD (MSB) = 1 :EAD - 


1 — EAD dAD— LR 


011 


EAD - P— EAD 
dAD (MSB) = 1 :EAD — 


1 — EAD dAD— LR 


100 


EAD - P— EAD 




101 


EAD - P— EAD 
dAD (LSB) = 1:EAD - 


I — EAD dAD— RR 


110 


dAD (LSB) a 1:EAD - 


I — EAD dAD— RR 


111 


EAD - P-EAD 
dAD (LSB) = 1:EAD - 


I — EAD dAD— RR 



( P = Pilch, LR = Let! Rotate. RR = Right Rotate, EAD = Execute Word Address, and 
dAD = Dot Address stored in the Mask register. 



83 



Whole word drawing is useful for filling areas in memory 
with a single value. By setting the Mask register to all 1s 
with the MASK command, both the LSB and MSB of the 
dAD will always be 1 , so that the EAD value will be incre- 
mented or decremented for each cycle regardless of 
direction. One RMW cycle will be able to affect all 16 bits 
of the word for any drawing type. One bit in the Pattern 
register is used per RMW cycle to write all the bits of the 
word to the same value. The next Pattern bit is used for 
the word, etc. 

For the various figures, the effect of the initial direction 
upon the resulting drawing is shown below: 



done quickly, thereby minimizing the overall figure draw- 
ing time. The table below summarizes the parameters. 



Hi 


Line 


Arc 


Character 


Slant Char 


Rectangle 


000 


k 


K7 


mi 


\ 


n 


001 




r\ 






O 


010 


A 


L> 




✓ 


i i 


011 










o 


100 




•A 


nni 


\ 




101 






# 




o 


110 










r i 


111 










O 



Note that during line drawing, the angle of the line may 
be anywhere within the shaded octant defined by the DIR 
value. Arc drawing starts in the direction initially specified 
by the DIR value and veers into an arc as drawing pro- 
ceeds. An arc may be up to 45° in length. DMA transfers 
are done on word boundaries only, and follow the arrows 
indicated in the table to find successive word addresses. 
The slanted paths for DMA transfers indicate the HGDC 
changing both the X and Y components of the word ad- 
dress when moving to the next word. It does not follow a 
45° diagonal path by pixels. 

Drawing Parameters 

In preparation for graphics figure drawing, the HGDC's 
Drawing processor needs the figure type, direction and 
drawing parameters, the starting pixel address, and the 
pattern from the microprocessor. Once these are in place 
within the HGDC, the Figure Draw command, FIGD, 
initiates the drawing operation. From that point on, the 
system microprocessor is not involved in the drawing 
process. The HGDC Drawing controller coordinates the 
RMW circuitry and address registers to draw the speci- 
fied figure pixel by pixel. 

The algorithms used by the processor for figure drawing 
are designed to optimize its drawing speed. To this end, 
the specific details about the figure to be drawn are re- 
duced by the microprocessor to a form conducive to 
high-speed address calculations within the HGDC. In 
this way the repetitive, pixel-by-pixel calculations can be 



Drawing Type 


DC 


D 


D2 


D1 


DM 


Initial Value CD 





a 


8 


-1 


-1 


Line 


M 


2|4D| - 


mm - mi 


2|AD] 




Are® 


rain * 


r-1 


2<r-1) 


-1 


rain B J 




3 


A-1 


B-1 


-1 


A-1 


Area Fill 


B-1 


A 


A 






Graphic Character© 


B-1 


A 


A 






Read & Write Data 


W-1 










DMAW 


D-1 


C-1 








DMAR 


D-1 


C-1 


(C-1)ffit 







Notes: All numbers are shown in base 10 (or convenience. The HGDC accepts base 2 numbers 
(2s complement notation) where appropriate. 

© Initial values tor the various parameters remain as each drawing process ends. 

® Circles are drawn with 8 arcs, each ot which span 45°, so that sin * = 1/V2 and 
sin 8 = 0. 

® Graphic characters are a special case of bit-map area filling in which Band A « 8. If A 
= 8 there is no need to load D and D2. 



- 1 = All ONES value. 
- - No parameter bytes sent to HGDC for this parameter. 
Al = The larger at Ax or Ay. 
AD= The smaller at Ax or Ay. 
r= Radius of curvature, in pixels. 
>t> = Angle from major axis to end of the arc. 4> =s 45°. 
8 = Angle from major axis to start of the arc. e « 45°. 
t = Round up to the next higher integer. 
i = Round down to the next lower integer. 
A - Number of pixels in the initially specified direction. 
B = Number of pixels in the direction at right angles to the 

initially specified direction. 
W= Number of words to be accessed. 
C = Number ot bytes to be transferred in the initially specified 
direction. (Two bytes per word if word transfer mode 
is selected.) 

D = Number of words to be accessed in the direction at right 
angles to the initially specified direction. 
DC - Drawing count parameter which is one less than the num- 
ber of RMW cycles to be executed. 
DM = Dots masked from drawing during arc drawing, 
t = Needed only for word reads. 

Graphics Character Drawing 

Graphics characters can be drawn into display memory 
pixel by pixel. The up to 8-by-8 character display is loaded 
into the HGDC's parameter RAM by the system micropro- 
cessor. Consequently, there are no limitations on the 
character set used. By varying the drawing parameters 
and drawing direction, numerous drawing options are 
available. In area fill applications, a character can be 
written into display memory as many times as desired 
without reloading the parameter RAM. 

Once the parameter RAM has been loaded with up to 
eight graphics character bytes by the appropriate PRAM 
command, the GCHRD command can be used to draw 
the bytes into display memory starting at the cursor. The 
zoom magnification factor for writing, set by the ZOOM 
command, controls the size of the character written into 
the display memory in integer multiples of 1 through 16. 
The bit values in the PRAM are repeated horizontally and 
vertically the number of times specified by the zoom 
factor. 

The movement of these PRAM bytes to the display mem- 
ory is controlled by the parameters of the FIGS 
command. 



84 



Based on the specified height and width of the area to be 
drawn, the parameter RAM is scanned to fill the required 
area. 

For an 8-by-8 graphics character, the first pixel drawn 
uses the LSB of RA-1 5, the second pixel uses bit 1 of 
RA-1 5, and so on, until the MSB of RA-1 5 is reached. 
The HGDC jumps to the corresponding bit in RA-1 4 to 
continue the drawing. The progression then advances 
toward the LSB of RA-1 4. This snaking sequence is con- 
tinued for the other 6 PRAM bytes. This progression 
matches the sequence of display memory addresses 
calculated by the drawing processor as shown above. If 
the area is narrower than 8 pixels wide, the snaking will 
advance to the next PRAM byte before the MSB is 
reached. If the area is less than 8 lines high, fewer bytes 
in the parameter RAM will be scanned. If the area is 
larger than 8 by 8, the HGDC will repeat the contents of 
the parameter RAM in two dimensions, as required to fill 
the area with the 8-by-8 mosaic. (Fractions of the 8-by-8 
pattern will be used to fill areas which are not multiples of 
8 by 8.) 

Parameter RAM Contents: RAM Address 
RA-Oto RA-1 5 

The parameters stored in the parameter RAM, PRAM, 
are available for the HGDC to refer to repeatedly during 
figure drawing and raster-scanning. In each mode of 
operation the values in the PRAM are interpreted by the 
HGDC in a predetermined fashion. The host micropro- 
cessor must load the appropriate parameters into the 
proper PRAM locations. PRAM loading command allows 
the host to write into any location of the PRAM and trans- 
fer as many bytes as desired. In this way any stored pa- 
rameter byte or bytes may be changed without 
influencing the other bytes. 

The PRAM stores two types of information. For specifying 
the details of the display area partitions, blocks of four 
bytes are used. The four parameters stored in each block 
include the starting address in display memory of each 
display area, and its length. In addition, there are two 
mode bits for each area which specify whether the area 
is a bit-mapped graphics area or a coded-character area, 
and whether a 1 6-bit or a 32-bit wide display cycle is to 
be used for that area. 

The other use for the PRAM contents is to supply the 
pattern for figure drawing when in a bit-mapped graphics 
area or mode. In these situations, PRAM bytes 8 through 
16 are reserved for this patterning information. For line, 
arc, and rectangle drawing (linear figures) locations 8 
and 9 are loaded into the Pattern register to allow the 
HGDC to draw dotted, dashed, etc. lines. For area filling 
and graphics bit-mapped character drawing locations 8 
through 1 5 are referenced for the pattern or character to 
be drawn. 

Details of the bit assignments are shown for the various 
modes of operation. 



Character Mode 



) Display Partition Area 1 
Zm — starting address with low & 
high significance fields 
(word address) 



2 C 





WD1 





LEN1„ 



RA-4 




SAD2, 


5 













SAD2 


6 




LE 


N2, 





7 


WD2 





LEN2. 



Length of Display Partition t 
- (line count) with high and 
low significance fields 

A Wide Display cycle width 
of two words per memory cycle 
_ is selected for this display 
area if this bit is set to a 1 . 
The display address counter 
is then incremented by 
2 for each display scan 
cycle. Other memory cycle 
types are not influenced 

Display Partition 2 
_ starting address 
and length 



RA-8 




SAD3 


9 













SAD3„ 


10 




LE 







11 


WD3 





LEN3„ 



Display Partition 3 
-starting address 
and length 





SAD4 L 









I 







SAD4 M 






LE 


44, 







WD4 





LEN4 H 





Display Partition 4 
- starting address 
and length 



85 



Graphics and Mixed Graphics and Character Modes 



Command Bytes Summary 



P.A-4 
5 



or GCHR7 



Pattern of 16 bits used for 
figure drawing to pattern 
dotted, dashed, etc. lines 



Graphics character bytes 
. to be moved into display 



SAD1 L 



SAD2 L 


SA 


D2„ 






LE 


N2, 





SAD2 1H 


WD2 


IM 


LEN2„ 



character drawing 



Display Partition Area 1 
- starting address with low, 
middle, and high significance 
fields (word address) 



Length ot Display Partition 

- Area 1 with tow and high 
significance fields (line count) 

In mixed mode, a 1 indicates an 
image or graphics area, and a 
indicates a character area. In 
graphics mode this bit must be 0. 
When 1, the DAD is incremented 
every other display cycle. 

Display Partition Area 2 

- starting address and 
length with image 
bit as in area 1 



110 10 11 



1 1 1 



CURS 



1 1 1 



111 



1 1 1 1 



1 


TYPE 





MOD 




10 


10 10 




1 


110 




110 


110 




110 


10 




1 1 


TYPE 





MOD 




1110 







110 







1 1 


TYPE 


1 


MOD 




1 


TYPE 


1 


MOD 



Command Bytes Summary 














1 







10 1 







1 1 
1 1 


DE 







1 


DE 







1 1 1 


DE 




110 


1 1 1 


M 




10 


10 11 
1 1 1 



Video Control Commands 

Reset 



0000 000 



Blank the display, enter 
Idle mode, and initialize 
within the HGDC: 

— FIFO 

— Command Processor 

— Internal Counters 



This command can be executed at any time and does not 
modify any of the parameters already loaded into the 
HGDC. 

If followed by parameter bytes, this command also sets 
the sync generator parameters as described below. Idle 
mode is exited with the START command. 



RESET1 
RESET2 
RESET3 



Resync video timing in slave mode. 
Blank the display and do not resync. 
Unblank the display and do not resync. 




PI 





c 


F 


1 


D 


G 


S 


P2 




AW 


P3 




HS 



V 



- Mode of Operation select bits 



- Active Display Words per 
line - 2 Must be even 
number with bit 



- Horizontal Sync Width - 1 

- Vertical Sync Width, low bits 




DH PH 


HBP 

i ■ i 1 1 


VH VL 


VFP 


AW 




Vertical Sync Width, high bits 



Horizontal From Porch Width - 1 



- Horizontal Back Porch Width — 1 

- Vertical Front Porch Width 



- Active Display Lines per 
Video Field, low bits 



Active Display Lines per 
Video Field, high bits 



Vertical Back Porch Width 



In graphics mode, a word is a group of 1 6 pixels. In char- 
acter mode, a word is one character code and its attrib- 
utes, if any. The number of active words per line must be 
an even number from 2 to 256. An all-zero parameter 
value selects a count equal to 2" where n = number of 
bits in the parameter field for vertical parameters. All 
horizontal widths are counted in display words. All verti- 
cal intervals are counted in lines. 
If the Drawing Hold (DH) is set to one, pin 21 (LPEN/DH) 
is used as the drawing hold control pin. When the input 
to LPEN/DH is held high for over four 2 x WCLK clocks, 
the drawing address output is temporarily held and the 
display address is output. 

The HGDC allows an even or odd number of lines per 
frame. Selection is via the VL flag, the seventh bit of the 
sixth parameter byte following a RESET or SYNC com- 
mand. When VL is 0, an odd number of display lines is 
generated. 



SYNC Generator Period Constraints 

Horizontal Back Porch Constraints 

1. In general: 

HBP > 3 Display Word Cycles (6 clock cycles). 

2. If the Image bit or WD mode changes within one video 
field: 

HBP > 5 Display Word Cycles (10 clock cycles). 

3. If interlaced, mixed mode, or split screen is used: 
HBP > 5 Display Word Cycles (1 clock cycles). 

Horizontal Front Porch Constraints 

1. In general: 

HFP » 2 Display Word Cycles (4 clock cycles). 

2. If the HGDC is used in the video sync Slave mode: 
HFP > 4 Display Word Cycles (8 clock cycles). 

3. If the Light Pen is used: 

HFP 3* 6 Display Word Cycles (1 2 clock cycles). 

4. If interlaced mode, DMA, or ZOOM is used: 
HFP 2* 3 Display Word Cycles (6 clock cycles). 

Horizontal SYNC Constraints 

1 . If Interlaced display mode is used: 

HS > 5 Display Word Cycles (6 clock cycles). 

2. If DRAM Refresh is enabled: 

HS > 2 Display Word Cycles (4 clock cycles). 

Modes of Operation Bits 



c 


■ 


Display Mode 










Mined Graphics S Character 







1 


Graphics Mode 




1 









1 


1 








1 5 Video Framing 












1 Invalid 


1 





Interlaced Repeat Field for Character Displays 




1 1 Interlaced 



Repeat Field Framing: 2 field sequence with V2 line 
offset between otherwise iden- 
tical fields. 

Interlaced Framing: 2 field sequence with V2 line 

offset. Each field displays alter- 
nate lines. 

Non-interlaced Framing: 1 field brings all the information 
to the screen. 



VL Number ol linos In interlaced mode O Dynamic RAM Refresh Cycles Enable 






Odd, as in 7220 





No Re 


fresh — Static RAM 


1 


Even 


1 




h — Dynamic RAM 



When VH = 0, status operation is as in the 7220. 



VH Blank Status Bit Definition 

Status regis ter bit 6 ind icates Horizont al Blan k 

1 Status register bit 6 indicates Vertical Blank 



Dynamic RAM refresh is important when high display 
zoom factors or DMA are used in such a way that not all 
of the rows in the RAMs are regularly accessed during 
display raster generation and for otherwise inactive dis- 
play memory. 



PH is the most significant bit (9) of the display pitch pa- 
rameter. Use the PITCH command to set the lower eight 
bits. 



Drawing during active display time and retrace blanking 



Drawing only during retrace Wanking 



87 



Access to display memory can be limited to retrace blank- 
ing intervals only, so that no disruptions of the image are 
seen on the screen. 



oooo 



1 



RESET3 1 C 1 



Both commands allow a reset while preventing reinitial- 
ization of the internal sync generator by an external sync 
source (slave mode). 

SYNC Format Specify 



1 1 1 



P2 

P3 



V 



. The display is enabled by 
a 1, and blanked by a 0. 



- Mode of Operation select bits 
See below 

- Active Display Words per line. 
Must be even number with 
blto - 0. 



- Horizontal Sync Width 
-vertical Sync Width, low bits 



When using two or more HGDCs to contribute to one 
image, one HGDC is defined as the master sync genera- 
tor, and the others operate as its slaves. The VSYNC pins 
of all HGDCs are connected together. 
Slave Mode Operation 

A few considerations should be observed when synchro- 
nizing two or more HGDCs to generate overlayed video 
via the V/EXT SYNC pin. As mentioned above, the Hori- 
zontal Front Porch (HFP) must be four or more display 
cycles wide. This is equivalent to eight or more clock 
cycles. This gives the slave HGDCs time to initialize their 
internal video sync generators to the proper point in the 
video field to match the incoming vertical sync pulse 
(VSYNC). This resetting of the generator occurs just after 
the end of the incoming VSYNC pulse, during the HFP 
interval. Enough time during HFP is required to allow the 
slave HGDC to complete the operation before the start of 
the HSYNC interval. 

Once the HGDCs are initialized and set up as master 
and slaves, they must be given time to synchronize. It is 
a good idea to watch the VSYNC status bit of the master 
HGDC and wait until after one or more VSYNC pulses 
have been generated before the display process is 
started. The START command will begin the active dis- 
play of data and will end the video synchronization pro- 
cess, so be sure there has been at least one VSYNC 
pulse generated to which the slaves can synchronize. 
Cursor and Character Characteristics 



V 



-Vertical Syne Width, high bits 



tal Front Porch width 



P5 
P6 



DH PH 


HBP 


VH VL 


VFP 


*k 



-Horizontal Back Porch Width 
-Vertical Front Porch Width 



-Active Display Lines per Video 
Field, low bits 



Active Display Lines per Video 
Field, high bits 



-Vertical Back Porch Width 






1 








1 1 
I ■ ■ 
















/ 






DC 


SE 





LR 

i l l i 



-External SYNC Enable 



- Display Cursor If 1 



- Cursor Top line number 

-0 - Blinking Cursor 
1 - Steady Cursor 

- Blink Rate, lower bits 



-Blink Rate, upper bits 



- Cursor Bottom line number In 
the row CBOT < LR 



This command also loads parameters into the sync gen- 
erator. The various parameter fields and bits are identical 
to those at the RESET command. The HGDC is not reset 
nor does it enter idle mode. 



Vertical Sync Mode 



VSYNC: 110 111 M 



-Accept External Vertical 

Sync — Slave Mode 

1 - Generate & Output Vertical 

Sync — Master Mode 



In graphics mode, LR should be set to 0. The blink rate 
parameter controls both the cursor and attribute blink 
rates. The cursor blink-on time = blink-off time = 2xBR 
(video frames). The attribute blink rate is always one-half 
the cursor rate but with a 3 /4-on-'/4-off duty cycle. All 
three parameter bytes must be output for interlaced 
displays, regardless of mode. For interlaced displays in 
graphics mode, the parameter BR L = 3. 

When SE = 0, the HGDC, in slave mode, detects the 
falling edge of EX. SYNC on the first frame. When SE = 
1 , the HGDC, in slave mode, detects the falling edge of 
EX. SYNC on every frame. 



88 



Display Control Commands 

Start Display and End Idle Mode 



START: 110 10 1 1 



The START command generates the video signals as 
specified by the RESETX or SYNC command. 

Display Blanking Control 



IK1: 1 1 DE 



- The display is enabled 
byal. and blanked by 
aO. 



BLANK2: 



1 



BLANK 2 does not cause the resyncing of an HGDC in 
slave mode. BLANK 1 does cause the resyncing of an 
HGDC in slave mode. 

Zoom Factors Specify 



ZOOM: 


1 
1 — 




— I 1 








1 1 

I 1 



















PI 


DISP 


GCHR 
1 1 1 



- Zoom factor (or graphics 
character writing and area 



Zoom magnification factors of 1 through 16 are available 
using codes through 1 5, respectively. 

Cursor Position Specify 



CURS : 1 1 1 



- Execute Word Address, 
low byte 



- Execute Word Address, 
middle byte 



to zero, the pattern written is determined by the least 
significant bit of each parameter byte following the WDAT 
command. This bit is expanded into 16 identical bits 
which form the pattern. 
Parameter RAM Load 



SA 
-t 



- Starting 



- 1 to 16 bytes to be loaded 
into the parameter RAM 
starting at the RAM address 
specified by SA 



From the starting address SA, any number of bytes may 
be loaded into the parameter RAM at incrementing ad- 
dresses, up to location 15. The sequence of parameter 
bytes is determined by the next command byte entered 
into the FIFO. The parameter RAM stores 16 bytes of 
information in predefined locations which differ for graph- 
ics and character modes. See the parameter RAM dis- 
cussion for bit assignments. 

Pitch Specification 



f of word 
lay memory ii 
horizontal direction 



This value is used during drawing by the drawing proces- 
sor to find the word directly above or below the current 
word, and during display to find the start of the next line. 
The Pitch parameter (width of display memory) is set by 
two different commands. In addition to the PITCH com- 
mand, the RESET (or SYNC) command also sets the 
pitch value. The "active-words-per-line" parameter, 
which specifies the width of the raster-scan display, also 
sets the pitch of the display memory. Note that the AW 
value is two less than the display window width. The 
PITCH command must be used to set the proper memory 
width larger than the window width. 



(Graphics Mode only, 



Word Address, top bits 
Dot Address within the word 

In character mode, the third parameter byte is not 
needed. The cursor is displayed for the word time in 
which the display scan address (DAD) equals the cursor 
address. In graphics mode, the cursor word address 
specifies the word containing the starting pixel of the 
drawing; the dot address value specifies the pixel within 
that word. 

When the WG bit is set to one, any data following the 
WDAT command is written as is. When the WG bit is set 




89 



Drawing Control Commands 

Write Data into Display Memory 



WDAT: 








1 


TYPE 





MOD 






I 











- RMW Memory cycle 
Logical Operation: 

- REPLACE with Pattern 

- COMPLEMENT 

- RESET to zero 
-SET lot 



- Data Transfer Type: 

- Word, Low then High byte 



- Low Byte of the Word 
-High Byte of the Word 



WORD OR BYTE 



- Word Low Data Byte or 
Single Byte Data value 



- Word transfer only: 
High Data Byte 



Upon receiving a set of parameters (two bytes for a word 
transfer, one for a byte transfer), one RMW cycle into 
video memory is done at the address pointed to by the 
cursor EAD. The EAD pointer is advanced to the next 
word, according to the previously specified direction. 
More parameters can then be accepted. 
For byte writes, the unspecified byte is treated as all 
zeros during the RMW memory cycle. 

In graphics bit-map situations, only the LSB of the WDAT 
parameter bytes is used as the pattern in the RMW oper- 
ations. Therefore it is possible to have only an all ones or 
all zeros pattern. If the WG bit of the third parameter of 
the CURS command is set to one, any byte following the 
WDAT command is written as is. In coded character appli- 
cations all the bits of the WDAT parameters are used to 
establish the drawing pattern. 

The WDAT command operates differently from the other 
commands which initiate RMW cycle activity. It requires 
parameters to set up the Pattern register while the other 
commands use the stored values in the parameter RAM. 
Like all of these commands, the WDAT command must 
be preceded by a FIGS command and its parameters. 
Only the first three parameters need be given following 
the FIGS opcode to set up the type of drawing, the DIR 
direction, and the DC value. The DC parameter + 1 will 
be the number of RMW cycles done by the HGDC with 
the first set of WDAT parameters. Additional sets of WDAT 
parameters will see a DC value of which will cause only 
one RMW cycle to be executed per set of parameters. 

Mask Register Load 



This command sets the value of the 1 6-bit Mask register 
of the figure drawing processor. The Mask register con- 
trols which bits can be modified in the display memory 
during a read-modify-write cycle. 
The Mask register is loaded both by the MASK command 
and the third parameter byte of the CURS command. 
The MASK command accepts two parameter bytes to 
load a 16-bit value into the Mask register. All 16 bits can 
be individually one or zero, under program control. The 
CURS command, on the other hand, puts a 1 -of-1 6 pat- 
tern into the Mask register based on the value of the Dot 
Address value, dAD. If normal single-pixel-at-a-time 
graphics figure drawing is desired, there is no need to do 
a MASK command at all since the CURS command will 
set up the proper pattern to address the proper pixels as 
drawing progresses. For coded character DMA, and 
screen setting and clearing operations using the WDAT 
command, the MASK command should be used after the 
CURS command if its third parameter byte has been 
output. The Mask register should be set to all ones for 
any "word-at-a-time" operation. 

Figure Drawing Parameters Specify 



10 110 

— 1 1 1 1 1 1 i 



- Drawing Direction Base 



Figure Type Select Bits: 
Line (Vector) 



- Graphics Character 



- Rectangle 

- Slanted Graphics Character 











MASK: 


1 10 10 


P9 





D1m 



n 



High significance byte 



P3 





GD 


DC. 






s 














"( 


D, 












PS 





• 


D. 












"C 


D2, 










P7 








D2„ 

! 1 i 1 1 



D1, 



DM. 



DM. 



DC Drawing Parameter 



> 



_ Graphics Drawing flag for use in 
Mixed Graphics and Character Mode 



9 



- D Drawing Parameter 



-02 Drawing Parameter 



- D1 Drawing Parameter 



- DM Drawing Parameter 



The parameters lake on 
different interpretations for 
different figure types. 



90 



Valid Figure Type Select Combinations 



Cursor Address Read 



SL 


R 


A 


QC 


L 


Operation 
















Character Display Mode Drawing, Individual Dot Drawing, DMA, 
WDAT, and RDAT 














1 


Straight Line Drawing 











1 





Graphics Character Drawing and Area Filling with Graphics Char- 
acter Pattern 








1 








Arc and Circle Drawing 





1 











Rectangle Drawing 


1 








1 





Slanted Graphics Character Drawing and Slanted 
Area Filling 



Only these bit combinations assure correct drawing 
operation. 

Figure Draw Start 



On execution of this instruction, the HGDC loads the 
parameters from the parameter RAM into the drawing 
processor and starts the drawing process at the pixel 
pointed to by the cursor, EAD, and the dot address, dAD. 

Graphics Character Draw and Area Filling Start 



Based on parameters loaded with the FIGS command, 
this command initiates the drawing of the graphics char- 
acter or area filling pattern stored in parameter RAM. 
Drawing begins at the address in display memory pointed 
to by the EAD and dAD values. 

Data Read Commands 

Read Data from Display Memory 



1 1 


TYPE 





MOD 






J? 












Data 



Data Transfer Type: 
-Word, low then high byte 



-Low byte of the Word only 
- High byte of the Word only 



Using the DIR and DC parameters of the FIGS command 
to establish direction and transfer count, multiple RMW 
cycles can be executed without specification of the cursor 
address after the initial load (DC = number of words or 
bytes). 

As this instruction begins to execute, the FIFO buffer 
direction is reversed so that the data read from display 
memory can pass to the microprocessor. Any commands 
or parameters in the FIFO at this time will be lost. A com- 
mand byte sent to the HGDC will immediately reverse the 
buffer direction back to write mode, and all RDAT infor- 
mation not yet read from the FIFO will be lost. MOD 
should be set to 00 if no modification to video buffer is 
desired. 



CURD: 1 1 1 



The following bytes are returned by the HGDC through 
the FIFO: 



A7 


EAD 


AO 















3 


EAD,. 



- Execute Address (EAD), 
low byte 



Execute Address (EAD), 
middle byte 



Execute Address (EAD), 
high bits 



- Dot Address (dAD], low byte 



- Dot Address (dAD), high byte 



The execute address, EAD, points to the display memory 
word containing the pixel to be addressed. 

The dot address, dAD, within the word is represented as 
a 1-of-1 6 code for graphics drawing operations. 

Light Pen Address Read 



LPRD: 1 1 



The following bytes are returned by the HGDC through 
the FIFO: 



A7 




LAD, 




AO 




A15 




LAD. 




A8 
















LAD. 



AO -> Light Pen Address, low byte 



-Light Pen Address, 
middle byte 



- Light Pen Address, high byte 



The light pen address, LAD, corresponds to the display 
word address, DAD, at which the light pen input signal is 
detected and deglitched. 

The light pen may be used in graphics, character, or 
mixed modes but only indicates the word address of light 
pen position. 



91 



DMA Control Commands 

DMA Read Request 



DMA Write Request 



1 1 


TYPE 


1 


MOD 



DMAW : 



1 


TYPE 


1 


MOD 



- Data Transfer Type: 



- Word, Low then High Byte 

- Low Byte ot the Word 



- High Byte ot the Word 



tRMW Memory Logical Operation: 

REPLACE with Pattern 

COMPLEMENT 

RESET to Zero 

SET to One 

- Data Transfer Type: 



Word, Low then High Byte 

- Low Byte ot the Word 

- High Byte ot the Word 

- Invalid 



AC Characteristics 

T A = to +70°C; V cc = 5.0 V ±10%; GND = V 







6 MHz 


Limits 


8 MHz Limits 






Parameter 


Symbol 


Mill 


Max 


Mill 


Max 


Unit 


Test Conditions 


Read Cycle [6DC * — * 


CPU) 














Address setup to 
11 


tAR 












ns 




Address hold from 

HU 1 


Ira 












ns 




RD pulse width 


<RH1 


'rdi + 20 


tRCY- 1/2 tCLK 


1RD1+20 


tRCY -1/2 'CLK 


ns 




Data delay from 
ROl 


<RD1 




75 




55 


ns 


C L = 50 pF 


Data floating from 

KU I 


tDF 





75 





55 


ns 




SB pulse cycle 


tRCY 


4'CLK 




41CLK 




ns 




Write Cycle (GDC - — ■ 


CPU] 














Address setup to 

m 


Uw 












ns 




Address hold from 
WRt 


tWA 


10 




10 




ns 




WR pulse width 


'WW 


80 


IWCY - tCLK 


60 


twCY - tCLK 


ns 




Data setup to WRt 


<ow 


65 




45 




ns 




Data hold from WRt 


>WD 







10 




ns 




WR pulse cycle 


>WCY 


4 tfJLK 




4 tCLK 




ns 




DMA Read Cycle (GDC - 


1 — * CPU) 














Back setup to 
RBI 


tKR 












ns 




DACK hold from RDt 


Irk 












ns 




RD pulse width 


tRR2 


IRD2 + 20 




tR02 + 20 




ns 




Data delay from RBI 


tRD2 




1-5 t C LK + 80 




1.5 t CLK + 60 


ns 


C L = 50 pF 


DREQ delay from 
2xWCLKt 


Ireq 




100 




75 


ns 


C L = 50 pF 


DREQ setup to 

BaBkI 


tQK 












ns 




BACK high-level 
width 


'OK 


tCLK 




tCLK 




ns 




BACK pulse cycle 


tE 


4t C LK<1) 




4t C LK(1) 




ns 




DREQl delay from 
DACKi 


( KQ(R) 




tCLK + 100 




tGLK + 80 


ns 


C L = 50 pF 


DACK low-level 
width 


tLK 


2t C LK 




2tCLK 









92 



AC Characteristics (cont) 

T A = to +70°C; V cc = 5.0 V ±10%; GND = V 







6 MHz 


Limits 


8 MHz 


Limits 






Parameter 


Symbol 


Mln 


Max 


Mln 


Max 


Unit 


Test Conditions 


DMA Write Cycle (GDC 


' — ' CPU) 














DACK setup to 

am j 


<KW 












ns 




BACK hold fromWRt 


twK 












ns 




RMVY Cycle (GDC - — > 


Display Mi 


imory) 












Address/dats 
display from 
2xWCLKt 


tan 


20 


105 


15 


80 


ns 


C L = 50 pF 


Address/data 
floating from 
2xWCLKt 


'OFF 


20 


105 


15 


80 


ns 


C L = 50pF 


Input data setup to 
2xWCLKl 


'dis 












ns 




Input data hold from 
2xWCLKi 


t0IH 


IDE 




IDE 




ns 




DBIN delay from 
2xWCLKl 


tOE 


20 


80 


15 


60 


ns 


C L = 50 pF 


ALEt delay from 
?xwn Kt 


tRR 


20 


80 


15 


60 


ns 


C L = 50 pF 


ALE 1 delay from 
2xWCLKt 


tRF 


20 


65 


15 


50 


ns 


C L = 50 pF 


ALE high width 


Irw 


1/3t C LK 




1/3 tcLK 




ns 


C L = 50 pF 


ALE low width 


tRL 


15 tc L K-30 




1.5t CLK -30 




ns 




Address setup to 
ALEl 


Ua 


30 




30 








Display Cycle (GDC " — * Display Memory) 


Video signal display 
from 2xWCLKl 


typ 




90 




70 


ns 


C L = 50pF 


Input Cycle (GDC - — ► 


Display Memory) 












Input signal setup to 
2xWCLKt 


tps 


10 




10 




ns 




Input signal width 


>PW 


>CLK 




'CLK 




ns 




Clock (2xWCLK| 


Clock rise time 


( CR 




15 




15 


ns 




Clock fall time 


tCF 




15 




15 


ns 




Clock high pulse 
width 


»CH 


70 




52 




ns 




Clock low pulse 
width 


tCL 


70 




52 




ns 




Clock cycle 


'CLK 


165 


10000 


125 


10000 


ns 





Note: 



(1) For high-byte and low-byte transfers: t E = 5 t CLK . 



Capacitance 

T A = 25°C i V cc = GND = 0V 



Input Capacitance 
I/O Capacitance 



Output Capacitance 
Clock Input Capacitance 



c our 
C* 



20 
20 



pF 

pF tc = 1 

~ V, 

: 0V 



PF 
pF 



DC Characteristics 

T» = 0°C to + 70°C; V cc = 5V ± 10%; GND = OV 







Limits 






Parameter 


Symbol 


Min Typ Max 


Unit 


Conditions 


Input Low Voltage 


V,L 


-0.5 0.8 


V 


© 


Input High Voltage 


V|H 


2.2 V x + 0.5 


V 


© © 


Output Low Voltage 


Vol 


0.45 






Output High Voltage 


Vo» 


2.4 


V 


lo„=-400pA 


Input Low Leak Current 
(except VSVNC, DACK) 


Ik. 


-10 


nA 


v, = ov 


Input Low Leak Current 
(VSYNC. DACK) 




-500 


P* 


Input High Leak Current 
(except LPEN/DH) 


III. 


+ 10 


hA 


V. = V 

I *cc 


Input High Leak Current 
(LPEN/DH) 


■iM 


+ 500 




Output Low Leak 
Current 


l0L 


-10 




V o = 0V 


Output High Leak 
Current 


■w 


+ 10 


"A 


V = V cc 


Clock Input Low Voltage 


»CL 


-OS (16 


V 




Clock Input High Voltage 


Vo, 


3.5 Vcc + '•<> 


V 




Vcc Supply Current 


Ice 


270 


mA 




Note*: CD For2xWCLK,V, L - -0.5V to *0.6V 

© For2xWCLK.V IH = + 3.9VtoV cc + 1.0V. 
CD FotWR.Vih = 2.5V10VCC +0.5V. 






Absolute Maximum Ratings* (Tentative) 




Ambient Temperature under Bias 




ere: to +7ox 


Storage Temperature 






65°Cto +150°C 


Voltage on Any Pin v. 


ith Resc 


ect to Ground 




-0.5V to +7V 


Power Dissipation 








1.5 w 



Comment: Exposing the device to stresses above those listed in 
Absolute Maximum Ratings could cause permanent damage. The 
device is not meant to be operated under conditions outside the 
limits described in the operational sections of this specification. 
Exposure to absolute maximum rating conditions for extended 
periods may affect device reliability. 



AC Testing Conditions 

Input Waveform for AC Test (Except 2xCCLK) 



Timing Waveforms 

Microprocessor Interface Write riming 



AO: Invalid ) ■ Valid ; < Invalid X Valid 



DBO -7: Invalid I % 



1- 



Timing 



AO: Invalid > Valid < Invalid Y 


RD: — M 


*-t»H-» 




7 High 












> \ f High Impedance 





Microprocessor Interlace DMA Write Timing 




l„„ (WR | to HSVNC t ) » tcu, 
t,„ (DACK 1 to HSYNC f ) » tc L , 

Timing 



2.4 






0.45 


)C Test Points 






Output Waveform for AC Test 



Clock Timing (2xCCLK) 



-^^3.5 3.5^^- 



94 



Timing Waveforms (Cont.) 

Display Memory Display Cycle Timing Display Memory RMW Timing 




LCO 3 
CSR 

CSR-IMAGE 
ATT-BLINK-CLC 




95 



Timing Waveforms (Cont.) 




96 



Timing Waveforms (Cont.) 




Timing Waveforms (Cont.) 

Light Pen and External Sync Input Timing 



Clock Timing (2xWCLK) 




f Video Timing 



»«*<: ji n_n n_n n_n n n ri_n____jL_n_- 

i j i i i i i 



VSYNC: 
(tnterlace) - 



VS"NC: 
(No lnterlace>- 



I I 



Timing Waveforms (Cont.) 

Video Horizontal Syne Generator Parameters 



-rl 



i i 
i i 



Video Vertical Sync Generator Parameters 



H 



Cursor — Image Bit Flag 



_»| j«— tci-K 

JUUUl 



rii <>- 

t-H 0- 



-it-\ 



99 



Block Diagram of a Graphics Terminal 



Graphics 

Input 
Devices 







Z7220A 
HGDC 



Display 
Memory 



±2. 



Character 
Generator 
ROM 







Lighl Pen 
Circuit 



CRT 
Display 



Multiplane Display Memory Diagram 

731 



AD A 
0IO15 ! 



V 



COL 
MUX 
ftOWj 



RAMs DO 
ADR 



-, Sh.ll , 
V— Registers 



3^ 



RAMs 00 
ADR 



> 



> 



1£ 



RAMs DO 
ADR 



3_k 



ADR 



Cha, 
Gen 



Attri 
Logic 



V.deo 




Amp 





Zilog 



Product Specification 



Z765A FDC 

Floppy Disk Controller 



October 1988 



FEATURES 

Address Mark detection circuitry internal to the FDC 
simplifies the phase locked loop and read electronics. The 
track stepping rate, head load time, and head unload time 
are user-programmable. 

Z765A features are: 

■ IBM-compatible format, Single and Double Density 

■ Multisector and multitrack transfer capability 

■ Data scan capability— scans a single sector or an entire 
cylinder comparing byte-for-byte host memory and disk 
data 



Drives up to 4 floppy-disk drives (FDD) 
Data transfers in DMA or non-DMA mode 
Parallel seek operations on up to four drives 
Compatible with most general-purpose microprocessors 
Single phase 8 MHz clock 
+ 5V Only 

40-Pin Dual-ln-Line (DIP) package, 44-Pin plastic 
chip carrier (PLCC) package. 



GENERAL DESCRIPTION 

The Z765A is an LSI Floppy Disk Controller (FDC) chip 
which contains the circuitry and control functions for 
interfacing a processor to four floppy-disk drives. It supports 
IBM System 3740 Single Density format (FM) and IBM 
System 34 Double Density format (MFM) including 
double-sided recording. The Z765A provides control 
signals which simplify the design of an external phase 
locked loop and write precompensation circuitry. The FDC 
simplifies and handles most of the burdens associated with 
implementing a floppy-disk interface. (Figure 1 ). 

Handshaking signals make DMA operation easily 
incorporated with the aid of an external DMA Controller 
chip, such as the Z80 DMA. The FDC operates in either the 
DMA or non-DMA mode. In the non-DMA mode the FDC 
generates interrupts to the processor every time a data byte 
is to be transferred. In the DMA mode, the processor need 
only load the command into the FDC and all data transfers 
occur under control of the FDC and DMA controllers. 

The Z765A executes 15 commands; each command 
requires multiple 8-bit bytes to fully specify the operation 
which the processor wishes the FDC to perform. The 
commands are: 



READ DATA 

WRITE DATA 

WRITE DELETED DATA 

READ DELETED DATA 

READ TRACK 

READ ID 

FORMAT TRACK 

SCAN EQUAL 

SCAN HIGH OR EQUAL 

SCAN LOW OR EQUAL 

SEEK 

RECALIBRATE 

SENSE INTERRUPT STATUS 

SPECIFY 

SENSE DRIVE STATUS 



101 



DATA 
BUS 
BUFFER 



TERMINAL 
COURT ' 



DRQ 
DACK 
INT 
RD — • 

WR 

0/S 



READ 
WRITE 
DMA 
CONTROL 
LOGIC 



cs ■ 

CLK ■ 
*5V • 
GND ■ 



SERIAL 
INTERFACE 
CONTROLLER 



WR CLOCK 
WR DATA 
WR ENABLE 
PRESHIFT 
PRESHIFT 1 
RD DATA 

READ DATA WINDOW 
VCO/SYNC 



DRIVE 
INTERFACE 
CONTROLLER 



INPUT 
PORT 



OUTPUT 
PORT 



. READY 

• WRITE PROTECT/TWO SIDE 

• INDEX 

■ FAULT /TRACK 

UNIT SELECT 
UNIT SELECT 1 

■ MFMMODE 

■ RW/SEEK 
HEAD LOAD 
HEAD SELECT 

■ LOW CURRENT DIRECTION 
FAULT RESET/STEP 



Figure 1 . Z765A FDC Block Diagram 



SYSTEM 
DATA , 
BUS 



BUS 
CONTROL 



SYSTEM 
BUS 
CONTROL 





WCK 


D 7 


WDA 


Ds 


WE 


Ds 


PSi 


D 4 


PS 


D 3 


RDD 


D 2 


RDW 


D, 


VCO/SYNC 


Do 






RDY 


DACK 


Z765A WP/TS 


DRQ 


IDX 


TC 


FLT/TRo 


D/S 


USo 


RD 


US, 


WR 


MFM 


CS 


RW/SEEK 


INT 


HDL 


RESET 


HD 




LCT/DIR 




FR/STP 


t 

CLK 


I I 

GND +5V 


Figure 2. Pin Functions 



SERIAL 

INTERFACE 

CONTROL 



DRIVE 

INTERFACE 

INPUTS 



DRIVE 

INTERFACE 

OUTPUTS 

















RESET 


c 




10 


J 


+ 5V 


RD 


c 






39 


J 


RW/SEEK 


WR 


c 


3 




38 




LCT/DIR 


CS 


L 






37 


J 


FR/STP 


D/S 


C 






36 


J 


HDL 


Do 


L 


6 




35 


J 


RDY 


D, 


L 






34 




WP/TS 


D 2 


C 


» 




33 




FLT/TRo 


D 3 


c 


9 




32 




PSo 


D, 


L 


10 


Z765A 


31 




PS, 


Ds 


c 


« 




30 


] 


WDA 


D 6 


c 


12 




29 


] 


USo 


Or 


L 


13 




28 


1 


US, 


DRO 


L 


1* 




27 


3 


HD 


Back 


L 


15 




26 




MFM 


TC 


C 


16 




25 


3 


WE 


IDX 


c 


17 




24 


J 


VCO/SYNC 


INT 


L 


18 




23 


1 


RDD 


CLK 


E 


19 




22 


2 


RDW 


GND 


L 


20 




2. 


1 


WCK 



Figure 3a. Pin Assignments 



102 



2357-001.002.003 



UJ AC m 

- s 16 

Qlo Isloc it + +ICC J it I 

n n n n n n nnn n n 

6 5 4 3 2 1 44 4342 41 40 



D„ C7 
D, O 

Da C 10 
D, C 11 
D 5 C 12 
D* C 13 
D 7 C14 
DRO C 15 
DSCK C 16 
TC C 17 



Z765A 



39 □RDY 
38 □WP/TS 
37 □FLT/TR 
36 □PS,, 
35 □PS, 
34 ^WOA 
33 □ US 
32 □US, 
31 □HD 

30 □mfm 

29 □WE 



18 19 20 21 22 23 24 2526 27 28 

uuuuuuuuuuu 



x fc * o o o o * 

9 ? rl " 



7 z z z 

z (5 (5 (3 



o o 

1 



Figure 3b. Pin Assignments 



PIN DESCRIPTIONS (Figures 2 and 3) 



CLK. Clock (input). Single phase 8MHz square wave clock. 

CS. Chi p Se lect (input). IC selected when (Low), allowing 
RD and WR to be enabled. 

D -D 7 . Dafa Bus. Bidirectional 8-bit Data Bus. Disabled 
when CS = 1 . 

DACK. DMA Acknowledge (input). DMA cycle is active 
when 0, and controller is performing DMA transfer. 

DRQ. Dafa DMA Request (output). DMA Request is being 
made by FDC when DRQ = 1 . 

D/S. Data/Status Register Select (input). Selects Data 
Register (D/S = 1) or Status Register (D/S = 0) contents of 
the FDC to be sent to Data Bus. Disabled when CS = 1 . 

FR/STP. Fault Reset/Step (output). Resets fault FF in FDD in 
Read/Write mode, contains step pulses to move head to 
another cylinder in Seek mode. 

FLT/TRq. Fault/Track (input). Senses FDD fault condition 
in Read/Write mode and Track condition in Seek mode. 

HD. Head Select (output). Head 1 selected when 1 (High); 
Head selected when (Low). 

HDL. Head Load (output). Command which causes 
read/write head in FDD to contact diskette. 

IDX. Index (input). Indicates the beginning of a disk track. 

INT. Interrupt (output). Interrupt Request generated by 
FDC. 

LCT/DIR. Low Current/Direction (output). Lowers Write 
current on inner tracks in Read/Write mode; determines 
direction head will step in Seek mode. A fault reset pulse is 
issued at the beginning of each Read or Write command 
prior to the occurrence of the Head Load signal. 

MFM. MFM Mode (output). MFM mode when 1 ; FM mode 
when 0. 

PS-i, PSo. Precompensation (preshift) (output). Write 
precompensation status during MFM mode. Determines 
early, late, and normal times. 



RD. Read (input). When 0, control signal for transfer of data 
from FDC to Data Bus. Disabled when CS = 1 . 

RDD. Read Data (input). Read data from FDD, containing 
clock and data bits. 

RDW. Read Data Window (input). Generated by PLL, and 
used to sample data from FDD. 

RDY. Ready (input). Indicates FDD is ready to send or 
receive data. 

RESET. Reset (input). Places FDC in idle state. Resets 
output lines to FDD to 0. Does not affect SRT, HUT or HLT in 
Specify command. If RDY pin is held High during Reset, 
FDC generates an interrupt within 1 .024 msec. To clear this 
interrupt use Sense Interrupt Status command. 

RW/SEEK. Read Write/Seek (output). When 1 (High) Seek 
mode selected; when (Low) Read/Write mode selected. 

TC. Terminal Count (input). Indicates the termination of a 
DMA transfer when 1 (High). It terminates data transfer 
during Read/Write/Scan command in DMA or Interrupt 
mode. 

US-i, US . Unit Select (output). FDD Unit selected. 

VCO/SYNC. (output). Inhibits VCO in PLL when (Low); 
enables VCO when 1 . 

WCK. Write Clock (input). Write data rate to FDD. FM = 500 
KHz, MFM = 1 MHz with a pulse width of 250 ns for both 
FM and MFM. 

WDA. Write Data (output). Serial clock and data bits to FDD. 

WE. Write Enable (output). Enables write data into FDD. 

WP/TS. Write Protect/Two Side (input). Senses Write Protect 
status in Read/Write mode and Two-Side Media in Seek 
mode. 

WR. Write (input). When 0, control signal for transfer of data 
to FDC via Data Bus. Disabled when CS = 1 . 



104 



Table 1 . Internal Registers 



The bits in the Main Status Register are defined as follows: 



Bit 

No. Name Symbol Description 

Dq FDD Busy DqB FDD number is in the Seek mode. If any bit is set, FDC will not accept read 

or write command. 



Di FDD 1 Busy D-|B FDD number 1 is in the Seek mode. If any bit is set, FDC will not accept read 

or write command. 



D 2 


FDD 2 Busy 


D 2 B 


FDD number 2 is in the Seek mode. If any bit is set, FDC will not accept read 
or write command. 


D 3 


FDD 3 Busy 


D 3 B 


FDD number 3 is in the Seek mode. If any bit is set, FDC will not accept read 
or write command. 


D 4 


FDC Busy 


CB 


A read or write command is in process. FDC will not accept any other 
command. 


D 5 


Execution Mode 


EXM 


This bit is set only during execution phase in non-DMA mode. When D5 
goes low, execution phase has ended and result phase has started. It 
operates only during non-DMA mode of operation. 


D 6 


Data Input/Output 


DIO 


Indicates direction of data transfer between FDC and Data Register. If DIO « 
1 , then transfer is from Data Register to the processor. If DIO = 0, transfer is 
from the processor to Data Register. 


D 7 


Request for Master 


ROM 


Indicates Data Register is ready to send or receive data to or from the 
processor. Both bits DIO and ROM should be used to perform the 
handshaking functions of "ready" and "direction" to the processor. 



INTERNAL REGISTERS 

The Z765A contains two registers which may be accessed 
by the main system processor: a Status register and a Data 
register. The 8-bit Main Status register (Table 1) contains the 
FDC status information and may be accessed at any time. 
The 8-bit Data register is several registers in a stack; one 
register at a time is presented to the data bus. The Data 
register stores data, commands, parameters, and FDD 
status information. Data bytes are read out of, or written into, 
the Data register in order to program or obtain the results 
after a particular command. Only the Status register may be 
read and used to facilitate the transfer of data between the 
processor and Z765A. 

The relationship between the Status/Data registers and the 
signals RD, WR, and D/S is shown in Table 2. 

The Data Input/Output (DIO) and Request for Master (ROM) 
bits in the Status register indicate when data is ready and the 
direction transfer on the data bus (Figure 4). The maximum 
time between the last RD or WR during a command or result 



phase and the set or reset DIO and ROM is 1 2/iS; every time 
the Main Status register is read the CPU should wait 12^s. 
The maximum time from the trailing edge of the last RD in 
the result phase to when D 4 (FDC busy) goes Low is 1 2^is. 



Table 2. Relationships Between Status/Data Registers 
and RD, WR, and D/S 



D/S 


RD 


WR 


Function 








1 


Read Main Status Register 





1 





Illegal 











Illegal 


1 








Illegal 


1 


_ 


1 


Read from Data Register 


1 


1 





Write into Data Register 



105 



STATUS REGISTER IDENTIFICATION 



Bit 



No. 


Name 


Symbol 


Description 


Status Register 








D 7 = and Dg = 

Normal Termination of command, (NT). Command was completed and 
properly executed. 


D7 


Interrupt Code 


IC 


D7 = and D6 = 1 

Abnormal Termination of command, (AT). Execution of command was started 
but was not successfully completed. 


D 6 






D 7 = 1 and D 6 = 

Invalid Command issue, (IC). Command which was issued was never started. 
D7 = 1 and Dg = 1 

Abnormal Termination because during command execution the ready signal 
from FDD changed state. 


D 5 


Seek End 


SE 


When the FDC completes the SEEK command, this flag is set to 1 (High). 


D 4 


Equipment Check 


EC 


If a fault signal is received from the FDD, or if the Track signal fails to occur 
after 77 step pulses (Recalibrate Command) then this flag is set. 


D 3 


Not Ready 


NR 


When the FDD is in the not-ready state and a read or write command is issued, 
this flag is set. If a read or write command is issued to Side 1 of a single-sided 
drive, then this flag is set. 


D 2 


Head Address 


HD 


This flag is used to indicate the state of the head at Interrupt. 


D1 


Unit Select 1 


USi 


This flag is used to indicate a Drive Unit Number at Interrupt. 


Do 


Unit Select 


us 


This flag is used to indicate a Drive Unit Number at Interrupt. 


Status Register 1 


D 7 


End of Cylinder 


EN 


When the FDC tries to access a sector beyond the final sector of a cylinder, 
this flag is set. 


D 6 






Not used. This bit is always (Low). 


D 5 


Data Error 


DE 


When the FDC detects a Cyclic Redundancy Check (CRC) error in either the 
ID field or the data field, this flag is set. 


D 4 


Overrun 


OR 


If the FDC is not serviced by the host system during data transfers within a 
certain time interval, this flag is set. 


D 3 






Not used. This bit always (Low). 








During execution of READ DATA, WRITE DELETED DATA or SCAN command, 
if the FDC cannot find the sector specified in the Internal Data Register (IDR), 
this flag is set. 


D 2 


No Data 


ND 


During execution of the READ ID command, if the FDC cannot read the ID 
field without an error, then this flag is set. 

During execution of the READ A cylinder command, if the starting sector 
cannot be found, then this flag is set. 



106 



STATUS REGISTER IDENTIFICATION (Continued) 



Bit 


No. 


Name 


Symbol 


Description 


Status Register 1 (Continued) 


□1 


Not Writeable 


NW 


During execution of WRITE DATA, WRITE DELETED DATA or Format A 
cylinder command, if the FDC detects a write protect signal from the FDD, 
then this flag is set. 








If the FDC cannot detect the ID Address Mark after encountering the index 
hole twice, then this flag is set. 


Do 


Missing Address Mark 


MA 


If the FDC cannot detect the Data Address Mark or Deleted Data Address 
Mark, this flag is set. Also at the same time, the MD (Missing Address Mark in 
data field) of Status register 2 is set. 


Status Register 2 


D 7 






Not used. This bit is always (Low). 


D 6 


Control Mark 


CM 


During execution of the READ DATA or SCAN command, if the FDC 
encounters a sector which contains a Deleted Data Address Mark, this flag is 
set. 


D 5 


Data Error in Data Field 


DD 


If the FDC detects a CRC error in the data field then this flag is set. 


D 4 


Wrong Cylinder 


WC 


This bit is related to the ND bit, and when the contents of Cylinder (C) on the 
medium is different from that stored in IDR, this flag is set. 


D 3 


Scan Equal Hit 


SH 


During execution of the SCAN command, if the condition of "equal" is 
satisfied, this flag is set. 


D 2 


Scan Not Satisfied 


SN 


During execution of the SCAN command, if the FDC cannot find a sector on 
the cylinder which meets the condition, then this flag is set. 


Pi 


Bad Cylinder 


BC 


This bit is related to the ND bit, and when the contents of C on the medium is 
different from that stored in the IDR and the contents of C is FFh, then this flag 
is set. 


Do 


Missing Address Mark in 
Data Field 


MD 


When data is read from the medium, if the FDC cannot find a Data Address 
Mark or Deleted Data Address Mark, then this flag is set. 


Status Register 3 


D 7 


Fault 


FT 


This bit is used to indicate the status of the Fault signal from the FDD. 


D 6 


Write Protected 


WP 


This bit is used to indicate the status of the Write Protected signal from the 
FDD. 


D 5 


Ready 


RY 


This bit is used to indicate the status of the Ready signal from the FDD. 


D 4 


Track 


TO 


This bit is used to indicate the status of the Track signal from the FDD. 


D 3 


Two Side 


TS 


This bit is used to indicate the status of the Two Side signal from the FDD. 


D 2 


Head Address 


HD 


This bit is used to indicate the status of the Side Select signal to the FDD. 


Di 


Unit Select 1 


USi 


This bit is used to indicate the status of the Unt Select 1 signal to the FDD. 


Do 


Unit Select 


us 


This bit is used to indicate the status of the Unit Select signal to the FDD. 



107 



OUT FDC AND INTO PROCESSOR 



DATA IN/OUT 

(DIO) OUT PROCESSOR AND INTO FOC 



REQUEST FOR MASTER 
(ROM) 

WR 
RD 




A B ABACDCOBA 



NOTES: [A] — Data register ready to be written into by processor 

\B\ — Data register not ready to be written into by processor 

Icl — Data register ready for next data byte to be read by processor 

[D] — Data register not ready to be read by processor 



Figure 4. Data Transfer 



COMMAND SEQUENCE 

The Z765A is capable of performing 15 different 
commands. Each command is initiated by a multibyte 
transfer from the processor; the result after execution of the 
command may also be a multibyte transfer back to the 
processor. Because of this multibyte interchange of 
information between the Z765A and the processor, each 
command consists of three phases: 

Command Phase. The FDC receives all information 
required to perform a particular operation form the 
processor. 

Execution Phase. The FDC performs the operation it was 
instructed to do. 



Result Phase. After completion of the operation, status and 
other housekeeping information are made available to the 
processor. 

The Instruction set shows the required preset parameters 
and results for each command. Most commands require 9 
command bytes and return 7 bytes during the result phase. 
The W to the left of each byte indicates a command phase 
byte to be written; an R indicates a result byte. 



PROCESSOR INTERFACE 



During Command or Result phases the Main Status register 
must be read by the processor before each byte of 
information is written into, or read from, the Data register. 
Then the CPU should wait for 1 2jjs before reading the Main 
Status register. Bits D6 and D 7 in the Main Status register 
must be in a and 1 state, respectively, before each byte of 
the command word may be written into the Z765A. Many of 
the commands require multiple bytes and, as a result, the 
Main Status register must be read prior to each byte transfer 
to the Z765A. During the Result phase, D 6 and D 7 in the 
Main Status register must both be 1's before reading each 
byte from the Data Register. Reading the Main Status 
register before each byte transfer to the Z765A is required 
only in the Command and Result phases, not during the 
Execution phase. 



If theZ765A is in the non-DMA mode and reading data from 
FDD, then the receipt of each data byte is indicated by an 
interrupt signal on pin 1 8(INT = 1 ). The generation of a Read 
signal (RD = 0) or Write signal (WR = 0) will clear the 
interrupt and output the data onto the data bus. If the 
processor cannot handle interrupts fast enough (every 1 3^s 
for the MFM mode and 27jiS for the FM mode), then it may 
poll the Main Status register and bit D7 (RQM) functions as 
the_ interrupt signal. If a Write command is in process, the 
WR signal negates the reset to the interrupt signal. 

In the non-DMA mode it is necessary to examine the Main 
Status register to determine the cause of the interrupt, since 
it could be a data interrupt or a command termination 
interrupt, either normal or abnormal. If the Z765A is in the 



108 



COMMAND SYMBOL DESCRIPTION 



Symbol 


Name 


Description 


D/S 


Data/Status Select 


D/S controls selection of Main Status register (D/S = 0) or Data register (D/S = 1) 


Q 


^yiniuci iNUii iuci 


O QtanrHQ for thp n irrpnt/<5p|prtpH rvlinrfpr rtrapk^ ni imhprc fl thrm mh 7fi nf thp mpHii im 
u dial IU3 iui uicouiioiiu acici^icu v^yin iuci \u a\jry) luuiucia u u iiuuyi I u u iiicii icutui 1 1 . 


D 


Data 


D stands for the data pattern which is going to be written into a sector. 


D 7 -D 


Data Bus 


8-bit Data Bus, where D7 stands for a most significant bit, and On stands for a least 
significant bit. 


DTL 


Data Length 


When N is defined as 00, DTL stands for the data length which users are going to read 
out or write into the sector. 


EOT 


End of Track 


EOT stands for the final sector number on a cylinder. During Read or Write operations, 
FDC will stop data transfer after a sector number equal to EOT 


GPL 


Gap Length 


GPL stands for the length of Gap 3. During Read/Write commands this value 

HotDrminoc tho ni imhor r\i h\/toc that V/fT't/QVMr"' \ai\U ctow Im*/ aftesr ti«/r\ PR^ h*/toc 
UcLcI 1 1 III leb 11 Ic 1 IUI 1 IUcI (Jl Uyicb II Idl vi^r^JI 1 1 \\j Will bldy IUW dl Lcl IWU bnL uyicb. 

During Format command it determines the size of Gap 3. 


l-l 


ncdU nUUicbb 


n btdi lUb IUI 1 IcdU 1 IUI llucl UUl 1 , db bpcOlIlcU 111 1 L/ 1 Ibl U . 


HD 


nfcJdu 


HD stands for a selected head number or 1 and controls the polarity of pin 27. (H — 
HD in all command words.) 


HLT 


ntidu LUdu 1 tine 


1— 1 1 ~T cton/Ho f/*\r tho ho^ H l/io*H timD in tho ^r~M~^ ^0 if\ 0^/1 mo in O mo i nr rflmQnfc\ 
tl LI bldl )(Jb lUf lllc i icdu lUdU III Tic in U Ic rUU \c. tU dJO^ lllb 111 c. I Tib IllUicrricTllb^. 


HUT 


ncdU UUHUdU llllle 


1 I IT ctonHc \r\t tho haoH i inlr^aH ti rnfi oft^r o DdoH t~\r \A/nt^ AnQr^f Inn h^o ( irrnrl / 1 ft 
nU I bldl tub IUT II Ic I ledU UI HUdU HI lit? dllcl d rlcdU UF VVi lie upcTdllUi l Ildb UUUUritJU \ I O 

to 240 ms in 16 ms increments). 


MF 


nvi ur ivinvi iviuue 


If 10 I oia/ mn^Q ic eplaotprt iirnH if it c l-iinh K/Ph^ mndo ic polo/'tQW 

ii ivir it) low, nvi muue is seieoteu, anu n it is niyn. ivinvi rnuue is selected. 


MT 


IVIUIlllr dOK 


If MT is high, a Multitrack operation is performed. If MT = 1 after finishing Read/Write 
operation on side 0, FDC automatically starts searching for sector 1 on side 1 . 


M 
IN 


M 1 1 m hor 
INUl rltJCI 


N stands for the Number of data bytes written in a sector. 


INV^IN 


incw ^ym iuci inuihuci 


MPh elanHc for o Moia, fV/liriHar Mi mhor or rlociraH oooitioo of fioQ^ i.fKioh ic- rtninn +0 

inl/In sidrius iui d iNew v^yiinuer iNuniuer ur uesireu pusiuun ui neau wnicn is going to 
be reached as a result of the Seek operation. 


ND 


Non-DMA Mode 


ND stands for operation in the Non-DMA mode. 


PCN 


Present Cylinder Number 


PCN stands for the cylinder number or present position of Head at the completion of 
Sense Interrupt Status command. 


R 


Record 


R stands for the sector number which will be read or written. 


R/W 


Read/Write 


RAW stands for either Read (R) or Write (W) signal. 


SC 


Sector 


SC indicates the number of Sectors per Cylinder. 


SK 


Skip 


SK stands for Skip Deleted Data Address mark. 


SRT 


Step Rate Time 


SRT stands for the Stepping Rate for the FDD (1 to 1 6 ms in 1 ms increments). Stepping 
Rate applies to all drives (F(i 6 ) = 1 ms, E (16 ) = 2 ms, D( 16 ) = 3 ms, . . .). 


STO 
ST1 
ST2 
ST3 


Status 
Status 1 
Status 2 
Status 3 


STO-3 stands for one of four registers which store the status information after a 
command has been executed. This information is available during the result phase after 
command execution. These registers should not be confused with the main status 
register (selected by D/S = 0). STO-3 may be read only after a command has been 
executed and contains information relevant to that particular command. 


STP 


Step 


During a Scan operation, if STP = 1 , the data in contiguous sectors is compared byte 
by byte with data sent from the processor (or DMA); if STP = 2, then alternate sectors 
are read and compared. 


US , US! 


Unit Select 


Used to select between drives 0-3. 



109 



INSTRUCTION SET 1 > 2 



Data Bus 

Phase R/W D 7 D 6 D 5 D 4 D 3 D 2 D^ D Remarks 

Read Data 

Command W MT MF SK 1 1 Command Codes 

W X X X X X HD US! US SeeNote3 

W C Sector ID information prior to 

W H command execution. The 4 bytes 

W R are commanded against header 

W N on Floppy disk. 

W EOT 

W GPL 

W DTL 



Execution Data transfer between the FDD 

and main system 

Result R STO Status information after command 

R ST1 execution 

R ST2 

R C Sector ID information after 

R H command execution 

R R 

R N 



Read Deleted Data 

Command W MT MF SK 1 1 Command Codes 

W X X X X X HD US! US 

W C Sector ID information prior to 

W H command execution. The 4 bytes 

W R are commanded against header 

W N on Floppy Disk. 

W EOT 

W GPL 

W DTL 



Execution Data transfer between the FDD 

and main system 

Result R STO Status information after command 

R ST1 execution 

R ST2 

R C Sector ID information after 

R H command execution 

R R 

R N 



NOTES: 1 . Symbols used in this table are described at the end of this section. 

2. D/S should equal binary 1 for all operations. 

3. X = Don't care, usually made to equal binary 0. 



110 



INSTRUCTION SET 1 - 2 (Continued) 



Data Bus 

Phase R/W D 7 D 6 D 5 D 4 D 3 D 2 D-| D Remarks 



Write Data 

Command W MT MF 1 1 Command Codes 

W X X X X X HD US-i US 

W C Sector IC information prior to 

W H command execution. The 4 bytes 

W R are commanded against header 

W N on Floppy Disk. 

W EOT 

W GPL 

W DTL 



Execution Data transfer between the main 

system and FDD 

Result R STO Status information after command 

R ST1 execution 

R ST2 

R C Sector ID information after 

R ' H command execution. 

R R 

R N 



Write Deleted Data 

Command W MT MF 1 1 Command Codes 

W X X X X X HD US-i US 

W C Sector ID information prior to 

W H command execution. The 4 bytes 

W R are commanded against header 

W N on Floppy disk. 

W EOT 

W GPL 

W DTL 



Execution Data transfer between the FDD 

and main system 

Result R STO Status information after command 

R ST1 execution 

R ST2 

R C Sector ID information after 

R H command execution 

R : R 

R N 

NOTES: 1 . Symbols used in this table are described at the end of this section. 

2. D/S should equal binary 1 for all operations. 

3. X = Don't care, usually made to equal binary 0. 



111 



INSTRUCTION SET 1 - 2 (Continued) 



Data Bus 

Phase R/W D 7 D 6 D 5 D 4 D 3 D 2 0^ D Remarks 

Read A Track 



Command W MF SK 1 Command Codes 

W X X X X X HD US! US 

W C Sector ID information prior to 

W H command execution 

W R 

W N ; 

W EOT 

W GPL 

W DTL 



Execution Data transfer between the FDD 

and main system. FDC reads all 
data fields from index hole to EOT 

Result R STO Status information after command 

R ST1 execution 

R ST2 

R C Sector ID information after 

R H command execution 

R R 

R N 



Read ID 



Command 



W 
W 



MF 

X 





HD 



1 

US-, 





us 



Command Codes 



Execution 



The first correct ID information on 
the cylinder is stored in Data 
Register. 



Result 



STO- 
-ST1 - 
ST2- 

-c- 

-H- 
-R- 
- M — 



Status information after command 
execution 

Sector ID information read during 
Execution phase from Floppy 
Disk. 



NOTES: 1 Symbols used in this table are described at the end of this section. 

2. D/S should equal binary 1 tor all operations. 

3. X = Don't care, usually made to equal binary 0. 



112 



INSTRUCTION SET 1 . 2 (Continued) 



Data Bus 

Phase R/W D 7 D 6 D 5 D 4 D 3 D 2 0, D Remarks 

Format A Track 

Command W MF 1 1 1 Command Codes 

W X X X X X HD USi US 

W N Bytes Sector 

W SC Sectors/Track 

W GPL Gap3 

W D Filler byte 



Execution FDC formats an entire track. 



Result R STO Status information after command 

R ST1 execution 

R ST2 

R C In this case, the ID information 

R H has no meaning. 

R R 

R N 



Scan Equal 

Command W MT MF SK 1 1 Command Codes 

W X X X X X HD USi USn 

W C Sector ID information prior to 

W H command execution 

W R 

W N 

W EOT 

W GPL 

W DTL ' : 



Execution Data compared between the FDD 

and the main system. 

Result R STO Status information after command 

R ST1 execution 

R ST2 

R C Sector ID information after 

R H command execution 

R : R 

R N 

NOTES: 1 . Symbols used in this table are described at the end ol this section. 

2. D/S should equal binary 1 for all operations. 

3, X = Don't care, usually made to equal binary 0. 



113 



INSTRUCTION SET 1 - 2 (Continued) 



Data Bus 

Phase R/W D 7 D 6 D 5 D 4 D 3 D 2 Di D Remarks 

Scan Low or Equal 

Command W MT MF SK 1 1 1 Command Codes 

W X X X X X HD US-i USo 

W C Sector ID information prior to 

W H command execution 

W R 

W N 

W EOT 

W GPL 

W — STP 

Execution Data compared between the FDD 

and main system 

Result R STO Status information after command 

R ST1 execution 

R ST2 

R C Sector ID information after 

R H command execution 

R R 

R N 

Scan High or Equal 

Command W MT MF SK 1 1 1 1 Command Codes 

W X X X X X HD US! USo 

W C Sector ID information prior to 

W H command execution. 

W R 

W N 

W EOT 

W GPL 

W STP 



Execution Data compared between the FDD 

and main system. 

Result R STO ■ Status information after command 

R ST1 execution 

R ST2 

R C Sector ID information after 

R H command execution. 

R R 

R N 

Recalibrate 

Command W 1 1 1 Command Codes 

W X X X X X USi USo 



Execution Head retracted to Track 



NOTES: 1 . Symbols used in this table are described at the end of this section. 

2. D/S should equal binary 1 for all operations. 

3. X = Don't care, usually made to equal binary 0. 



114 



INSTRUCTION SET 1 - 2 (Continued) 













Data Bus 








Phase 


R/W 








D 4 D 3 D 2 


D1 


Do 


Remarks 


Sense Interrupt Status 


Command 


W 











1 








Command Codes 


Result 


R 
R 














Status information about the FDC 
at the end of seek operation 








STO 














PCN 






Specify 


Command 


W 

w 
w 














1 


1 


Command Codes 




— SRT- 










-HUT — 












HLT 




ND 




Sense Drive Status 


Command 


w 
w 



X 



X 



X 


1 
X X HD 



US, 




us 


Command Codes 


Result 


R 














Status information about FDD 








ST3 






Seek 


Command 


W 
W 

w 



X 



X 



X 


1 1 
X X HD 


1 

US, 


1 

us 


Command Codes 










NCN 








Execution 
















Head is positioned over proper 
cylinder on diskette. 


Invalid 


Command 


w 














Invalid Command Codes 
(NoOp— FDC goes into Standby 
state.) 








Invalid Codes 






Result 


R 














STO = 80(H) 








STO 







NOTES: 1. Symbols used inthistable are described at the end of this section. 

2. D/S should equal binary 1 for all operations. 

3. X = Don't care, usually made to equal binary 0. 



115 



DMA mode, no interrupts are generated during the 
Execution phase. The Z765A generates DRQs (DMA 
Requests) when each byte of data is availabl e. The DMA 
Controller responds to this request with both a DACK (DMA 
Acknowledge) = and an RD (Read signal) = 0. When the 
DMA Acknowledge signal goes Low (DACK = 0), then the 
DMA request is cleared (DRQ = 0). It a Write command has 
been issued, a WR signal appears instead of RD. After the 
Execution phase has been completed [Terminal Count (TC) 
has occurred] or the last sector on the cylinder (EOT) 
read/written, then an interrupt occurs (INT = 1) which 
signifies the beginning of the Result phase. When the first 
byte of data is read during the Result phase, the interrupt is 
automatically cleared (INT = 0). 

The RD or WR signals should be asserted while DACK is 
true. The CS signal is used in conjunction with RD and WR 
as a gating function during programmed I/O operations. CS 
has no effect during DMA operations. If the non-DMA mode 
is chosen, the DACK signal should be pulled up to Vcc- 

During the Result phase all bytes shown in the Command 
Table must be read. For example, the Read Data command 



has seven bytes of data in the Result phase; all seven bytes 
must be read to successfully complete the Read Data 
command and allow the Z765A to accept a new command. 

The Z765A contains five Status registers. The Main Status 
register can be read at any time by the processor. The other 
four Status registers (STO, ST1 , ST2, and ST3) are available 
only during the Result phase and can be read only after 
completing a command. The particular command that has 
been executed determines how many of the Status registers 
are read. 

The bytes of data which are sent to the Z765A to form the 
Command phase and are read out of the Z765A in the 
Result phase must occur in the order shown in the 
Command Table. That is, the Command Code must be sent 
first and the other bytes sent in the prescribed sequence. No 
foreshortening of the Command or Result phases is allowed. 
After the last byte of data in the Command phase is sent to 
the Z765A, the Execution phase automatically starts. In a 
similar fashion, when the last byte of data is read out in the 
Result phase, the command is automatically ended and the 
Z765A is ready for a new command. 



POLLING FEATURE OF THE Z765A 



After Reset is sent to the Z765A, the Unit Select lines US 
and USi automatically go into a polling mode (Figure 5). 
Between commands (and between step pulses in the Seek 
command) the Z765A polls all four FDDs looking for a 
change in the Ready line from any of the drives. If the Ready 
line changes state (usually due to a door opening or 
closing), then the Z765A generates an interrupt. When 
Status register (STO) is read (after Sense Interrupt Status is 



issued), Not Ready (NR) is indicated. The polling of the 
Ready line by the Z765A occurs continuously between 
commands, thus notifying the processor which drives are 
on or off line. Each drive is polled every 1 .024 ms except 
during the Read/Write commands. When used with a 4 MHz 
clock for interfacing to minifloppies, the polling rate is 2.048 
ms. 



- APPROX. 1.0 ms - 



- 760^ - 



us, 



Figure 5. Polling Features 



116 



COMMANDS 



Read Data 

A set of nine (9) byte words are required to place the FDC 
into the Read Data Mode. After the Read Data command is 
issued, the FDC loads the head (if it is in the unloaded state), 
waits the specified head settling time (defined in the Specify 
command), and begins reading ID Address Marks and ID 
fields. When the current sector number (R) stored in the ID 
Register (I DR) compares with the sector number read off the 
diskette, then the FDC, via the data bus, outputs data 
byte-to-byte from the data field to the main system. 

After completion of the read operation from the current 
sector, the Sector Number is incremented by one, and the 



data from the next sector is read and output on the data bus. 
This continuous read function is called a Multi-Sector Read 
Operation. The Read Data command can be terminated by 
the receipt of a TC signal which should be issued when the 
DACK for the last byte of data is sent. Upon receipt of this 
signal, the FDC stops outputting data to the processor, but 
continues to read data from the current sector, checks 
Cyclic Redundancy Count (CRC), and at the end of the 
sector, terminates the Read Data command. The amount of 
data which can be handled with a single command to the 
FDC depends upon multitrack (MT), MFM/FM (MF), and 
Number of Bytes/Sector (N). Table 3 shows the Transfer 
Capacity. 



Table 3. Transfer Capacity 









Maximum Transfer Capacity 


Final Sector 


Multi-Track 


MFM/FM 


Bytes/Sector 


(Bytes/Sector) 


Read from 


MT 


MF 


N 


(Number of Sectors) 


Diskettes 








00 


(128) (26) 




3,328 


26 at Side 





1 


01 


(256) (26) 




6.656 


or 26 at Side 1 


1 





00 


(128) (52) 




6,656 


26 at Side 1 


1 


1 


01 


(256) (52) 




13,312 










01 


(256) (15) 




3,840 


15 at Side 





1 


02 


(512) (15) 




7,680 


or 15 at Side 1 


1 





01 


(256) (30) 




7,680 


1 5 at Side 1 


1 


1 


02 


(512) (30) 




15,360 










02 


(512) (8) 




4,096 


8 at Side 





1 


03 


(1024) (8) 




8,192 


or 8 at Side 1 


1 





02 


(512) (16) 




8,192 


8 at Side 1 


1 


1 


03 


(1024) (16) 




16,384 



MT allows the FDC to read data from both sides of the 
diskette. For a particular cylinder, data is transferred starting 
at Sector 1 , Side and completing at the last sector, Sector 
L, Side 1 . This function pertains to only one cylinder (the 
same track) on each side of the diskette. 

When N = 0, then DTL defines the data length which the 
FDC must treat as a sector. If DTL is smaller than the actual 
data length in a Sector, the data beyond DTL in the Sector is 
not sent to the Data Bus. The FDC internally reads the 
complete sector performing the CRC check and. 
depending upon the manner of command termination, may 
perform a Multi-Sector Read Operation. When N is 
non-zero, then DTL has no meaning and should be set to 
FF H . 

At the completion of the Read Data Command the head is 
unloaded, after the Head Unload Time Interval specified in 
the Specify Command has elapsed. If the processor issues 
another command before the head unloads, there is no 
head settling time between subsequent reads. This time 
saved is particularly valuable when a diskette is copied. 



If the FDC twice detects the index hole without finding the 
right sector (R), then the FDC sets Status register 1 's No Data 
(ND) flag to 1 , and terminates the Read Data command. 
(Status register also has bits 7 and 6 set to and 1 
respectively.) 

After reading the ID and Data fields in each sector, the FDC 
checks the CRC bytes. If a read error is detected indicating 
incorrect CRC in the ID field, the FDC sets Status register 1's 
Data Error (DE) flag to 1 , and if a CRC error occurs in the 
Data Field, the FDC also sets Status register 2's Data Error in 
Data Field (DD) flag to 1 , and terminates the Read Data 
command. (Status register 0, bit 7 = 0, bit 6 = 1 .) 

If the FDC reads a Deleted Data Address Mark off the 
diskette, and the SK bit D in the first Command Word = 0, 
then the FDC sets Status register 2's Control Mark (CM) flag 
to 1 , and after reading all the data in the sector, terminates 
the Read Data command. If SK = 1, the FDC skips the 
sector with the Deleted Data Address Mark and reads the 
next sector. When SK = 1 , the CRC bits in the deleted data 
field are not checked. 



117 



(OR) flag to 1 , 


>o, u ic i acta ocaiuo leyissier i s uverrun 
and terminates the Read Data command. 


4 shows the values for C, H, R, and N when the processor 
terminates the command. 






Table 4. C, H, R, and N Values When Processor Terminates Commands 










Final Sector Transferred 




ID Information at Result Phase 




MT 


HD 


to Processor 


c 


H 


R 


N 







Less than EOT 


NC 


NC 


R + 1 


NC 








Equal to EOT 


C + 1 


NC 


R = 01 


NC 




1 


Less than EOT 


NC 


NC 


R + 1 


NC 




1 


Equal to EOT 


C + 1 


NC 


R = 01 


NC 







Less than EOT 


NC 


NC 


R + 1 


NC 


1 





Equal to EOT 


NC 


LSB 


R = 01 


NC 


1 


Less than EOT 


NC 


NC 


R + 1 


NC 




1 


Equal to EOT 


C + 1 


LSB 


R = 01 


NC 



NOTES: NC (No Change): The same value as the one at the beginning of command execution. 
LSB (Least Significant Bit): The least significant bit of H is complemented. 



Write Data 

A set of nine (9) bytes is required to set the FDC in the Write 
Data mode. After the Write Data command is issued, the 
FDC loads the head, waits the specified head setting time, 
and begins reading ID fields. When all four bytes (C, H, R, 
and N) loaded during the command match the four bytes of 
the ID field from the diskette, the FDC takes data from the 
processor byte-by-byte via the data bus and outputs it to the 
FDD. 

After writing data into the current sector, the sector number 
stored in the R register is incremented by one, and new data 
is written into the next data field. The FDC continues this 
Multisector Write Operation until a Terminal Count signal is 
issued. If a Terminal Count signal is sent to the FDC, it 
continues writing into the current sector to complete the data 
field. If the Terminal Count signal is received while a data 
field is being written, the remainder of the data field is filled 
with zeros. 

The FDC reads the ID field of each sector and checks the 
CRC bytes. If the FDC detects a read error (CRC error) in 
one of the I D fields, it sets Status register 1 's DE flag to 1 , and 
terminates the Write Data command. (Status register 0, bit 
7 = 0, bit 6 = 1.) 

The Write command operates in the same manner as the 
Read command for the following items: 

■ Transfer capacity 

■ End of cylinder (EN) flag 

■ No data (ND) flag 

■ Head unload time interval 



■ ID information when the processor terminates command 

■ Definition of DTL when N = and when N + 

Refer to the Read Data command for details. 

In the Write Data mode, data transfers between the 
processor and FDC via the data bus, must occur every 27^s 
intheFM mode and every 13f/s in the MFM mode. If the time 
interval between data transfers is longer, then the FDC sets 
Status register 1's Overrun (OR) flag to 1 , and terminates the 
Write Data command. (Status register 0, bit 7 = 0, bit 6 = 1 .) 

Write Deleted Data 

This command is the same as the Write Data command 
except a Deleted Data Address mark, instead of the normal 
Data Address mark, is written at the beginning of the data 
field. 

Read Deleted Data 

This command is the same as the Read Data command 
except that when the FDC detects a Data Address mark at 
the beginning of a data field and SK = 0, the FDC reads all 
the data in the sector and sets Status register 2's CM flag to 
1 , and terminates the command. If SK = 1 , then the FDC 
skips the sector with the Data Address mark and reads the 
next sector. 

Read Track 

This command is similar to the Read Data command except 
that this is a continuous Read operation 'where the entire 
data field from each of the sectors is read. Immediately after 



118 



sensing the index hole, the FDC starts reading all data fields 
on the track as continuous blocks of data. If the FDC finds an 
error in the ID or DataCRC check bytes, it continues to read 
data from the track. The FDC compares the ID information 
read from each sector with the value stored in the IDR and, if 
there is no comparison, sets Status register 1's ND flag to 1 . 
Multitrack or skip operations are not allowed with this 
command. 

This command terminates when the number of sectors read 
is equal to EOT. If the FDC does not find an ID Address mark 
on the diskette after it senses the index hole for the second 
time, it sets Status register 1's Missing Address mark (MA) 
flag to 1 and terminates thecommand. (Status RegisterO, bit 
7 = 0, bit 6 = 1 .) 

Read ID 

The Read ID command gives the present position of the 
recording head. The FDC stores the values from the first ID 
field it can read. If no proper ID Address mark is found on the 
diskette before the index hole is encountered for the second 
time, Status register 1 's MA flag is set to 1 ; if no data is found, 
Status register Ts No Data (ND) flag is set to 1. The 
command is then terminated with STO bit 7 = and bit 
6 = 1. During this command, data transfer between FDC 
and the CPU occurs only during the result phase. 

Format Track 

The Format command allows an entire track to be formatted. 
After the index hole is detected, data is written on the 
diskette; Gaps, Address marks, ID fields and data fields, all 
per the IBM 3740 Single Density format or IBM System 34 
Double Density format, are recorded. The processor, during 
the command phase, supplies values i.e., Number of 
bytes/sector (N), Sectors Cylinder (SC), Gap Length (GPL), 
and Data Pattern (D) which determine the particular format 
to be written. 

The data field is filled with the byte of data stored in D. The ID 
field for each sector is supplied by the processor; that is, four 
data requests per sector are made by the FDC for Cylinder 
number (C), Head number (H), Sector number (R), and 
Number of bytes/sector (N). This allows diskette formatting 
with nonsequential sector numbers. 

The processor must send new values for C, H, R, and N to 
the Z765A for each sector on the track. If FDC is set for the 
DMA mode, it issues four DMA requests per sector. If it is set 
for the Interrupt mode, it issues four interrupts per sector and 
the processor must supply C, H. R, and N loads for each 
sector. The contents of the R register are incremented by 1 
after each sector is formatted; thus, the R register contains a 
value of R when it is read during the Result phase. This 
incrementing and formatting continues for the whole track 
until the FDC detects the index hole for the second time, 
whereupon it terminates the command. 

If the Fault signal is received from the FDD at the end of a 
Write operation, the FDC sets Status register 0's EC flag to 1 



and terminates the command after setting Status register 0, 
bit 7 to and bit 6 to 1 . Also the loss of a Ready signal at the 
beginning of a command execution phase causes Status 
register 0, bit 7 and 6 to be set to and 1 respectively. 

Table 5 shows the sector size relationship between N, SC, 
and GPL. 



Table 5. Functional Description of Commands 



Format 


Sector Size N 


SC 


GPL 1 


GPL 2 ' 3 


8" Standard Floppy 




128 byt 


es sector 00 


1A 


07 


1B 




256 


01 


OF 


0E 


2A 


FM Mode 


512 


02 


08 


1B 


3A 


1024 


03 


04 


47 


8A 




2048 


04 


02 


C8 


FF 




4096 


05 


01 


C8 


FF 




256 


01 


1A 


0E 


36 




512 


02 


OF 


1B 


54 


MFM 


1024 


03 


08 


35 


74 


Mode 4 


2048 


04 


04 


99 


FF 




4096 


05 


02 


C8 


FF 




8192 


06 


01 


C8 


FF 


5V 4 " Minifloppy 




1 28 bytes/sector 00 


12 


07 


09 




128 


00 


10 


10 


19 


FM Mode 


256 


01 


08 


18 


30 


512 


02 


04 


46 


87 




1024 


03 


02 


C8 


FF 




2048 


04 


01 


C8 


FF 




256 


01 


12 


OA 


OC 




256 


01 


10 


20 


32 


MFM 


512 


02 


08 


2A 


50 


Mode 4 


1024 


03 


04 


80 


F0 




2048 


04 


02 


C8 


FF 




4096 


05 


01 


C8 


FF 



NOTES: 1 . Suggested values of GPL in Read or Write commands to 

avoid splice point between data field and ID field of contiguous 
sections. 

2. Suggested values of GPL in format command. 

3. All values except sector size are hexidecimal. 

4. In MFM mode FDC cannot perform a Read/Write format 
operation with 1 28 bytes sector. (N = 00) 



119 



Scan Commands 



The Scan commands allow comparison of data read from 
the diskette and data supplied from the main system. The 
FDC compares the data on a byte-by-byte basis and looks 
for a sector of data which meets the conditions of Dfdd = 
^Processor. E>FDD < ^Processor, or DpDD > Dp rocessor . The 
hexadecimal byte of FF from memory or from FDD can be 
used as a mask byte because it always meets the condition 
of the comparison. One's complement arithmetic is used for 
comparison (FF = largest number, 00 = smallest number). 
After a whole sector of data is compared, if the conditions 
are not met, the sector number is incremented (R + STP -* 
R) and the scan operation continues until one of the 
following conditions occur: the conditions for scan are met 
(equal, low, or high), the last sector on the track is reached 
(EOT), or the terminal count (TC) signal is received. 

If the conditions for scan are met, the FDC sets the Status 
register 2's Scan Hit (SH) flag to 1 and terminates the Scan 
command. If the conditions for scan are not met between 
the starting sector number (R) and the last sector on the 
cylinder (EOT), then the FDC sets Status register 2's Scan 
Not Satisfied (SN) flag to 1, and terminates the Scan 
command. During the scan operation, the receipt of a signal 
from the processor or DMA controller causes the FDC to 
complete the comparison of the particular byte in process 
and then to terminate the command. Table 6 shows the 
status of bits SH and SN under various conditions of Scan. 



Table 6. 




Status Register 2 




Command 


Bit 2 = 


SN Bit 3 = SH 


Comments 


Scan Equal 





1 


D FDD = Dp r0 cessor 










1 





DfqD * Dprocessor 


Scan Low 
or Equal 





1 


D FDD = Dp roC essor 








D FDD < Dprocessor 




1 





DFDD > Dprocessor 


Scan High 





1 


D FDD ■ Dp mcessor 








or Equal 








Dfdd > Dp rocessor 









°FDD < Dprocessor 



If the FDC encounters a Deleted Data Address mark on one 
of the sectors and SK = 0, then it regards the sector as the 
last sector on the cylinder, sets Status register 2's Control 
Mark (CM) flag to 1 and terminates the command. If SK = 1, 
the FDC skips the sector with the Deleted Address mark, 
reads the next sector, and sets Status register 2's Control 
Mark (CM) flag to 1 to show that a Deleted sector has been 
encountered. 

When either the Step (STP) (contiguous sectors = 01 or 
alternate sectors = 02) sectors are read or the Multitrack 



(MT) is programmed, the last sector on the track must be 
read. For example, if STP = 02, MT = 0, the sectors are 
numbered sequentially 1 through 26 and the Scan 
command is started at sector 21, the following happens. 
Sectors 21 , 23, and 25 are read, then the next sector, 26, is 
skipped and the index hole is encountered before the EOT 
value of 26 can be read resulting in an abnormal termination 
of the command. If the EOT had been set at 25 or the 
scanning started at sector 20, then the Scan command 
would be completed in a normal manner. 

During the Scan command, data is supplied by either the 
processor or DMA Controller for comparison against the 
data read from the diskette. In order to avoid having Status 
register 1's Overrun (OR) flag set, it is necessary to have the 
data available in less than 27/js (FM mode) or 13»iS (MFM 
mode). If an Overrun occurs, the FDC ends the command 
with Status register 0, bit 7 cleared to and bit 6 set to 1 . 

Seek 

The Read/Write head within the FDD is moved from cylinder 
to cylinder under control of the Seek command. The FDC 
has four independent Present Cylinder registers for each 
drive which are cleared only after the Recalibrate command. 
The FDC compares the Present Cylinder Number (PCN) 
which is the current head position with the New Cylinder 
Number (NCN), and if there is a difference, performs the 
following operations: 

PCN < NCN: Direction signal to FDD set to 1, and Step 
Pulses are issued. (Step In) 

PCN > NCN: Direction signal to FDD cleared to 0, and Step 
Pulses are issued. (Step Out) 

The rate at which Step pulses are issued is controlled by 
Stepping Rate Time (SRT) in the Specify command. After 
each Step pulse is issued NCN is compared against PCN, 
and when NCN = PCN, Status register 0's Seek End (SE) 
flag is set to 1, and the command is terminated. At this point 
FDC interrupt goes High. Bits D -D 3 in the Main Status 
register are set during the Seek operation and are cleared 
by the Sense Interrupt Status command. 

During the command phase of the Seek operation the FDC 
is in the FDC Busy state, but during the execution phase it is 
in the Nonbusy state. While the FDC is in the Nonbusy state, 
another Seek command may be issued, and in this manner 
parallel Seek operations may be done on up to four drives at 
once. No other command can be issued for as long as the 
FDC is in the process of sending step pulses to any drive. 

If an FDD is in a Not Ready state at the beginning of the 
command execution phase or during the Seek operation, 
then Status register 0's Not Ready (NR) flag is set to 1 , and 
the command is terminated after bit 7 is set to 1 and bit 6 to 0. 

If writing three bytes of Seek command exceeds 1 50^s, the 
timing between the first two step pulses may be 1 ms shorter 
than that set in the Specify command. 



120 



Recalibrate 

The function of this command is to retract the Read/Write 
head within the FDD to the Track position. The FDC clears 
the contents of the PCN counter and checks the status of the 
Track signal from the FDD. As long as the Track signal is 
Low, the Direction signal remains and step pulses are 
issued. When the Track signal goes High, the Status 
register O's SE flag is set to 1 and the command is 
terminated. If the Track signal is still Low after 77 step 
pulses have been issued, the FDC sets Status register O's SE 
and Equipment Check (EC) flags to 1s and terminates the 
command after Status register 0, bit 7 is cleared to and bit 
6 is set to 1 . 

The ability to do overlap Recalibrate commands to multiple 
FDDs and the loss of the Ready signal, as described in the 
Seek command, also applies to the Recalibrate command. 
If the Diskette has more than 77 tracks, the Recalibrate 
command should be issued twice, in order to position the 
Read/Write head to Track 0. 

Sense Interrupt Status 

An interrupt signal is generated by the FDC for one of the 
following reasons: 

1 . Upon entering the Result phase of command: 

□ Read Data □ Read Track 

□ Write Data □ Read ID 

□ Write Deleted Data □ Format Track 

□ Read Deleted Data □ Scan 

2. Ready Line of FDD changes state 

3. End of Seek or Recalibrate command 

4. During Execution phase in the non-DMA mode 

Interrupts caused by reasons 1 and 4 occur during normal 
command operations and are easily discernible by the 
processor. During an execution phase in non-DMA mode, 
D 5 in the Main Status Register is High. Upon entering the 
Result phase this bit is cleared. Reasons 1 and 4 do not 
require Sense Interrupt Status commands. The interrupt is 
cleared by Reading/Writing data to the FDC. Interrupts 
caused by reasons 2 and 3 may be uniquely identified with 
the aid of the Sense Interrupt Status command which resets 
the Interrupt signal and, via bits 5, 6, and 7 of Status register 
0, identifies the cause of the interrupt (Table 7). 

Table 7. interrupt Identification 



Seek End 
Bit 5 


Interrupt Code 
Bit 6 Bit 7 


Cause 





1 


1 


Ready Line changed state, 
either polarity 


1 








Normal Termination of Seek 
or Recalibrate command 


1 


1 





Abnormal Termination of 



The Sense Interrupt Status command is used in conjunction 
with the Seek and Recalibrate commands which have no 
result phase. When the disk has reached the desired head 
position, the Z765A sets the interrupt line true. The host CPU 
must then issue a Sense Interrupt Status command to 
determine the actual cause of the interrupt, which could be 
Seek End or a change in ready status from one of the drives. 
Figure 6 is a graphic example. 

Specify 

The Specify command sets the initial values for each of the 
three internal timers. The Head Unload Time (HUT) defines 
the time from the end of the execution phase of one of the 
Read/Write commands to the head unload state. This timer 
is programmable from 16 to 240ms in increments of 16ms 
(01 = 16ms, 02 = 32ms.. .OF 16 = 240ms). The Step Rate 
Time (SRT) defines the time interval between adjacent step 
pulses. This timer is programmable from 1 to 16ms in 
increments of 1 ms (F = 1 ms, E = 2ms, and D = 3ms). The 
Head Load Time (HLT) defines the time between the Head 
Load signal's going High and the start of the ReadAVrite 
operation. This timer is programmable from 2 to 254ms in 
increments of 2ms (01 = 2ms, 02 = 4ms, 03 = 6ms.. ,7F = 
254ms). 

The time intervals mentioned are a direct function of the 
8MHz clock; if the clock were reduced to 4MHz (minifloppy 
application), all time intervals would be increased by a factor 
of 2. 

The choice of a DMA or non-DMA operation is made by the 
Non-DMA (ND) bit. When this bit is High (ND = 1), the 
Non-DMA mode is selected: when ND = 0, the DMA mode 
is selected. 

Sense Drive Status 

The processor uses this command to obtain the status of the 
FDDs. Status register 3 contains the Drive Status information 
stored internally in FDC registers. 

Invalid 

If an Invalid command (not defined above) is sent to the 
FDC, then the FDC terminates the command after Status 
Register bit 7 is set to 1 and bit 6 to 0. No interrupt is 
generated by the Z765A during this condition. Bits 6 and 7 
(DIO and RQM) in the Main Status register are both High, 
indicating to the processor that the Z765A is in the Result 
phase and the contents of Status register (STO) must be 
read. When the processor reads Status register 0, it finds an 
80 H indicating the receipt of an Invalid command. 

A Sense Interrupt Status command must be sent after a 
Seek or Recalibrate Interrupt, otherwise the FDC considers 
the next command as an Invalid command. 

This command may be used as a No-Op command to place 
the FDC in a standby or No Operation state. 



Seek or Recalibrate 
command 



121 



~U~LTLJL_rLn_J 



-"iLrrLunLTJH 



U U IT 

— u — \r~ 



_n_ 



U IT 

ji n_ 



t t 

OPCODE FOR HD/DR1VE NOT 

INSTRUCTION WRITTEN 

WRITTEN INTO Z76SA 
INTO Z765A 




"IT 
Jl 



OPCODE FOR 
INSTRUCTION 
WRITTEN 
INTO Z765A 



X 
JL 



Figure 6. Seek, Recalibrate, and Sense Interrupt Status 



X 
X 



GAP 4b 
40* 


SVNC 
6x 


1 AM 

FC 


GAP 1 
26x 


SYNC 
fix 


IDAM 
FE 


C 
V 


H 

D 


S 
E 


N 




C 
R 


GAP 2 


SVNC 
6x 


DATA AM 
FB OR FB 


DATA 


C 
R 


GAP 3 


GAP 4b 


FF 


00 


FF 


00 


L 




C 




C 


FF 


00 




C 







Figure 7. Data Format, FM Mode 



- REPEAT N TIMES - 



Figure 8. Data Format, MFM Mode 



-if- 



7C 



GAP 4a 1AM GAP 1 ID GAP 2 



NOTE; Read - 



Write — — — 



f 



\u — v 



Figure 9. Data Timing Relationships 




AC CHARACTERISTICS 

T A = -10°Cto + 70°C; V cc = +5V ± 5% unless otherwise specified. 



Number Symbol 



Min Typ 1 Max 



Unit 



Test Condition 









120 


125 


500 




1 


TcC 


Clock Cycle Time 




125 
250 




ns 
ns 


2 


TwCh 


Clock Width (High) 


40 






ns 


2a 


TwCI 


Clock Width (Low) 


40 






ns 


3 


TrC 


Clock Rise Time 






20 


ns 


4 


TfC 


Clock Fall Time 






20 


ns 


5 


TsAR 


D/S, CS, DACK to RD 1 Setup Time 









ns 


6 


ThRA 


D/S, CS, DACK from RD t Hold Time 









ns 


7 


TwRD 


RD Width 


250 






ns 


8 


TdRDf (Do) 


RD i to Data Output Delay 






200 


ns 


9 


TdRDr (Dz) 


RD t to Data Float Delay 


20 




100 


ns 


10 


TsCS(WRf) 


Control Signal (D/S. CS. DACK) to 
WRi Setup Time 









ns 


11 


ThCS(WRr) 


Control Signal (D/S, CS, DACK) from 
WRt Hold Time 









ns 


12 


TwWR 


WR Width 


250 






ns 


13 


TsDfWRr) 


Data to WRt Setup Time 


150 






ns 


14 


ThD(WRr) 


Data from WR t Hold Time 


5 






ns 


15 


TdRDr(INT) 


RD t to INT Delay Time 






500 


ns 


16 


TdWRr(INT) 


WRt to INT Delay Time 






500 


ns 


I / 


ICUHU 


uhu oycie 1 ime 


13 






MS 


18 


TdDRQ(DACK) 


DACK A to DRQ 4 Delay 






200 


ns 


19 






onn 






ns 






nAPK - W/iHth 
UML/f\ VVlUlll 


o 
f 






I CL- 


21 


T\A/TP 
IW I o 


TP WiHIh 


1 
I 






1 


22 


TwRST 


Rpept Wirlth 


14 


4 




TcC 
M s 


23 


TcWCK 


WCK Cycle Time 




2 
2 




Its 




24 


TwWCKh 


WCK Width (High) 


80 


1 

250 


350 


IIS 

Ds- 


25 


TrWCK 


WCK Rise Time 






20 


ns 


26 


TfWCK 


WCK Fall Time 






20 


ns 


27 


TdWCKr(PS) 


WCK t to Preshift Delay Time 


20 




100 


ns 


OB 


T^\A/f"*L'rAA/Cr\ 


WL/i\ T to wl T ueiay I ime 


20 




100 


ns 






wl*k t to wua ueiay i ime 






100 


ns 


an 


TuDnnh 
iwnuun 


nUU Wiutn (nign) 


40 


4 




ns 
MS 


■31 
J I 


I WUI 


Window Cycle Time 




2 
2 
1 




MS 
MS 
MS 


32 


TsW(RDDh) 
ThW(RDDI) 


Window to RDD t Setup Time 
Window from RDD i Hold Time 


15 






ns 


33 


TsUS(RWh) 


Unit Select to RW/SEEK t Setup Time 


12 






MS 


34 


TsRWr(DIR) 


RW/SEEK t to LCT/DIR Setup Time 


7 






MS 


35 


TsDIR(STEPr) 


LCT/DIR to STEP t Setup Time 


1 






MS 


36 


ThUS(STEPI) 


Unit Select from STEP i Hold Time 


5 






MS 



8" FDD 
5V4" FDD 



C L = 100 pf 
C L = 100 pf 



TcC = 1 25 ns 



MFM = 5V4" 
MFM = 1 5V4" 
MFM = 8" 
-MFM = 1 8" 



MFM 


= 


5V4" 


MFM 


= 1 


5V4" 


MFM 


= 


8" 


MFM 


- 1 


8" 



NOTES: 1 . Typical values for T A = 25 °C and nominal supply voltage, 

2. Under software control, the range is from 1 ms to 1 6 ms at 8 MHz clock period. 



123 



AC CHARACTERISTICS (Continued) 

T A = -10°Cto + 70°C;V C c = +5V ± 5% unless otherwise specified. 



Number Symbol 


Parameter 


Min 


Typ 1 Max 


Unit 


Test Condition 


37 


TwSTEPh 


STEP Width (High) 


6 


7 8 


MS 




38 


TcSTEP 


STEP Cycle Time 


16 


Note 2 Note 2 


MS 




39 


TwFRh 


FAULT RESET Width (High) 


8 


10 


MS 




40 


TwWDAh 


Write Data (WDA) Width (High) 


Tn-50 




ns 




41 


ThUS(SEEKf) 


Unit Splprt from RW/SFFK I Hnld Time 

KJ 1 II L OCIC^l IIUIIinVV»Ol_l_I\*IIUI»J IIIIIC 


15 








42 


ThSEEK(DIR) 


RW/SFFK fmm 1 CT/DIR Hold Timp 


30 




| JO 




43 


ThDIR(STEPf) 


LCT/DIR from STEP * Hold Time 


24 




MS 




44 


TwIDX 


INDEX Width (High and Low) 


4 




TcC 




45 


TdDRQh(RDI) 


DRQ 1 to RDi Delay Time 


800 




ns 




46 


TdDRQh(WRI) 


DRQ t to WR i Delay Time 


250 




ns 




47 


TdDRQh(RWh) 


DRQ t to RD t or WR t Delay Time 




12 


MS 




NOTES: 1 


Typical values for T A 


= 25 °C and nominal supply voltage. 











2. Under software control, the range is from 1 ms to 1 6 ms at 8 MHz clock period. 



Processor Read Operation 



D/S, CS, DACK 



SSL 




© 



S 



X 



® 



]i — 



Processor Write Operation 



O/S, CS, DACK 



® 



x 



-©- 



-®- 



® 



X 



® 



X 



V 



124 



DMA Operation 



®* 



-®- 



\ / 



FDD Write Operation 



WRITE CLOCK 



WRITE ENABLE 



PRESHIFT OR 1 



@ 



— ® 



WRITE DATA 



®* 



-®- 



X 



xz 



A A A 





Preshift 


Preshift 1 


Normal 








Late 





1 


Early 


1 






Seek Operation 



os ,i 



X 



■®- 



© 



■®- 



DIRECTION 



:cd: 



JTi 

® 



-ff- 



-®- 



125 



INDEX 



FAULT RESET = 



FDD Read Operation 



— »-( 


\ 


















- ® . 



Terminal Count 



RESET 



® 



126 



ABSOLUTE MAXIMUM RATINGS 

T A = 25 °C 



Operating Temperature 0°Cto + 70°C 

Storage Temperature - 65 °C to + 1 50 °C 

All Output Voltages -.5Vto +7V 

All Input Voltages - 5Vto + 7V 

Supply Voltage V cc - 5V to + 7V 

Power Dissipation 1W 



Stresses greater than those listed under Absolute Maximum Ratings may 
cause permanent damage to the device- This is a stress rating only; 
operation of the device at any condition above these indicated in the 
operational sections of these specifications is not implied. Exposure to 
absolute maximum rating conditions for extended periods may affect 
device reliability. 



DC CHARACTERISTICS 

T A = 0°C to + 70°C; V cc = + 5V ± 5% unless otherwise specified. 

Symbol Parameter Min Typ* Max Unit Test Condition 



V|L 


Input Low Voltage 


-0.5 


0.8 


V 






V|H 


Input High Voltage 


2.0 


Vcc + 05 


V 






Vol 


Output Low Voltage 




0.40 


V 


IOL = 


2.0 mA 


V H 


Output High Voltage 


2.4 


v C c 


V 


IfOH = 


-200(jA 


VlLC 


Input Low Voltage (CLK + WR Clock) 


-0.5 


0.65 


V 






VlHC 


Input High Voltage (CLK + WR Clock) 


2.4 


Vcc + 0-5 


V 






ice 


Vqc Supply Current 




150 


mA 






ka 


Input Load Current 




10 


HA 


V|N = 


VCC 


(All Input Pins) 




-10 


MA 


VlN = 


ov 


!lOH 


High Level Output Leakage Current 




10 


«A 


Vout 


= v cc 


'lOL 


Low Level Output Leakage Current 




-10 


M A 


VOUT 


= +0.40V 



"Typical values for T A = 25°C and nominal supply voltage. 



CAPACITANCE 

T A = 25 °C; f c = 1 MHz; V cc = 0V 



Symbol 



Parameter 



Min 



Max 



Unit 



Test Condition 



c CLOCK Clock Input Capacitance 
Cin Input Capacitance 

Cqut Output Capacitance 



20 
10 
20 



PF 
pF 
pF 



All pins except pin under 
test tied to AC Ground 



127 



Zilog 



ADVANCED INFORMATION 
Product Specification 



Z8001 Z8002 

Z8000 CPU 

Central Processing Unit 



October 1988 



FEATURES 



Regular, easy-to-use architecture 

Instruction set more powerful than many minicomputers 

Directly addresses 8 Mbytes 

Eight user-selectable addressing modes 

Seven data types that range from bits to 32-bit long words 
and byte and word strings 

System and Normal operating modes 

Separate code, data, and stack spaces 

Sophisticated interrupt structure 



Resource-shaping capabilities for multiprocessing 
systems 

Multi-programming support 
Compiler support 

Memory management and protection provided by 
Z8010 Memory Management Unit 

32-bit operations, including signed multiply and divide 

Z-BUS compatible 

4, 6, and 10 MHz clock rate 



GENERAL DESCRIPTION 



The Z8000 is an advanced high-end 1 6-bit microprocessor 
that spans a wide variety of applications ranging from simple 
stand-alone computers to complex parallel-processing 
systems. Essentially a monolithic minicomputer central 
processing unit, the Z8000 CPU is characterized by an 
instruction set more powerful than many minicomputers; 
abundant resources in registers, data types, addressing 
modes and addressing range, and a regular architecture 
that enhances throughput by avoiding critical bottlenecks 
such as implied or dedicated registers. 

CPU resources include sixteen 16-bit general-purpose 
registers, seven data types that range from bits to 32-bit long 
words and byte and word strings, and eight user-selectable 
addressing modes. The 1 10 distinct instruction types can 
be combined with the various data types and addressing 
modes to form a powerful set of 414 instructions. Moreover, 
the instruction set is regular; most instructions can use any 
of the five main addressing modes and can operate on byte, 
word, and long-word data types. 

The CPU can operate in either the system or normal mode. 
The distinction between these two modes permits privileged 
operations, thereby improving operating system 
organization and implementation. Multiprogramming is 
supported by the "atomic" Test and Set instruction; 
multiprocessing by a combination of instruction and 



BUS 
TIMING 



STATUS< 



CPU 
CONTROL 



BUS J 
CONTROL \ 



MULTI-MICRO 
CONTROL 



/ Ml 

| — iio 



65 

SlRETS 

BEAD/WRITE 

NORMAL/SYSTEM 

BYTE/WORD 

ST, 
ST, 
ST, 
ST 



Z8001 
Z8002 



WATT 
STOP 



8USRE0 
8USACK 



NMi 

VI 



+5V GND CLK 



AOis 
AD.. 
AD„ 

AD, : 
AD„ 
AD,o 
AD, 
AD, 
AD, 
AD, 



AD, 
AD, 
AD, 
ADo 

SN, 
SN, 
SN, 
SN, 
SN, 
SN, 
SN. 

SEGT 



TTi r 



28001 - 1 

ONLY 



.J 



128 



hardware features; and compilers by multiple stacks, 
special instructions, and addressing modes. 

The Z8000 CPU is offered in three versions: the Z8001/ 
Z160 segmented CPUs and the Z8002 nonsegmented 
CPU (Figure 1). The main difference is in addressing 
range. The Z8001 can directly address 8 megabytes of 
memory; the Z160 directly addresses 2 megabytes; the 
Z8002 directly addresses 64 kilobytes. The two operating 
modes - system and normal - and the distinction between 
code, data, and stack spaces within each mode allows 
memory extension up to 48 megabytes for the Z8001 , 1 2 
megabytes for the Zf 60 and 384 kilobytes for the Z8002. 



To meet the requirements of complex, memory-intensive 
applications, a companion memory-management device is 
offered for the Z8001. The Z8010 Memory Management 
Unit manages the large address space by providing fea- 
tures such as segment relocation and memory protection. 
The Z8001 can be used with or without the Z8010. If used 
by itself, the Z8001 still provides an 8 megabyte direct ad- 
dressing range, extendable to 48 megabytes. 

The Z8001 , Z8002 and Z80 1 are fabricated with high-den- 
sity, high-performance scaled n-channel silicon-gate 
depletion-load technology, and are housed in dual-in-line 
packages (DIPs) and leadless chip carriers (LCC). 



REGISTER ORGANIZATION 

The Z8000 CPU is a register-oriented machine that offers 
sixteen 1 6-bit general-purpose registers and a set of special 
system registers. All general-purpose registers can be used 
as accumulators and all but one as index registers or 
memory pointers. 

Register flexibility is created by grouping and overlapping 



multiple registers (Figures 2 and 3). For byte operations, the 
first eight 16-bit registers (RO... R7) are treated as sixteen 
8-bit registers (RLO. RHO..., RL7, RH7). The sixteen 16-bit 
registers are grouped in pairs (RRO... RR14) to form 32-bit 
long-word registers. Similarly, the register set is grouped in 
quadruples (RQO... RQ12) to form 64-bit registers. 



| R1 \l 



RSI 

R6 I 



Rr[ 



|r"( 



B 1T [~ 

R14 CZ 

his I - 



SYSTEM STACK POINTER |SEG WO.) 
NORMAL STACK POINTER (SEG. NO.) 



SYSTEM STACK POINTER (OFFSET) 



NORMAL STACK POINTER (OFFSET) 



P 



P 



Figure 2. Z8001 General-Purpose Registers 



(ROE 
I R1 pF 



R6L 
R7f 



6 Pis" 



R9|_ 
R10Q 
R11 Q 
R12Q 
R13Q 

R14| 

R15' 
R1S I 



SYSTEM STACK POINTER 



NORMAL STACK POINTER 



3 



P 



Figure 3. Z8002 General-Purpose Registers 



129 



anywhere in memory. Call and Return instructions as well as 
interrupts and traps use implied stacks. The distinction 
between normal and system stacks separates system 
information from the application program information. Two 
stack pointers are available: the system stack pointer and 
the normal stack pointer. Because they are part of the 
general-purpose register group, the user can manipulate the 



operations. 

In the Z8001, register pair RR14 is the implied stack 
pointer. Register R14 contains the 7-bit segment number 
and R15 contains the 16-bit offset. In the Z8002, register 
R15 is the implied 16-bit stack pointer. 



REFRESH 



The Z8000 CPU contains a counter that can be used to 
automatically refresh dynamic memory. The refresh counter 
register consists of a 9-bit row counter, a 6-bit rate counter, 
and an enable bit (Figure 4). The 9-bit row counter can 
address up to 256 rows and is incremented by two each 
time the rate counter reaches end-of-count. The rate counter 
determines the time between successive refreshes. It 
consists of a programmable 6-bit modulo-n prescaler (n = 1 
to 64), driven at one-fourth the CPU clock rate. The refresh 



period can be programmed by 1 to 64 ^is with a 4 MHz 
clock. Refresh can be disabled by programming the refresh 
enable/disable bit. 



HATE 

J I I I L 



i i i i i i i i 



Figure 4. Refresh Counter 



PROGRAM STATUS INFORMATION 



This group of status registers contains the program counter, 
flags, and control bits. When an interrupt or trap occurs, the 
entire group is saved and a new program status group is 
loaded. 

Figure 5 illustrates how the program status groups of the 
Z8001 and Z8002 differ. In the nonsegmented Z8002, the 
program status group consists of two words: the program 
counter (PC), and the flag and control word (FCW). In the 
segmented Z8001 , the program status group consists of 



four words : a two-word program counter, the flag and con- 
trol word, and an unused word reserved for future use. 
Seven bits of the first PC word designate one of the 1 28 
memory segments. The second word supplies the 16-bit 
offset that designates a memory location within the seg- 
ment. 

With the exception of the segment enable bit in the Z8001 
program status group, the flags and control bits are the 
same for both CPUs. 



ISEG &n epa 



SEGMENT NUMBER 
-I I l_L_ 



| I FLAG AND 

H O CONTROL 
I 1 I | WORD 



SEGMENT OFFSET 

J I I I I 1 I I I I I I I— 

Z8001 Program Status Registers 



Sin EPA VIE 



ADDRESS 

J 1 1 1 1 1 I I I I I 'I'l 

28002 Program Status Registers 



1FLAG AND 
CONTROL 
| WORD 



j i i i_ 



j i \ i i_ 



Z8002 Program Status Area Pointer 



Z8001 Program Status Area Pointer 

Figure 5. Z8000 CPU Special Registers 



130 



INTERRUPT AND TRAP STRUCTURE 



The Z8000 provides a very flexible and powerful interrupt 
and trap structure. Interrupts are external asynchronous 
events requiring CPU attention, and are generally triggered 
by peripherals needing service. Traps are synchronous 
events resulting from the execution of certain instructions. 
Both are processed in a similar manner by the CPU. 

The CPU supports three types of interrupts (non-maskable, 
vectored, and non-vectored) and four traps [system call, 
Extended Process Architecture (EPA) instruction, privileged 
instructions, and segmentation trap]. The vectored and 
non-vectored interrupts are maskable. Of the four traps, the 
only external one is the segmentation trap, which is 
generated by the Z8010. 

The remaining traps occur when instructions limited to the 
system mode are used in the normal mode, or as a result of 
the System Call instruction, or for an EPA instruction. The 



DATA TYPES 

Z8000 instructions can operate on bits, BCD digits (4 bits), 
bytes (8 bits), words (1 6 bits), long words (32 bits), and byte 
strings and word strings (up to 64 kilobytes long). Bits can be 
set, reset, and tested; digits are used in BCD arithmetic 
operations; bytes are used for characters or small integer 
values; words are used for integer values, instructions and 
nonsegmented addresses; long words are used for long 
integer values and segmented addresses. All data elements 



SEGMENTATION AND MEMORY 
MANAGEMENT 

High-level languages, sophisticated operating systems, 
large programs and data bases, and decreasing memory 
prices are all accelerating the trend toward larger memory 
requirements in microcomputer systems. The Z8001 meets 
this requirement with an eight megabyte addressing space. 
This large address space is directly accessed by the CPU 
using a segmented addressing scheme and can be 
managed by theZ8010 Memory Management Unit. 

Segmented Addressing 

A segmented addressing space — compared with linear 
addressing— is closer to the way a programmer uses 
memory because each procedure and data space resides 
in its own segment. The 8 megabytes of Z8001 addressing 
space is divided into 128 relocatable segments up to 64 
kilobytes each. A 23-bit segmented address uses a 7-bit 
segment address to point to the segment, and a 1 6-bit offset 
to address any location relative to the beginning of the 
segment. The two parts of the segmented address may be 
manipulated separately. The segmented Z8001 can run any 
code written for the nonsegmented Z8002 in any one of its 
128 segments, provided it is set to the nonsegmented 
mode. 



descending order of priority for traps and interrupts is: 
internal traps, nonmaskable interrupt, segmentation trap, 
vectored interrupt, and non-vectored interrupt. 

When an interrupt or trap occurs, the current program status 
is automatically pushed on the system stack. The program 
status consists of the processor status (PC and FCW) plus a 
16-bit identifier. The identifier contains the reason or source 
of the trap or interrupt. For internal traps, the identifier is the 
first word of the trapped instruction. For external traps or 
interrupts, the identifier is the vector on the data bus read by 
the CPU during the interrupt-acknowledge or trap- 
acknowledge cycle. 

After saving the current program status, the new program 
status is automatically loaded from the program status area 
in system memory. This area is designated by the program 
status area pointer (PSAP). 



except strings can reside either in registers or memory. 
Strings are stored in memory only. 

The basic data element is the byte. The number of bytes 
used when manipulating a data element is either implied by 
the operation or— for strings and multiple register 
operations— explicitly specified in the instruction. 




BASE 
ADDRESS 
REGISTER 

FILE 




23 8 Hr Q 

*A 24-BIT PHYSICAL ADDRESS |-4 

Figure 6. Logical-to-Physical Address 
Translation 



131 



In hardware, segmented addresses are contained in a 
register pair or long-word memory location. The segment 
number and offset can be manipulated separately or 
together by all the available word and long-word operations. 

When contained in an instruction, a segmented address has 
two different representations: long offset and short offset. 
The long offset occupies two words, whereas the short offset 
requires only one and combines in one word the 7-bit 
segment number with an 8-bit offset (range 0-256). The 
short offset mode allows very dense encoding of addresses 
and minimizes the need for long addresses required by 
direct accessing of this large address space. 

Memory Management 

The addresses manipulated by the programmer, used by 
instructions and output by the Z8001, are called logical 
addresses. The Memory Management Unit takes the logical 
addresses and transforms them into the physical addresses 
required for accessing the memory (Figure 6). This address 
transformation process is called relocation. Segment 
relocation makes user software addresses independent of 
the physical memory so the user is freed from specifying 



where information is actually located in the physical 
memory. 

The relocation process is transparent to user software. A 
translation table in the Memory Management Unit 
associates the 7-bit segment number with the base address 
of the physical memory segment. The 1 6-bit offset is added 
to the physical base address to obtain the actual physical 
address. The system may dynamically reload translation 
tables as tasks are created, suspended, or changed. 

In addition to supporting dynamic segment relocation, the 
Memory Management Unit also provides segment 
protection and other segment management features. The 
protection features prevent illegal uses of segments, such as 
writing into a write-protected zone. 

Each Memory Management Unit stores 64 segment entries 
that consist of the segment base address, its attributes, size, 
and status. Segments are variable in size from 256 bytes to 
64 kilobytes in increments of 256 bytes. Pairs of 
Management Units support the 128 segment numbers 
available for each of the six CPU address spaces. Within an 
address space, several Management Units can be used to 
create multiple translation tables. 



EXTENDED PROCESSING ARCHITECTURE 



TheZilog Extended Processing Architecture (EPA) provides 
an extremely flexible and modular approach to expanding 
both the hardware and software capabilities of the Z8000 
CPU. Features of the EPA include: 

■ Specialized instructions for external processors or 
software traps may be added to CPU instruction set. 

■ Increases throughput of the system by using up to four 
specialized external processors in parallel with the CPU. 

■ Permits modular design of Z8000-based systems. 

■ Provides easy management of multiple microprocessor 
configurations via "single instruction stream" 
communication. 

■ Simple interconnection between extended processing 
units and Z8000 CPU requires no additional external 
supporting logic. 

■ Supports debugging of suspect hardware against 
proven software. 

■ Standard features on all Zilog Z8000 CPUs. 
Specific benefits include: 

■ EPUs can be added as the system grows and as EPUs 
with specialized functions are developed. 

■ Control of EPUs is accomplished via a "single instruction 
stream" in the Z8000 CPU, eliminating many significant 
system software and bus contention management 
obstacles that occur in other multiprocessor (e.g., 
master-slave) organization schemes. 



The processing power of the Zilog Z8000 16-bit 
microprocessor can be boosted beyond its intrinsic 
capability by Extended Processing Architecture. Simply 
stated, EPA allows the Z8000 CPU to accommodate up to 
four Extended Processing Units (EPUs), which perform 
specialized functions in parallel with the CPU's main 
instruction execution stream (Figure 7). 

The use of extended processors to boost the main CPU's 
performance capability has been proven with large 
mainframe computers and minicomputers. In these 
systems, specialized functions such as array processing, 
special input/output processing, and data communications 
processing are typically assigned to extended processor 
hardware. These extended processors are complex 
computers in their own right. 

The Zilog Extended Processing Architecture combines the 
best concepts of these proven performance boosters with 
the latest in high-density MOS integrated-circuit design. The 
result is an elegant expansion of design capability— a 
powerful microprocessor architecture capable of 
connecting single-chip EPUs that permits very effective 
parallel processing and makes for a smoothly integrated 
instruction stream from the Z8000 programmer's point of 
view. A typical addition to the current Z8000 instruction set is 
a set of Floating Point Instructions. 

The Extended Processing Units connect directly to the 
Z8000 Bus (Z-BUS) and continuously monitor the CPU 
instruction stream. When an extended instruction is 
detected, the appropriate EPU responds, obtaining or 



placing data or status information on the Z-BUS using the 
Z8000-generated control signals and performing its 
function as directed. 

The Z8000 CPU is responsible for instructing the EPU and 
delivering operands and data to it. The EPU recognizes 
instructions intended for it and executes them, using data 
supplied with the instruction and/or data within its internal 
registers. There are four classes of EPU instructions: 

■ Data transfers between main memory and EPU registers 

■ Data transfers between CPU registers and EPU registers 

■ EPU internal operations 

■ Status transfers between the EPUs and the Z8000 CPU 
Flag and Control Word register (FCW) 

Four Z8000 addressing modes may be utilized with 
transfers between EPU registers and the CPU and main 
memory: 

■ Register 

■ Indirect Register 

■ Direct Address 

■ Index 

In addition to the hardware-implemented capabilities of the 
Extended Processing Architecture, there is an extended 
instruction trap mechanism to permit software simulation of 
EPU functions. A control bit in the Z8000 FCW register 
indicates whether actual EPUs are present or not. If not, 
when an extended instruction is detected, the Z8000 traps 
on the instruction, so that a software "trap handler" can 
emulate the desired EPU function— a very useful 



development tool. The EPA software trap routine supports 
the debugging of suspect hardware against proven 
software. This feature will increase in significance as 
designers become familiar with the EPA capability of the 
Z8000 CPU. 

This software trap mechanism facilitates the design of 
systems for later addition of EPUs: initially, the extended 
function is executed as a trap subroutine; when the EPU is 
finally attached, the trap subroutine is eliminated and the 
EPA control bit is set. Application software is unaware of the 
change. 

Extended Processing Architecture also offers protection 
against extended instruction overlapping. Each EPU 
connects to the Z8000 CPU via the STOP line so that if an 
EPU is requested to perform a second extended instruction 
function before it has completed the previous one, it can put 
the CPU into the Stop/Refresh state until execution of the 
previous extended instruction is complete. 

EPA and CPU instruction execution are shown in Figure 8. 
The CPU begins operation by fetching an instruction and 
determining whether it is a CPU or an EPU command. The 
EPU meanwhile monitors the Z-BUS for its own instructions. 
If the CPU encounters an EPU command, it checks to see 
whether an EPU is present; if not, the EPU may be simulated 
by an EPU instruction trap software routine; if an EPU is 
present, the necessary data and/or address is placed on the 
Z-BUS. If the EPU is free when the instruction and data for it 
appear, the extended instruction is executed. If the EPU is 
still processing a previous instruction, it activates the CPU's 
STOP line to lock the CPU off at the Z-BUS until execution is 
complete. After the instruction is finished, the EPU 
deactivates the STOP line and CPU transactions continue. 



1 



DEDICATED 
EPU 
MEMORY 



"hJ 



DEDICATED 
EPU 
MEMORY 



E 



Z-BUS COMPONENT INTERFACE 





r- ^ 










r= 






PERIPHERAL 




PERIPHERAL 




MEMC 
MANAGE 
UNI 


RY 

MENT 

r 

T- 





2i 



MEMORY 



Figure 7. Typical Extended Processor Configuration 



133 




A DATA OR ADDRESSES ARE PLACED ON THE BUS AND USED BY THE EPU IN THE 
EXECUTION OF AN INSTRUCTION. 



Figure 8. EPA and Z8000 CPU Instruction Execution 



INPUT/OUTPUT 

A set of I/O instructions performs 8-bit or 1 6-bit transfers 
between the CPU and I/O devices. I/O devices are 
addressed with a 16-bit I/O port address. The I/O port 
address is similar to a memory address; however, I/O 
address space need not be part of the memory address 
space. I/O port and memory addresses coexist on the same 
bus lines and they are distinguished by the status outputs. 



Two types of I/O instructions are available: standard and 
special. Each has its own address space. The I/O 
instructions include a comprehensive set of In, Out, and 
Block I/O instructions for both bytes and words. Special I/O 
instructions are used for loading and unloading the Memory 
Management Unit. The status information distinguishes 
between standard and special I/O references. 



MULTI-MICROPROCESSOR SUPPORT 

Multi-microprocessor systems are supported in hardware 
and software. A pair of CPU pins is used in conjunction with 
certain instructions to coordinate multiple microprocessors. 
The Multi-Micro Out pin issues a request for the resource, 
while the Multi-Micro In pin is used to recognize the state of 
the resource. Thus, any CPU in a multiple microprocessor 
system can exclude all other asynchronous CPUs from a 
critical shared resource. 



Multi-microprocessor systems are supported in software by 
the instructions Multi-Micro Request, Test Multi-Micro In, Set 
Multi-Micro Out, and Reset Multi-Micro Out. In addition, the 
eight megabyte CPU address space is beneficial in multiple 
microprocessor systems that have large memory 
requirements. 



134 



ADDRESSING MODES 



The information included in Z8000 instructions consists of 
the function to be performed, the type and size of data 
elements to be manipulated, and the location of the data 
elements. Locations are designated by register addresses, 
memory addresses, or I/O addresses. The addressing 
mode of a given instruction defines the address space it 
references and the method used to compute the address 
itself. Addressing modes are explicitly specified or implied 
by the instruction. 



Figure 9 illustrates the eight addressing modes: Register 
(R), Immediate (IM), Indirect Register (IR), Direct Address 
(DA), Index (X), Relative Address (RA), Base Address (BA), 
and Base Index (BX). In general, an addressing mode 
explicitly specifies either register address space or memory 
address space. Program memory address space and I/O 
address space are usually implied by the instruction. 



Addressing Mode 



Operand Addressing 



Operand Value 



R 



Register 



In the Instruction In a Register 



In Memory 



| REGISTER ADDRESS | »• [ OPERAND^ 



The content oi the 
register 



IN 



Immediate 1 0PERAND 1 



In the instruction 



^Indirect | register address | — * \ address~"| - 



» | operand""] 



The content of the location 
whose address is in the 
register 



DA 



Direct 
Address 



*-| operand I 



The content of the location 
whose address is in the 
instruction 



Index 



REGISTER ADDRESS 



BASE ADDRESS 



■6— c 



The content of the loca- 
tion whose address is the 
address in the instruction 
plus the content of the 
working register. 



RA 



Relative 
Address 



DISPLACEMENT 



OPERAND | 



The content oi the location 
whose address is the 
content of the program 
counter, offset by the 
displacement in the 
instruction 



* BA 



Base 
Address 



REGISTER ADDRESS 



DISPLACEMENT 



BASE ADDRESS 



The content of the location 
whose address is the 
address in the register, 
offset by the displacement 
in the instruction 



BX 



Index 



REGISTER ADDRESS 



REGISTER ADDRESS 



BASE ADDRESS 



The content of the loca- 
tion whose address is 
the address in a register 
plus the index value in 
another register. 



*Do not use RO or RRO as indirect, index, or base registers. 

Figure 9. Addressing Modes 



135 



INSTRUCTION SET SUMMARY 

The Z8000 provides the following types of instructions: 

■ Load and Exchange 

■ Arithmetic 

■ Logical 

■ Program Control 



LOAD AND EXCHANGE 



Bit Manipulation 
Rotate and Shift 

Block Transfer and String Manipulation 

Input/Output 

CPU Control 



Clock Cycles* 







Addr. 


Word, Byte 




Long Word 




Mnemonics 


Operands 


Modes 


NS 


SS 


SL 


NS SS SL 


Operation 


CLR 


dst 


R 


7 


7 


7 




Clear 


CLRB 




IR 


8 


8 


8 




dst-0 






DA 


11 


12 


14 










X 


12 


12 


15 






EX 


R, src 


R 


6 


6 


6 




Exchange 


EXB 




IR 


12 


12 


12 




R**src 






DA 


15 


16 


18 










X 


16 


16 


19 







LO 


R, src 


R 


3 


3 


3 


5 


5 


5 


Load into Register 


LDB 




IM 


7 


7 


7 


11 


11 


11 


R — src 


LDL 




IM 


5 (byte only) 
















IR 


7 


7 


7 


11 


11 


11 








DA 


9 


10 


12 


12 


13 


15 








X 


10 


10 


13 


13 


13 


16 








BA 


14 


14 


14 


17 


17 


17 








BX 


14 


14 


14 


17 


17 


17 




LD 


dst, R 


IR 


8 


8 


8 


11 


11 


11 


Load into Memory (Store) 


LDB 




DA 


11 


12 


14 


14 


15 


17 


dst^R 


LDL 




X 


12 


12 


15 


15 


15 


18 








BA 


14 


14 


14 


17 


17 


17 








BX 


14 


14 


14 


17 


17 


11 





LD 


dst, IM 


IR 


11 


11 


11 


Load Immediate into Memory 


LDB 




DA 


14 


15 


17 


dst - IM 






X 


15 


15 


18 




LDA 


R, src 


DA 


12 


13 


15 


Load Address 






X 


13 


13 


16 


R *- source address 






BA 


15 


15 


15 








BX 


15 


15 


15 




LDAR 


R, src 


RA 


15 


15 


15 


Load Address Relative 














R — source address 


LDK 


R, src 


IM 


5 


5 


5 


Load Constant 














R-n(n = 0... 15) 


LDM 


R, src, n 


IR 


11 


11 


11 + 3n 


Load Multiple 






DA 


14 


15 


17 + 3n 


R — src (n consecutive words) 






X 


15 


15 


18 + 3n 


(n = 1... 16) 


'NS = Non-segmented 


SS - 


Segmented Short Offset 


SL = 


Segmented Long Offset 





136 



LOAD AND EXCHANGE (Continued) 



Clock Cycles* 
Addr. Word, Byte Long Word 



Mnemonics 


Operands 


Modes 


NS 


ss 


SL NS 


SS 


SL 


Operation 


LUM 


dst, R, n 


IR 
In 


1 1 


1 1 


1 1 T OH 






LU0U multiple ^OlUI C IVI Ul ll 






DA 


14 


15 


17 + 3n 






dst — R (n consecutive words) 






X 


15 


15 


18 + 3n 






(n = 1... 16) 


LUK 


R, src 


nA 


1 A 
I H 


1 A 


■\A 17 


1 7 
I f 


1 7 
I f 


1 nari Ralatiuo 


LDRB 
















R *~ src 


LDRL 
















(range -32768... +32767) 


i no 


QSl, n 


DA 

nrt 


1 A 
t H 


1 A 
I *-f 


1 A 17 
If if 


1 7 
1 f 


1 7 
I / 




i noQ 
















(jbi n 


i not 
















grange — j£/oo... -r*j*i/o(} 


POP 


dst, IR 


R 


8 


8 


8 12 


12 


12 


Pop 


POPL 




IR 


12 


12 


12 19 


19 


19 


dst^lR 






DA 


16 


16 


18 23 


23 


25 


Autoincrement contents ot R 






X 


16 


16 


19 23 


23 


26 




PUSH 


IR, src 


R 


9 


9 


9 12 


12 


12 


Push 


PUSHL 




IM 


12 


12 


12 19 


19 


19 


Autodecrement contents of R 






IR 


13 


13 


13 20 


20 


20 


IR — src 






DA 


14 


14 


16 21 


21 


23 








X 


14 


14 


17 21 


21 


24 




ARITHMETIC 


ADC 


R, src 


R 


5 


5 


5 






Add with Carry 


ADCB 
















R *- R + src + carry 


ADD 


R, src 


R 


4 


4 


4 8 


8 


8 


Add 


ADDB 




IM 


7 


7 


7 14 


14 


14 


R — R + src 


ADDL 




IR 


7 


7 


7 14 


14 


14 








DA 


9 


10 


12 15 


16 


18 








X 


10 


10 


13 16 


16 


19 




CP 


R, src 


R 


4 


4 


4 8 


8 


8 


Compare with Register 


CPB 




IM 


7 


7 


7 14 


14 


14 


R - src 


CPL 




IR 


7 


7 


7 14 


14 


14 








DA 


9 


10 


12 15 


16 


18 








X 


10 


10 


13 16 


16 


19 




CP 


dst, IM 


IR 


11 


11 


11 






Compare with Immediate 


CPB 




DA 


14 


15 


17 






dst - IM 






X 


15 


15 


18 








DAB 


dst 


R 


5 


5 


5 






Decimal Adjust 


DEC 


dst, n 


R 


4 


4 


4 






Decremented by n 


DECB 




IR 


11 


11 


11 






dst — dst - n 






DA 


13 


14 


16 






(n = 1... 16) 






X 


14 


14 


17 









"NS = Non-segmented SS = Segmented Short Offset SL = Segmented Long Offset 



137 



ARITHMETIC (Continued) 



Clock Cycles* 
Addr. Word, Byte Long Word 



Mnemonics Operands 


Modes 


NS 


SS 


SL 


NS 


SS 


SL 


Operation 


niV R err 


p 


I U/ 






744 


744 


744 


LHVIUC ^lyimuj 


DIVL 


IM 


107 


107 


107 


744 


744 


744 


Word: R n j. 1 *~ Rn n 1 + src 

• TWIW. I | '11,11+ | 




IR 


107 


107 


107 


744 


744 


744 


R n *~ remainder 




DA 


108 


109 


111 


745 


746 


748 


Lonq Word: R n + o n + T*~Rn n +. ^ + src 




X 


109 


109 


112 


746 


746 


749 


R n.n + 2"~ remainder 


EXTS dst 


R 


11 


11 


11 


11 


11 


11 


Extend Sign 


EXTSB 
















Fxtpnrl ^inn nf Inw nrdpr half nf rtat 


EXTSL 
















through high order half of dst 


INC dst, n 


R 


4 


4 


4 








Increment by n 


INCH 


in 

In 


1 1 


1 1 


1 1 








dst *- dst + n 




DA 


13 


14 


16 








{n = 1... 16) 




X 


14 


14 


17 










MULT R, src 


R 


70 


70 


70 


282t 


282t 


282t 


Multiply (signed) 


MULTL 


IM 


70 


70 


70 


282~f 


282t 


282t 


Word:R nin + i — R n + 1 • src 




IR 


70 


70 


70 


282t 


282t 


282t 


Lona Word' R n n4.^*"RnA9nj.i 




DA 


71 


72 


74 


283t 


284t 


286t 


tPluS seven cycles for each 1 in the 




X 


72 


72 


75 


284t 


284t 


287t 


multiplicand 


NEG dst 


R 


7 


7 


7 








Negate 


NEGB 


IR 


12 


12 


12 








dst — - dst 




DA 


15 


16 


18 












X 


16 


16 


19 










SBC R, src 


R 


5 


5 


5 








Subtract with Carry 


SBCB 
















R — R - src - carry 


SUB R. src 


R 


4 


4 


4 


8 


8 


8 


Subtract 


SUBB 


IM 


7 


7 


7 


14 


14 


14 


R «- R - src 


SUBL 


IR 


7 


7 


7 


14 


14 


14 






DA 


9 


10 


12 


15 


16 


18 






X 


10 


10 


13 


16 


16 


19 




LOGICAL 


AND R, src 


R 


4 


4 


4 








AND 


ANDB 


IM 


7 


7 


7 








R — RAND src 




IR 


7 


7 


7 












DA 


9 


10 


12 












X 


10 


10 


13 










COM dst 


R 


7 


7 


7 








Complement 


COMB 


IR 


12 


12 


12 








dst - NOT dst 




DA 


15 


16 


18 












X 


16 


16 


19 










OR R, src 


R 


4 


4 


4 








OR 


ORB 


IM 


7 


7 


7 








R — R OR src 




IR 


7 


7 


7 












DA 


9 


10 


12 












X 


10 


10 


13 










*NS = Non-segmented SS = Segmented Short Offset 


SL = 


Segmented Long Offset 







138 




LOGICAL (Continued) 



Clock Cycles' 
Addr. Word, Byte Long Word 



Mnemonics Operands 


Modes 


NS 


SS 


SL 


NS 


SS 


SL 


Operation 


TCC "~ cc, dst 


R 


5 


5 


5 








Test Condition Code 


TCCB 
















Spt I SR it rr is tri ip 

L l_OLJ II OL> lo LI UC 


TEST dst 


R 


7 


7 


7 


13 


13 


13 


Test 


TESTB 


IR 


8 


8 


8 


13 


13 


13 


dst OR 


TESTL 


DA 


11 


12 


14 


16 


17 


19 






X 


12 


12 


15 


17 


17 


20 




XOR R, src 


R 


4 


4 


4 








Exclusive OR 


XORB 


IM 


7 


7 


7 








R — R XOR src 




IR 


7 


7 


7 












DA 


9 


10 


12 












X 


10 


10 


13 










PROGRAM CONTROL 


CALL dst 


IR 


10 


15 


15 








Call Subroutine 




DA 


12 


18 


20 








Autodecrement SP 




A 


1 9 
i o 


1 ft 

I o 


£ I 








OD »- Dp 

tgj or 


















PC *■ dst 


CALR dst 


RA 


10 


10 


15 








Call Relative 


















Autodecrement SP 


















@ SP — PC 


















PC-PC + dst (range -4094 to +4096) 


DJNZ R, dst 


RA 


11 


11 


11 








Decrement and Jump if Non-Zero 


DBJNZ 
















R-R - 1 


















If R # 0: PC-PC + dst(range - 254 to 9) 


IRETt - 




13 


13 


16 








Interrupt Return 


















PS — @ SP 


















Autoincrement SP 


JP cc, dst 


IR 


10 


10 


15 




(taken) 




Jump Conditional 




IR 


7 


7 


7 




(not taken) 




If cc is true: PC — dst 




DA 


7 


8 


10 












X 


8 


8 


11 










JR cc, dst 


RA 


6 


6 


6 








Jump Conditional Relative 


















If cc is true: PC — PC + dst 


















(range - 256 to + 254) 


RET cc 




10 


10 


13 




(taken) 




Return Conditional 






7 


7 


7 




(not taken) 




If cc is true: PC — @ SP 


















Autoincrement SP 


SC src 


IM 


33 


33 


39 








System Call 



Autodecrement SP 
@ SP - old PS 
Push instruction 
PS — System Call PS 



• NS = Non-segmented SS = Segmented Short Offset SL = Segmented Long Offset 
tPrivileged instruction. Executed in system mode only. 



139 



BIT MANIPULATION 



Clock Cycles* 
Addr. Word, Byte Long Word 



Mnemonics 


Operands 


Modes 


NS 


SS 


SL 


NS SS SL 


Operation 


BIT 


dst, b 


R 


4 


4 


4 




Test Bit Static 


BITB 




IR 


8 


8 


8 




Z flag — NOT dst bit specified by b 






DA 


10 


11 


13 










X 


11 


11 


14 






BIT 


dst, R 


R 


10 


10 


10 




Test Bit Dynamic 


BITB 














Z flag — NOT dst bif specified by 
















contents of R 


RES 


dst, b 


R 


4 


4 


4 




Reset Bit Static 


RESB 




IR 


11 


11 


11 




Reset dst bit specified by b 






DA 


13 


14 


16 










X 


14 


14 


17 






RES 


dst, R 


R 


10 


10 


10 




Reset Bit Dynamic 


RESB 














Reset dst bit specified by contents R 


SET 


dst, b 


R 


4 


4 


4 




Set Bit Static 


SETB 




IR 


11 


11 


11 




Set dst bit specified by b 






DA 


13 


14 


16 










X 


14 


14 


17 






SET 


dst, R 


R 


10 


10 


10 




Set Bit Dynamic 


SETB 














Set dst bit specified by contents of R 


TSET 


dst 


R 


7 


7 


7 




Test and Set 


TSETB 




IR 


11 


11 


11 




S flag - MSB of dst 






DA 


14 


15 


17 




dst -all 1s 






X 


15 


15 


18 






ROTATE AND SHIFT 


RL 


dst, n 


R 




6 for n = 1 






Rotate Left 


RLB 




R 




7forn = 2 






by n bits (n = 1,2) 


RLC 


dst, n 


R 




6 for n = 1 






Rotate Left through Carry 


RLCB 




R 




7forn = 2 






by n bits (n = 1,2) 


RLDB 


R, src 


R 


9 


9 


9 




Rotate Digit Left 


RR 


dst, n 


R 




6 for n = 1 






Rotate Right 


RRB 




R 




7forn = 2 






by n bits (n = 1,2) 


RRC 


dst, n 


R 




6 for n = 1 






Rotate Right through Carry 


RRCB 




R 




7 for n = 2 






by n bits (n = 1,2) 


RRDB 


R, src 


R 


9 


9 


9 




Rotate Digit Right 


SDA 


dst, R 


R 




(15 + 3n) 




(15 + 3n) 


Shift Dynamic Arithmetic 


SDAB 














Shift dst left or right by 


SDAL 














contents of R 


SDL 


dst, R 


R 




(15 + 3n) 




(15 + 3n) 


Shift Dynamic Logical 



SDLB Shift dst left or right by 

SDLL contents of R 

"NS = Non-segmented SS = Segmented Short Offset SL = Segmented Long Offset 



140 



ROTATE AND SHIFT (Continued) 



Mnemonics 


Clock Cycles* 
Addr. Word, Byte Long Word 
Operands Modes NS SS SL NS SS SL 


Operation 


Ql A 
OLA 

SLAB 
SLAL 


dst, n H ( 1 3 + J n) 


(13 + 3 n) 


CKift Lpft Arithmetic 

by n bits 


CI 1 

SLL 

SLLB 

SLLL 


dst, n R (13 + 3 n) 


(13 + 3 n) 


Qhift 1 aft 1 rtnir-al 

onin Len Logical 

by n bits 


CD A 

SRAB 
SRAL 


dst, n R (13 + 3n) 


(13 + 3n) 


onin riigni Ariinmeiic 

by n bits 


SRL 

SRLB 

SRLL 


dst, n R (13 + 3n) 


(13 + 3n) 


Shift Right Logical 

by n bits 


BLOCK TRANSFER AND STRING MANIPULATION 


CPD 
CPDB 


R x ,src.RyCC IR 20 20 20 




Compare and Decrement 

Rx - src 

Autodecrement src address 
Ry — Ry - 1 


CPDR 
CPDRB 


R x ,src,Ry,cc IR (11 + 9n) 




Compare, Decrement, and Repeat 

R x - src 

Autodecrement src address 
Ry — Ry - 1 

Repeat until cc is true or Ry = 


CPI 
CPIB 


R x ,src,Ry,cc IR 20 20 20 




Compare and Increment 

Rx - src 

Autoincrement src address 
Ry — Ry - 1 


CPIR 
CPIRB 


R Xl src,R Y ,cc IR (11 + 9n) 




Compare, Increment, and Repeat 

R x - src 

Autoincrement src address 

Ry — Ry - 1 

Repeat until cc is true or Ry = 


CPSD 
CPSDB 


dst,src,R,cc IR 25 25 25 




Compare String and Decrement 

dst - src 

Autodecrement dst and src addresses 
R-R - 1 


CPSDR 
CPSDRB 


dst,src,R,cc IR (11 + 14 n) 




Compare String, Decrement, and 
Repeat 

dst - src 

Autodecrement dst and src addresses 
R-R - 1 

Repeat until cc is true or R = 


•NS = Non-segmented SS = Segmented Short Offset SL = Segmented Long Offset 



141 



Mnemonics 



oiocKoycies 
Addr. Word, Byte Long Word 

Operands Modes NS SS SL NS SS SL 



Operation 



CPSI 
CPSIB 



dst,src,R,cc IR 25 25 25 



Compare String and Increment 

dst - src 

Autoincrement dst and src addresses 
R-R - 1 



CPSIR 
CPSIRB 



dst,src,R,cc IR (11 + 14 n) 



Compare String, Increment and 
Repeat 

dst - src 

Autoincrement dst and src addresses 
R-R - 1 

Repeat until cc is true or R = 



LDD 
LDDB 



dst.src.R 



IR 



20 20 20 



Load and Decrement 

dst *- src 

Autodecrement dst and src addresses 
R-R - 1 



LDDR 
LDDRB 



dst.src.R 



IR 



(1 1 + 9 n) 



Load, Decrement and Repeat 

dst — src 

Autodecrement dst and src addresses 
R-R - 1 

t until R = 



LDI 
LDIB 



dst.src.R 



IR 



20 20 20 



Load and Increment 

dst — src 

Autoincrement dst and src addresses 
R-R - 1 



LDIR 
LDIRB 



dst.src.R 



IR 



(11 + 9n) 



Load, increment and Repeat 

dst — src 

Autoincrement dst and src addresses 
R-R - 1 
Repeat until R = 



TRDB 



dst.src.R IR 25 25 25 



Translate and Decrement 

dst — src (dst) 
Autodecrement dst address 
R-R - 1 



TRDRB 



dst.src.R IR (11 + 14n) 



Translate, Decrement and Repeat 

dst — src (dst) 
Autodecrement dst address 
R-R - 1 
Repeat until R = 



TRIB 



dst.src.R IR 25 25 25 



Translate and Increment 

dst — src (dst) 
Autoincrement dst address 
R-R - 1 



•NS = Non-segmented SS = Segmented Short Offset SL = Segmented Long Offset 
"Privileged instruction. Executed in system mode only. 



142 



BLOCK TRANSFER AND STRING MANIPULATION (Continued) 



Mnemonics 



Operands 



Clock Cycles* 
Addr. Word, Byte Long Word 

Modes NS SS SL NS SS SL 



Operation 



TRIRB 



dst.src.R IR (11 + 14 n) 



Translate, Increment and Repeat 

dst — src (dst) 
Autoincrement dst address 
R — R - 1 
Repeat until R = 



TRTDB 



src1,src2,R IR 25 25 25 



Translate and Test, Decrement 

RH1 -src2(srd) 
Autodecrement src 1 address 
R — R - 1 



TRTDRB 



src1,src2,R IR (11 + 14 n) 



Translate and Test, Decrement, and 
Repeat 

RH1 *-src2(srd) 
Autodecrement srd address 
R«-R - 1 

Repeat until R = OorRHI =0 



TRTIB 



src1,src2,R IR 25 25 25 



Translate and Test, Increment 

RH1 <-src2(srd) 
Autoincrement srd i 
R-R - 1 



TRTIRB 



src1,src2,R IR (11 + 14 n) 



Translate and Test, Increment and 
Repeat 

RH1 -src2(srd) 
Autoincrement src 1 address 
R.-R- 1 

Repeat until R = OorRHI =0 



INPUT/OUTPUT 



+- ffl 

z z 


R.src 


IR 
DA 


10 10 10 
12 12 12 


Input 

R *- src 


INDt 
INDBt 


dst.src.R 


IR 


21 21 21 


Input and Decrement 

dst — src 

Autodecrement dst address 
R-R - 1 


INDRt 
INDRBt 


dst.src.R 


IR 


(11 + 10 n) 


Input, Decrement and Repeat 

dst *- src 

Autodecrement dst address 
R-R - 1 
Repeat until R = 


INIt 


dst.src.R 


IR 


21 21 21 


Input and Increment 



INIBt dst - src 

Autoincrement dst address 
R-R - 1 

"NS = Non-segmented SS = Segmented Short Offset SL = Segmented Long Offset 
tPrivileged instruction. Executed in system mode only. 



143 



INPUT/OUTPUT (Continued) 



Clock Cycles* 
Addr. Word, Byte Long Word 



Mnemonics 


Operands 


Modes 


NS SS SL NS SS SL 


Operation 


INIRt 
INIRBt 


dst.src.R 


IR 


(11 + 10 n) 


Input, Increment and Repeat 

dst — src 

Autoincrement dst address 
R-R - 1 
Repeat until R = 


OUTt 
OUTBt 


dst,R 


IR 
DA 


10 10 10 
12 12 12 


Output 

dst-R 


OUTDt 

1 "TT I - * D t 

OUTDBT 


dst.src.R 


IR 


21 21 21 


Output and Decrement 

dst — src 

Autodecrement src address 
R-R - 1 


OTDRt 
OTDRB1 


dst,src,R 


IR 


(11 + 10 n) 


Output, Decrement and Repeat 

dst — src 

Autodecrement src address 
R-R - 1 
Repeat until R = 


OUTIt 
OUTIBt 


dst.src.R 


IR 


21 21 21 


Output and Increment 

dst *■ src 

Autoincrement src address 
R-R - 1 


OTIRt 
OTIRBt 


dst.src.R 


IR 


(11 + 10 n) 


Output, Increment, and Repeat 

dst — src 

Autoincrement src address 
R-R - 1 
Repeat until R = 


SINt 
SINBt 


R.src 


DA 


12 12 12 


Special Input 

R — src 


SINDt 
SINDB 


dst,src,R 


IR 


21 21 21 


Special Input and Decrement 

dst — src 

Autodecrement dst address 
R-R - 1 


SINDRt 


dst.src.R 


IR 


11 + 10 n) 


Special Input, Decrement, and 



SINDRBt Repeat 

dst — src 

Autodecrement dst address 
R-R - 1 
Repeat until R = 

SINIt dst.src.R IR 21 21 21 Special Input and Increment 

SINIBt dst - src 

Autoincrement dst address 
R-R - 1 

*NS = Non-segmented SS = Segmented Short Offset SL = Segmented Long Offset 
tPrivileged instruction. Executed in system mode only. 



144 



INPUT/OUTPUT (Continued) 



Mnemonics 


Operands 


Addr. 
Modes 


Clock Cycles* 
Word, Byte Long Word 
NS SS SL NS SS SL 


Operation 


SiNIRt 
SINIRBt 


dst.src.R 


IR 


(11 + 10 n) 


Special Input, Increment, and 

Repeat 
dst — src 

Autoincrement dst address 
R-R - 1 
Repeat until R = 


SOUTt 
SOUTBt 


dst.src 


DA 


12 12 12 


Special Output 

dst *- src 


SOUTDt 
SOUTDBt 


dst.src.R 


IR 


21 21 21 


Special Output and Decrement 

dst *■ src 

Autodecrement src address 
R-R - 1 


SOTDRt 
SOTDRBt 


dst.src.R 


IR 


(11 + 10 n) 


Special Output, Decrement, and 

Repeat 
dst — src 

Autodecrement src address 
R*-R- 1 
Repeat until R = 


SOUTIt 
SOUTIBt 


dst.src.R 


IR 


21 21 21 


Special Output and Increment 

dst,— src 

Autoincrement src address 
R-R - 1 


SOTIRt 
SOTIRBt 


dst.src.R 


R 


(11 + 10 n) 


Special Output, Increment, and 

Repeat 
dst — src 

Autoincrement src address 
R-R - 1 
Repeat until R = 


CPU CONTROL 


COMFLG 


flags 




7 7 7 


Complement Flag 

(Any combination of C, Z, S, PA/) 


Dlt 


int 




7 7 7 


Disable Interrupt 

(Any combination of NVI, VI) 


Elt 


tot 




7 7 7 


Enable Interrupt 

(Any combination of NVI, VI) 


HALTt 






(8 + 3 n) 


HALT 


LDCTLt 


CTLR.src 


R 


7 7 7 


Load into Control Register 

CTLR — src 


LDCTLt 


dst.CTLR 


R 


7 7 7 


Load from Control Register 

dst - CTLR 



" NS = Non-segmented SS = Segmented Short Offset SL = Segmented Long Offset 
tPrivileged instruction. Executed in system mode only. 



145 



ciock cycles 



Mnemonics 


Operands 


Addr. 
Modes 


V 

NS 


Vord, Byte 
SS 


Long Word 
SL NS SS SL 


Operation 


LDCTLB 


FLGR, src 


R 


7 


7 


7 


Load into Flag Byte Register 

FLGR *- src 


LDCTLB 


dst, FLGR 


R 


7 


7 


7 


Load from Flag Byte Register 

dst - FLGR 


LDPSt 




IR 
DA 
X 


12 
16 
17 


16 
20 
20 


16 

22 
23 


1 nari Prnnram Statue 

PS — src 


MBIT' 


— 


— 


7 


7 


7 


Test Multi-Micro Bit 

Set S if Ml is Low; reset S if Ml is High 


MREQt 


dst 


R 




(12 + n) 




Multi-Micro Request 


WIRES 1 


— 


— 


5 


5 


5 


Multi-Micro Reset 


MSETt 






5 


7 


7 


Multi-Micro Set 


NOP 






7 


7 


7 


No Operation 


RESFLG 


flag 


- 


7 


7 


7 


Reset Flag 

(Any combination of C, Z, S, P/V) 


SETFLG 


flag 




7 


7 


7 


Set Flag 

(Any combination of C, Z, S, P/V) 



•NS = Non-segmented SS = Segmented Short Offset SL = Segmented Long Offset 
tPrivileged instruction. Executed in system mode only. 



146 



19 



CONDITION CODES 



ooae 


Unnnlnn 

Meaning 


Clem CaMinnc 

Mag bettings 


rieiu 


F 


Always false 


— 


0000 


T 


Always true 


_ 


1000 


Z 


Zero 


Z = 1 


0110 


NZ 


Not zero 


Z = 


1110 


C 


Carry 


C = 1 


0111 


NC 


No Carry 


C = 


1111 


PL 


Plus 


S = 


1101 


Ml 


Minus 


S = 1 


0101 


NE 


Not equal 


Z = 


1110 


EQ 


Equal 


Z = 1 


0110 


OV 


Overflow 


P/V = 1 


0100 


NOV 


No overflow 


P/V = 


1100 


PE 


Parity is even 


P/V = 1 


0100 


PO 


Parity is odd 


P/V = 


1100 


GE 


Greater than or equal (signed) 


(S XOR P/V) = 


1001 


U 


Less than (signed) 


(S XOR P/V) = 1 


0001 


GT 


Greater than (signed) 


[Z OR (S XOR P/V)] = 


1010 


LE 


Less than or equal (signed) 


[Z OR (S XOR P/V)] = 1 


0010 


UGE 


Unsigned greater than or equal 


C = 


1111 


ULT 


Unsigned less than 


C = 1 


0111 


UGT 


Unsigned greater than 


t(C = 0) AND (Z = 0)] = 1 


1011 


ULE 


Unsigned less than or equal 


(C OR Z) = 1 


0011 



Note that some condition codes have identical flag settings and binary fields in the instruction 
Z = EQ, NZ = NE, C = ULT, NC = UGE, OV = PE, NOV = PO 



STATUS CODE LINES 



ST„-ST 3 


Definition 


0000 


Internal operation 


0001 


Memory refresh 


0010 


I/O reference 


0011 


Special I/O reference (e.g., to an MMU) 


0100 


Segment trap acknowledge 


0101 


Non-maskable interrupt acknowledge 


0110 


Non-vectored interrupt acknowledge 


0111 


Vectored interrupt acknowledge 


1000 


Data memory request 


1001 


Stack memory request 


1010 


Data memory request (EPU) 


1011 


Stack memory request (EPU) 


1100 


Program reference, nth word 


1101 


Instruction fetch, first word 


1110 


Extension processor transfer 


1111 


Reserved 



147 



PIN DESCRIPTION 



AD -AD 15 . Address/Data (inputs/outputs, active High, 
3-state). These multiplexed address and data lines are used 
for I/O and to address memory. 

AS. Address Strobe (output, active Low, 3-state), The rising 
edge of AS indicates addresses are valid. 

BUSACK. Bus Acknowledge (output active Low). A Low on 
this line indicates the CPU has relinquished control of the 
bus. 

BUSREQ. Bus Request (input, active Low). This line must 
be driven Low to request the bus from the CPU. 

B/W. ByteAVord (output, Low = Word, 3-state). This signal 
defines the type of memory reference on the 16-bit 
address/data bus. 

CLK. System Clock (input). CLK is a 5V single-phase 
time-base input. 

DS. Data Strobe (output, active Low, 3-state). This line times 
the data in and out of the CPU. 

MREQ. Memory Request (output, active Low, 3-state). A 
Low on this line indicates that the address/data bus holds a 
memory address. 

Ml, MO. Multi-Micro In, Multi-Micro Out (input and output, 
active Low). These two lines form a resource-request daisy 
chain that allows one CPU in a multi-microprocessor system 
to access a shared resource. 

NMI. Non-Maskable Interrupt (edge trig gered , input, active 
Low). A high-to-low transition on NMI requests a 









J AD. 






« 


J SN, 


AD, E 


3 


46 


3 SN S 


AD„ C 




45 


3 AD, 


AD,iC 


5 


« 


3 AD S 


AD,jC 


6 


43 


□ AD. 


STOP C 


7 


42 


3 SN, 


Mi C 


8 


41 


3ad s 


AD, S C 


9 


40 


□ AD, 


AD„ C 


10 


39 


□ ad, 


+ 5V rz 


« 


38 


□ AD, 


nvi c 


12 

28001 

13 


37 
36 


□ SN, 

□ GND 


SEGT C 


14 


35 


3 CLOCK 


NMI C 


15 


34 


□ as 


RESET Q 


16 


33 


J NC 


MOC 


17 


32 


□ B/W 


MREQ □ 


18 


31 


□ US 


BSC 


19 


30 


Jriw 


ST, C, 


20 


29 


□ BUSACK 


ST, C 


21 


28 


□ WAIT 


*!,£ 


22 


27 


□ BUSREQ 


ST, C. 


23 


26 


□ SN 


SN, C 


M 


25 


□ SN, 



Figure 10a. 48-pin Dual-ln-Line Package (DIP), 
Pin Assignments 



non-maskable interrupt. The NMI interrupt has the highest 
priority of the three types of interrupts. 

N/S. Normal/System Mode (output, Low = System Mode, 
3-state). N/S indicates the CPU is in the normal or system 
mode. 

NVI. Non-Vectored Interrupt (input, active Low). A Low on 
this line requests a non-vectored interrupt. 

RESET. Reset (input, active Low). A Low on this line resets 
the CPU. 

R/W. Read/Write (output, Low = Write, 3-state). R/W 
indicates that the CPU is reading from or writing to memory 
or I/O. 

SEGT. Segment Trap (input, active Low). The Memory 
Management Unit interrupts the CPU with a Low on this line 
when the MMU detects a segmentation trap. Input on 
Z8001 only. 

SNo-SNg. Segment Number (outputs, active High, 3-state). 
These lines provide the 7-bit segment number used to 
address one of 128 segments by the Z8010 memory 
Management Unit. Output by the Z8001 only. 

ST0-ST3. Status (outputs, active High, 3-state). These lines 
specify the CPU status (see Status Code Lines). 

STOP. Stop (input, active Low). This input can be used to 
single-step instruction execution. 

VI. Vectored Interrupt (input, active Low). A Low on this line 
requests a vectored interrupt. 

WAIT. Wait (input, active Low). This line indicates to the CPU 
that the memory or I/O device is not ready for data transfer. 



AD, C 




40 


] ADo 


AD,oC 


2 


39 


3 AD, 


AD„ [2 


3 


38 


] AD, 


AO, , C 


4 


37 


] AD, 


AD„C 




36 


J AO. 


STOP C 


6 


35 


Z\ AD, 


Ml C 




" 


Z\ AD, 


AD, S C 


8 


33 


] AD, 


AD„ C 


9 


32 


] AD, 


+ 5V [2 

wr 


10 

ZS002 

« 


31 
30 


] GND 
] CLOCK 


NWC 


12 


29 


]AS 


nmTC 


13 


28 


J NC 


ESET □ 


14 


? 


] B/W 


MO C 


15 


26 


2 N/S 


«REQ C 


16 


25 


] R/W 


DS □ 


17 


24 


2 BUSACK 


ST, Q 


18 


23 


] WATT 


ST, □ 


19 


22 


~\ BUSREQ 


ST, £ 


20 


21 





Figure 11a. 40-pin Dual-ln-Line Package (DIP), 
Pin Assignments 



148 





' 1 


STOP 


8 


Ml 


9 


AD15 


10 


AD 14 


11 


+ 5V 


ta 


NC 


13 


VI 


14 


NVl 


15 


SEGT 


16 


NMI 


17 


RESET 


18 


MO 


19 


MREQ 


20 




\ 



* gVVVV ? ? r ^ ? ? 



S 5 4 3 



52 51 50 49 48 47 



Z8001 
CPU 



SN, 
AD S 
AD 3 
AD 2 
AO, 
SNj 
GNO 
CLK 
AS 

RESERVED ABORT 

B/W 

N/S 

R/W 



22 23 24 25 26 27 28 29 30 31 32 33 



NC = No connection 

52-pin Chip Carrier, Pin Assignments 





( 6 


5 4 3 2 1 44 43 42 41 40 V 




STOP 


7 




39 


AD 5 


Ml 


8 




38 


AD 3 


AD 15 


9 




37 


ADa 


AD, 4 


10 




36 


AD, 


+ 5V 


11 




35 


GND 


NC 


12 


Z8002 
CPU 


34 


CLK 


VI 


13 


33 


AS 


NVl 


14 




32 


RESERVED 


NMI 


15 




31 


B/W 


RESET 


16 
17 




30 


N/S 


MO 




29 


R/W 






19 20 21 22 23 24 25 26 27 28 / 





Figure 11b. 

44-pin Chip Carrier, Pin Assignments 



Z8000 CPU TIMING 



The Z8000 CPU executes instructions by stepping through 
sequences of basic machine cycles, such as memory read 
or write, I/O device read or write, interrupt acknowledge, 
and internal execution. Each of these basic cycles requires 
three to ten clock cycles to execute. Instructions that require 
more clock cycles to execute are broken, up into several 
machine cycles. Thus no machine cycle is longer than ten 
clock cycles and fast response to a Bus Request is 
guaranteed. 

The instruction opcode is fetched by a normal memory read 
operation. A memory refresh cycle can be inserted just after 
the completion of any first instruction fetch (IF-|) cycle and 
can also be inserted while the following instructions are 
being executed: MULT, MULTL, DIV, DIVL, HALT, all Shift 
instructions, all Block Move instructions, and the Multi-Micro 



Request instruction (MREQ). 

The following timing diagrams show the relative timing 
relationships of all CPU signals during each of the basic 
operations. When a machine cycle requires additional clock 
cycles for CPU internal operation, one to five clock cycles 
are added. Memory and I/O read and write, as well as 
interrupt ac knowle dge cycles, can be extended by 
activating the WAIT input. For exact timing information, refer 
to the composite timing diagram. 

Note that the WAIT input is not synchronized in the Z8000 
and that the setup and hold times for WAIT, relative to the 
clock, must be met. If asynchronous WAIT signals are 
generated, they must be synchronized with the CPU clock 
before entering the Z8000. 



149 



MEMORY READ AND WRITE 



Low, a n additional clock period is added between T 2 and T 3 . 
WAIT is sampled again in the middle of this wait cycle, and 
additional wait states can be inserted: this allows interfacing 
slow memories. No control outputs change during wait 
states. 

Although Z8000 memory is word organized, memory is 
addressed as bytes. All instructions are word-aligned, using 
even addresses. Within a 16-bit word, the most significant 
byte (D8-D15) is addressed by the low-order address (Ao = 
Low), and the least significant byte (D0-D7) is addressed by 
the high-order address (A = High). 



CLOCK 


Tn 

I 1 




Ti 

\ WAIT 

SAMPLED 


^WAIT CYCLES ADDED 


DATA SAMPLED 
FOR READ 


WAIT 






X X 


















STATUS 

(B/W, NIS", 

STn-ST-,1 




X 






x_ 














SNo-SNs 


v 

A 


SEGMENT NUMBER 


— v — 

A 


















AS 




\ / 








MREQ 




V 


f— 










AO 

HEAD 




^lEMORY ADDRESS 


>- — 


( 0ATA N ) 














DS 

READ 






\ 


/ 




WW 

READ 




/ 








AD 

WRITE 




^^MEMORY ADDRESS 


X 


DATA OUT 


x_ 














DS 

WRITE 

RIW 

WRITE 




\ 


\ 


/ 


r 















Memory read and instruction fetch cycles are identical, ex- 
cept for the status information on the ST0-ST3 outputs. 
During a memory read cycle, a 16-bit address is placed on 
the AD0-AD15 outputs early in the first clock period, as 
shown in Figure 1 2. In the Z8001 , the 7-bit segment num- 
ber is output on SN0-SN6 one clock period earlier than the 
16-bit address offset. 

A valid address is indicated by the rising edge of Address 
Strobe. Status and mode information become valid early in 
the memory access cycle and remain stable throughout. 
The state of the WAIT input is sampled in the middl e of th e 
second clock cycle by the falling edge of Clock. If WAIT is 



Figure 12. Memory Read and Write Timing 



150 



INPUT/OUTPUT 



I/O timing is similar to memory read/write timing, except T 2 and T 3 (Figure 13). Both the segmented Z8001/Z8005 and 
that one wait state is automatically (T WA ) inserted between the nonsegmented Z8002 use 16-bit I/O addresses. 



_STATUS 

(BIW, STo-STj) 



IDC 



AS 



f 



V WAIT V 
SAMPLED 



XX 



*" WAIT CYCLES ADDED 



DATA SAMPLED 
FOR READ 



x: 



ZZX. 



PORT ADDRESS 



\ 



^ DATA 



/ 



c 



AD 

OUTPUT 



zzx. 



PORT ADDRESS 



X 



DS 

OUTPUT 



R/W 

OUTPUT 



\ 



X 



£Z 



Figure 13. Input/Output Timing 



151 



INTERRUPT AND SEGMENT TRAP 
REQUEST AND ACKNOWLEDGE 



The Z8000 CPU recognizes three interrupt inputs 
(non-maskable, vectored, and nonvectored) and a 
segmentation trap input. Any High-to-Low transition on the 
NMI in put is asynchronously edge detec ted and sets the 
internal NMI latch. The VI, NVI, and SEGT inputs, as well as 
the state of the internal NMI latch, are sampled at the end of 
T2 in the last machine cycle of any instruction. 

In response to an interrupt or trap, the subsequent IF-i cycle 
is exercised, but ignored. The internal state of the CPU is not 
altered and the instruction will be refetched and executed 
after the return from the interrupt routine. The program 
counter is not updated, but the system stack pointer is 
decremented in preparation for pushing starting information 
onto the system stack. 

The next machine cycle is the interrupt acknowledge cycle. 



This cycle has five automatic wait states, with additional wait 
states possible, as shown in Figure 14. 

After the last wait state, the CPU reads the information on 
AD0-AD15 and temporarily stores it, to be saved on the stack 
later in the acknowledge sequence. This word identifies the 
source of the interrupt or trap. For the nonvectored and 
nonmaskable interrupts, all 1 6 bits can represent peripheral 
device status information. For the vectored interrupt, the low 
byte is the jump vector, and the high byte can be extra user 
status. For the segmentation trap, the high byte is the 
Memory Management Unit identifier and the low byte is 
undefined. 

After the acknowledge cycle, the N/S output indicates the 
automatic change to system mode. 



_n_r 



INSTRUCTION 
— FETCH 1f\ — 
(ABORTED) 



_ ACKNOWLEDGE 



J \ / V 



■AT 



V 



f 



WW 



:xz: — x 



Figure 14. Interrupt and Segment Trap Request/Acknowledge Timing 



STATUS SAVING SEQUENCE 

The machine cycles, following the interrupt acknowledge or 
segmentation trap acknowledge cycle, push the old status 
information on the system stack in the following order: the 
16-bit program counter; the 7-bit segment number 



(Z8001/Z8005 only); the flag control word; and finally the 
interrupt/trap identifier. Subsequent machine cycles fetch 
the new program status from the program status area, and 
then branch to the interrupt/trap service routine. 



152 



BUS REQUEST ACKNOWLEDGE TIMING 



A Low on the BUSREQ input indicates to the CPU that 
another device is requestin g the Add ress/Data and control 
buses. The asynchronous BUSREQ input is syn chronized 
at the beginning of any machi ne cycle ( Figure 1 5). BUSREQ 
takes priority over WAI T. If BUSREQ is Low, an internal 
synchronous BUSREQ signal is generated, which— after 
completio n of the current machine cycle— causes the 
BUSACK output to go Low and all bus outputs to go into the 



high-impedance state. The requesting device- 
DMA— can then control the bus. 



typically a 



When BUSREQ is released, it is synchronized with the rising 
clock edge; the BUSACK output goes High one clock 
period later, indicating that the CPU will again take control of 
the bus. 



IN TERNAL 



MREO, DS, 
_ ST0-ST3, 
BIW, R/W, HIS . 



_i 

A 


1 ANY M CYCLE *■ 

T, Tj Tj 

\ 


Tx 


BUS 

Tx 


AVAILABLE — 

Tx 


Tx 


Tx 


Tx 




//( 
























y 


















\ 


/ 














W 


— \ 


J 
















>___. 




























— V 
>— 


-< 


_/ 




















y— 


-(sAME AS PREVIOUS CYCLeY 

\ r U 


—t 









Figure 15. Bus Request/ Acknowledge Timing 



153 



STOP 



The STOP input is sampled by the last falling clock edge 
immediately preceding any IF-| cycle (Figure 16) and before 
the second word of an EPA instruction is fetched. If STOP is 
found Low during the IF-| cycle, a stream of m emor y refresh 
cycles is inserted after T 3 , again sampling the STOP input on 
each falling clock edge in the middle of the T 3 states. During 
the EPA instruction, both EPA instruction words are fetched 
but any data transfer or subsequent instruction fetch is 



postponed until STOP is sampled High. This refresh 
operation does not use the refresh prescaler or its 
divide-by-four clock prescaler; rather, it double-inc remen ts 
the refresh counter every three clock cycles. When STOP is 
found High again, the next refresh cycle is completed, any 
remaining T states of the IF-j cycle are then executed, and 
the CPU continues its operation. 




Figure 16. Stop Timing 



154 



INTERNAL OPERATION 

cycles, each of which is three to eight clock cycles long 
(Figure 17). This allows fast response to Bus Request and 
Refresh Request, because bus request or refresh cycles 
can be inserted at the end of any internal machine cycle. 









T, 










I 
















WAIT 




















ST0-ST3 


X 


INTERNAL OP 


ERATION 














AS 


W 








AD 


^ UNDEFINED 


V 

) — 

* 








MREO, DS, R/W 




HIGH 






B/W 




UNDEFINED 
















HIS 




SAME AS PREVIOUS CYC 


LE 






I I 





Figure 17. internal Operation Timing 



Certain extended instructions, such as Multiply and Divide, 
and some special instructions need additional time for the 
execution of internal operations. In these cases, the CPU 
goes through a sequence of internal operation machine 



HALT 

A HALT instruction executes an unlimited number of 3-cycle 
internal operations, interspersed with memory refresh 
cycles whenever requested. An interrupt, segmentation 
trap, or reset are the only exits from a HALT instruction. 



The CPU samples the VI, NVI, NMI, and SEGT inputs at the 
beginning of every T 3 cycle. If an input is found active during 
two consecutive samples, the subsequent IF-| cycle is 
exercised, but ignored, and the normal interrupt 
acknowledge cycle is started. 



155 



ii loien ibi ueu uy iwo, tnus stepping tnrougn 2sb consecutive 
refresh addresses on AD r ADg. Unless disabled, the 
presettable prescaler runs continuously and the delay in 
starting a refresh cycle is therefore not cumulative. 

While the STOP input is Low, a continuous stream of memory 
refresh cycles, each three T-states long, is executed without 
using the refresh prescaler. 



CLOCK 



WAIT 



ST -ST 3 



MREQ 













T, »- 


•* Ti »- 


-* Tj m- 






































v 
X_ 


REFRESH 


















\ / 










\ 


/ 












^ REFRESH ADDRE 


1 


























SAME AS PREVIOUS 


CYCLE 








1 





Figure 18, Memory Refresh Timing 



w w uivUwM In H i^llbOll UUUI IICI I uo UCCI I 

decremented to zero, a refresh cycle consisting of three 
T-states is started as soon as possible (that is, after the next 
IF! cycle or Internal Operation cycle). 

The 9-bit refresh counter value is put on the low-order side of 
the address bus (AD -AD 8 ); AD9-AD15 are undefined 
(Figure 18). Since the memory is word-organized, Ao is 
always Low during refresh and the refresh counter is always 



RESET 



A Low on the RESET input causes the following results within 
five clock cycles (Figure 1 9): 

■ ADo-AD-| 5 are3-stated 

■ AS, DS, MREQ, ST -ST 3 , BUSACK, and MO are forced 
High 

■ SN -SN 6 are forced Low 

■ Refresh is disabled 

■ R/W, B/W] and N/S are not affected 



When RESET has been High for three clock periods, three 
consecutive memory read cycles are executed in the system 
mode for the Z8001 . The Z8002 has two consecutive 
read cycles. In the Z8001 , the first cycle reads the 
flag and control word from location 0002, the next reads the 
7-bit program counter segment number from location 0004, 
the next reads the 16-bit PC offset from location 0006, and 
the following IF, cycle starts the program. In the Z8002, the 
first cycle reads the flag and control word from location 
0002, the next reads the PC from location 0004, and the 
following IF, cycle starts the program. 



156 



COMPOSITE AC TIMING DIAGRAM 



This composite timing dia- 
gram does not show actual 
timing sequences. Refer to 
this diagram only for the 
detailed timing relationships 
of individual edges. Use the 
preceding illustrations as an 
explanation of the various 
timing sequences 



Timing measurements are 
^L^— made at the following 

fC voltages: 
* r> High Low 




AOo-ADis 



S T0-ST3 , 
RE A D/ WRITE , 
NORMAL/SYSTEM, 
BYTE/WORD 



158 



AC CHARACTERISTICSt 



Z8001/2 Z8001/2 Z8001/2 

4 MHz 6 MHz 10 MHz 



Number 


Symbol 


Parameter 


Min 


Max 


Min 


Max 


Min 


Max 


1 


TcC 


Clock Cycle Time 


250 


2000 


165 


2000 


100 


2000 


2 


TwCh 


Clock Width (High) 


105 


1895 


70 


1930 


40 


1960 


3 


TwCI 


Clock Width (Low) 


105 


1895 


70 


1930 


40 


1960 


4 


TfC 


Clock Fall Time 




20 




10 




10 


5 


TrC 


Clock Rise Time 




20 




15 




10 


6 


TdC(SNv) 


Clock t to Segment Number Valid (50 pf load) 




130 




110 




90 


7 


TdC(SNn) 


Clock t to Segment Number Not Valid 


20 




10 









8 


TdC(Bz) 


Clock t to Bus Float 




65 




55 




50 


9 


TdC(A) 


Clock t to Address Valid 




100 




75 




55 


10 


TdC(Az) 


Clock t to Address Float 




65 




55 




50 


11 


TdA(DR) 


Address Valid to Read Data Required Valid 




475* 




305* 




180* 


12 


TsDR(C) 


Read Data to Clock i Setup time 


30 




20 




10 




13 


TdDS(A) 


DS t to Address Active 


80* 




45* 




20* 




14 


TdC(DW) 


Clock t to Write Data Valid 




100 




75 




60 


15 


ThDR(DS) 


Read Data to DS t Hold Time 

















16 


TdDW(DS) 


Write Data Valid to DS t Delay 


295* 




195* 




110* 




17 


TdA(MR) 


Address Valid to MREQ I Delay 


55" 




35* 




20* 




18 


TdC(MR) 


Clock i to MREQi Delay 




80 




70 




50 


19 


TwMRh 


MREQ Width (High) 


210* 




135* 




80* 




20 


TdMR(A) 


MREQ J to Address Not Active 


70* 




35* 




20* 




21 


TdDW(DSW) 


Write Data Valid to DS i (Write) Delay 


55* 




35* 




15* 




22 


TdMR(DR) 


MREQ 1 to Read Data Required Valid 




370* 




230* 




140* 


23 


TdC(MR) 


Clock I MREQ t Delay 




80 




60 




50 


24 


TdC(ASf) 


Clock t to AS i Delay 




80 




60 




45 


25 


TdA(AS) 


Address Valid to AS t Delay 


55' 




35" 




20" 




26 


TdC(ASr) 


Clock i to AS t Delay 




90 




80 




45 


27 


TdAS(DR) 


AS t to Read Data Required Valid 




360* 




220* 




140* 


28 


TdDS(AS) 


DS t to AS i Delay 


70* 




35* 




15* 




29 


TwAS 


AS Width (Low) 


85* 




55* 




30* 




30 


TdAS(A) 


AS t to Address Not Active Delay 


70* 




45" 




20* 




31 


TdAz(DSR) 


Address Float to DS (Read) * Delay 

















32 


TdAS(DSR) 


AS t to DS (Read) i Delay 


80* 




55* 




30* 




33 


TdDSR(DR) 


DS (Read) i to Read Data Required Valid 




205* 




130* 




70* 


34 


TdC(DSr) 


Clock i to DS t Delay 




70 




65 




50 


35 


TdDS(DW) 


DS t to Write Data Not Valid 


75* 




45" 




25* 




36 


TdA(DSR) 


Address Valid to DS (Read) 1 Delay 


180* 




110* 




65* 




37 


TdC(DSR) 


Clock t to DS (Read) i Delay 




120 




85 




65 


38 


TwDSR 


DS (Read) Width (Low) 


275* 




185* 




110* 




39 


TdC(DSW) 


Clock 1 to DS (Write) I Delay 




95 




80 




65 


40 


TwDSW 


DS (Write) Width (Low) 


185* 




110* 




75* 





'Clock-cycle time-dependent characteristics. See Footnotes to AC Characteristics. 
tUnits in nanoseconds (ns). 



159 



AC CHARACTERISTICSf (Continued) 









28001/2 


28001/2 


28001/2 








4 MHz 


6 MHz 


10 MHz 


Number 


Symbol 


Parameter 


Min Max 


Min Max 


Min Max 


41 


TdDSI(DR) 


DS (I/O) i to Read Data Required Valid 


330* 


210* 


120* 


42 


TdC(DSf) 


Clock i to DS (I/O) I Delay 


120 


90 


65 


43 


TwDS 


DS (I/O) Width (Low) 


410* 


255* 


160* 


44 


TdAS(DSA) 


AS t to DS (Acknowledge) J Delay 


1065* 


690* 


410* 


45 


TdC(DSA) 


Clock t to DS (Acknowledge) i Delay 


120 


85 


70 


HO 




1 AnUr\r\\\i\or\nei\ 1 fn Roar! riata Roni liroH 












Delay 


455* 


295* 


165* 


47 


TdC(S) 


Clock t to Status Valid Delay 


110 


85 


65 


48 


TdS(AS) 


Status Valid to AS t Delay 


50* 


30* 


20* 


49 


TsR(C) 


RESET to Clock t Setup Time 


180 


70 


50 


50 


ThR(C) 


RESET to Clock t Hold Time 











51 


TwNMI 


NMl Width (Low) 


100 


70 


50 


52 


TsNMI(C) 


NMi to Clock t Setup Time 


140 


70 


50 


53 


TsVI(C) 


VI, NVI to Clock t Setup Time 


110 


50 


40 


54 


ThVI(C) 


VI, NVI to Clock t Hold Time 


20 


20 


10 


55 


TsSGT(C) 


SEGT to Clock t Setup Time 


70 


55 


40 


56 


ThSGT(C) 


SEGT to Clock t Hold Time 











57 


TsMI(C) 


Ml to Clock t Setup Time 


180 


140 


80 


58 


ThMI(C) 


Mi to Clock t Hold Time 











59 


TdC(MO) 


Clock t to MO Delay 


120 


85 


80 


60 


TsSTP(C) 


STOP to Clock i Setup Time 


140 


100 


50 


61 


ThSTP(C) 


STOP to Clock J Hold Time 











62 


TsW(C) 


WAIT to Clock i Setup Time 


50 


30 


20 


63 


ThW(C) 


WAIT to Clock i Hold Time 


10 


10 


5 


64 


TsBRQ(C) 


BUSREQ to Clock t Setup Time 


90 


80 


60 


65 


ThBRQ(C) 


BUSREQ to Clock t Hold Time 


10 


10 


5 


66 


TdC(BAKr) 


Clock t to BUSACK t Delay 


100 


75 


65 


67 


TdC(BAKf) 


Clock t to BUSACK 1 Delay 


100 


75 


65 


68 


TwA 


Address Valid Width 


150* 


95* 


50* 


69 


TdDS(S) 


DS t to STATUS Not Valid 


80* 


55* 


30* 



* Clock-cycle time-dependent characteristics- See Footnotes to AC Characteristics. 
tUnits in nanoseconds (ns). 



160 



FOOTNOTES TO AC CHARACTERISTICS 







Z8001/2 


Z8001/2 




Z8001/2 








4 MHz 


6 MHz 




10 MHz 




Number 


Symbol 


Equation 


Equation 




Equation 




■j ■] 




OTrP -+- TwPh — nn n<; 

c. 1 UU t IWUl I — 1 OU 1 lo 


?TrP + TwPh - 

C 1 UU i IWUI 1 


- 95 ns 


?TrP + TwPh - 

C. 1 UU T IWUI 1 


- 60 ns 


I o 




TwPI - 0^ nc 

IWUl — CJ 1 lo 


TwPI — 9^ nc. 

IWUl — 1 lo 




TwPl - 00 nc 

IWUI — t—\J 1 IO 




1 6 




TrP TwPh — fifi nc 

1 UU t IWUl 1 vJ<J 1 lo 


TrP 4- TwPh — 

1 1 IWUl 1 


40 ns 


TrP + TwPh - 

1 UU i IWUI i 


30 ns 


-| 7 


THA/'MRI 


TwPh — nc 
iwui i — ou i lo 


TwPh — nc 

IWUl 1 — OO 1 to 




TwPh — 00 nc 

IWUI 1 C\J J IO 




19 


TwMRh 


TcC - 40 ns 


TcC - 30 ns 




TcC - 20 ns 




on 




TwPI O.C: nc 
IWUl — OO lib 


Ta/PI nc 
IWUl OO 1 lb 




TwPI Of! nc 
IWUI c\> \ lb 




91 
tL I 


1 UUVV^L'OVvJ 


Ti*;Ph RO nc 

iwun - ou rib 


TiA/Ph nc 

iwun — oo rib 




IWUfl d.O Mb 






TrtMR/nR\ 

i uivin^LTu 


OTrP 1 °,n nc 
£ I Lb — I OU Mb 


OTrP 1 00 nc 
d. I UU I UU 1 lb 




9TrP Rfl nc 
d- 1 UU OU I lo 




9R 

<iO 




Ta/PH nc 
IWUil — OU lib 


T\A/Ph nc 
IWUM OO Mb 




"R*/Ph 0C\ nc 

iwun — c.\j ns 




27 


TdAS(DR) 


2TcC - 140 ns 


2TcC - 110 ns 




2TcC - 60 ns 




op. 




IWUI — OO MS 


TaiPI no 

iwui — oo ns 




Tia/PI OC nc 

iwui — dX) ns 




9Q 


Tu/AC; 


Tu/Ph OH nc 

iwun £iu nb 


Tu/Ph 1 C no 

iwun — i o no 




T\A»Ph 1 n nc 

iwun — i u ns 




OU 


1 QMolM; 


Tai^I O.G nc 

iwui — oo ns 


Ta/OI oc: no 

iwui - do ns 




TajOI OC\ nc 

iwui — c\j ns 






1 OAo(Uon) 


TlAf!*" 1 ! OC no 

iwui — ^o ns 


iwui — io ns 




"n»if~"i i n no 

iwui — i u ns 




33 


TdDSR(DR) 


TcC + TwCh - 1 50 ns 


TcC + TwCh - 


105 ns 


TcC + TwCh - 


70 ns 


do 


i aUo(uvvj 


iwui — ou ns 


iwui — <;o ns 




T»il"*l 1 C no 

iwui — i o ns 




JO 


THA/riCD\ 


1 Cu — / u ns 


i cu — oo ns 




T„P QC no 

I cu — oo ns 




TO 
OO 


x.,ncD 
iWUon 


icu + iwun — ou ns 


I Cu + iwun — 


50 ns 


icu + iwun — 


30 ns 


/in 


IWUOVV 


T/-.r^ CC no 

i cu — oo ns 


I Cu — oo ns 




Ta(~> OC no 

i cu — to ns 




41 


TnlFlCI/'r~lD\ 

1 aUbl(Un) 


^ icu — i fx) ns 


OTnP < no, 

^ I cu — i d\j ns 




OT/.P On nn 

^ I cu — ou ns 




43 


TwDS 


2TcC - 90 ns 


2TcC - 75 ns 




2TcC - 40 ns 




44 


TdAS(DSA) 


4TcC + TwCI - 40 ns 


4TcC + TwCI - 


40 ns 


4TcC + TwCI - 


30 ns 


46 


TdDSA(DR) 


2TcC + TwCh - 1 50 ns 


2TcC + TwCh - 


- 105 ns 


2TcC + TwCh 


- 75 ns 


48 


TdS(AS) 


TwCh - 55 ns 


TwCh - 40 ns 




TwCh - 30 ns 




68 


TwA 


TcC - 90 ns 


TcC - 70 ns 




TcC - 50 ns 




69 


TdDS(s) 


TwCI - 25 ns 


TwCI -15ns 




TwCI - 1 ns 





AC Timing Test Conditions 
V 0L = 0.8V 
V H = 20V 
V, L = 0.8V 
V| H = 2.4V 
V| LC - 0.45V 
V|HC= V CC -0.4V 



161 



ABSOLUTE MAXIMUM RATINGS 



Stresses greater than those listed under Absolute Maximum Ratings may 
cause permanent damage to the device. This is a stress rating only; 
operation of the device at any condition above those indicated in the 
operational sections of these specifications is not implied. Exposure to 
absolute maximum rating conditions for extended periods may affect 
device reliability. 



STANDARD TEST CONDITIONS 

The DC characteristics below apply for the following test 
conditions, unless otherwise noted. All voltages are 
referenced to GND (OV). Positive current flows into the 
referenced pin. 

Available operating temperature ranges are: 

■ S = 0°Cto +70°C, + 4.75V <V CC « + 5.25V 

■ E = -40-CtO+100-C,+4.75V<Vcc<+5.25V 

All ac parameters assume a total load capacitance The Ordering Information section lists package temperature 
(including parasitic capacitances) or 1 00 pf max, except for ranges and product numbers, 
parameter 6 (50 pf max). Timing references between two 
output signals assume a load difference of 50 pf max. 



DC CHARACTERISTICS 



Symbol 


Parameter 


Min 


Max 


Unit 


Condition 


VCH 


Clock Input High Voltage 


V CC -0.4 


V CC + 0-3 


V 


Driven by External Clock Generator 


V C L 


Clock Input Low Voltage 


-0.3 


0.45 


V 


Driven by External Clock Generator 


VlH 


Input High Voltage 


2.0 


V CC + 03 


V 




V|H RESET 


Input High Voltage on RESET pin 


2.4 


V CC + 0.3 


V 




V IHNMI 


Input High Voltage on NMI pin 


2.4 


V CC + 0.3 


V 




VlL 


Input Low Voltage 


-0.3 


0.8 


V 




V H 


Output High Voltage 


2.4 




V 


l H = -250 mA 


Vol 


Output Low Voltage 




0.4 


V 


Iol = +2 mA 


IlL 


Input Leakage 




±10 


XA 


0.4<V| N < + 2.4V 


!|L SEGT 


Input Leakage on SEGT pin 


-100 


100 






lOL 


Output Leakage 




±10 


MA 


0.4«V| N « + 2.4V 


!CC 


Vcc Power Supply Current 




300 


mA 


4 MHz and 6 MHz commercial 








400 


mA 


Extended temperature range 








400 


mA 


10 MHz speed range 



Voltages on all pins with respect 

to GND -0.3V to +7.0V 

Operating Ambient 

Temperature See Ordering Information 

Storage Temperature -65°Cto +150°C 



+ SV 




2.1K 



162 



Zilog 



Product Specification 



Z8010Z8000 MMU 
Memory Management Unit 



October 1988 



Features ■ Dynamic segment relocation makes software 

addresses independent of physical memory 
addresses. 

■ Sophisticated memory-management features 
include access validation that protects 
memory areas from unauthorized or 
unintentional access, and a write-warning 
indicator that predicts stack overflow. 

■ For use with both Z8001 and Z8003 CPU. 



■ 64 variable-sized segments from 256 to 
65,536 bytes can be mapped into a total 
physical address space of 16M bytes; all 64 
segments are randomly accessible. 

■ Multiple MMUs can support several transla- 
tion tables for each Z8001 address space. 

■ MMU architecture supports multi-program- 
ming systems and virtual memory implemen- 
tations. 



The Z8010 Memory Management Unit (MMU) 
manages the large 8M byte addressing spaces 
of the Z8001 CPU. The MMU provides dynamic 
segment relocation as well as numerous 
memory protection features. 

Dynamic segment relocation makes user soft- 
ware addresses independent of the physical 
memory addresses, thereby freeing the user 
from specifying where information is actually 



located in the physical memory. It also pro- 
vides a flexible, efficient method for support- 
ing multi-programming systems. The MMU 
uses a translation table to transform the 23-bit 
logical address output from the Z8001 CPU 
into a 24-bit address for the physical memory. 
(Only logical memory addresses go to an MMU 
for translation; I/O addresses and data, in 
general, must by pass this component.) 



DM Af SEGMENT - 



BUS TIMING 



CHIP SELECT - 



AO,, 




A !3 


AD„ 




Ai! 


AD, 3 




Aj, 


AD,j 




Am 


AD,, 




A,, 


AD„ 




A„ 


AD, 




A, T 


AO, 




A,, 






A,s 


SN, 




A,. 


SN, 




A,3 


SN 4 




A,! 


SN, 


Z8010 




MMU 


A„ 


SN 2 




A,o 


SN, 




A. 


SN 




A. 


STQT 




SUP 



cs 



ST n 



t t t J_ 

+ 5V QNO CLK RESET 

Figure 1. Pin Functions 




Figure 2. 48-pin Dual-In-Line Package (DIP), 
Pin Assignments 



163 



General Memory segments are variable in size from 

Description 256 bytes to 64K bytes, in increments of 256 
(Continued) bytes. Pairs of MMUs support the 128 segment 
numbers available for the various Z8001 CPU 
address spaces. Within an address space, any 
number of MMUs can be used to accommodate 
multiple translation tables for System and Nor- 
mal operating modes, or to support more 
sophisticated memory-management systems. 

MMU memory-protection features safeguard 
memory areas from unauthorized or unin- 
tended access by associating special access 
restrictions with each segment. A segment is 
assigned a number of attributes when its 
descriptor is entered into the MMU. When a 
memory reference is made, these attributes are 
checked against the status information sup- 
plied by the Z8001 CPU. If a mismatch oc- 



curs, a trap is generated and the CPU is inter- 
rupted. The CPU can then check the status 
registers of the MMU to determine the cause. 

Segments are protected by modes of permit- 
ted use, such as read only, system only, 
execute only and CPU-access only. Other seg- 
ment management features include a write- 
warning zone useful for stack operations and 
status flags that record read or write accesses 
to each segment. 

The MMU is controlled via 22 Special I/O 
instructions from the Z8000 CPU in System 
mode. With these instructions, system software 
can assign program segments to arbitrary 
memory locations, restrict the use of segments 
and monitor whether segments have been read 
or written. 



164 



General MOMENT NUMBER OFFSET/DATA SEGMENT NUMBER offset/data 



Description 

(Continued) 




STATUS SEGMENT SUPPRESS PHYSICAL STATUS SEGMENT SUPPRESS PHYSICAL 

INFORMATION TRAP ADDRESS INFORMATION TRAP ADDRESS 

REQUEST REQUEST 



Figure 3. The shaded areas in these block diagrams illustrate the resources used in the two modes of MMU operation. In 
the Address Translation Mode shown on the left, addresses are translated automatically. In the Command Mode shown 
on the right, specific registers are accessed using Special I/O commands. 



165 



cedure and data set can reside in its own 
segment. 

The 8M byte Z8001 addressing spaces are 
divided into 128 relocatable segments of up to 
64K bytes each. A 23-bit segmented address 
uses a 7-bit segment address to point to the 
segment, and a 16-bit offset to address any 
byte relative to the beginning of the segment. 
The two parts of the segmented address may 
be manipulated separately. 

The MMU divides the physical memory into 
256-byte blocks. Segments consist of physically 
contiguous blocks. Certain segments may be 
designated so that writes into the last block 
generate a warning trap. If such a segment is 
used as a stack, this warning can be used to 
increase the segment size and prevent a stack 
overflow error. 

The addresses manipulated by the program- 
mer, used by instructions and output by the 
Z8001 are called logical addresses. The MMU 
takes the logical addresses and transforms 
them into the physical addresses required for 
accessing the memory (Figure 4). This address 
transformation process is called relocation. 

The relocation process is transparent to user 
software. A translation table in the MMU 
associates the 7-bit segment number with the 
base address of the physical memory segment. 
The 16-bit logical address offset is added to the 
physical base address to obtain the actual 
physical memory location. Because a base 
address always has a low byte equal to zero. 



the same as the low-order byte of the logical 
address offset. This low-order byte therefore 
bypasses the MMU, thus reducing the number 
of pins required. 




24-BIT PHYSICAL 4 



Figure 4. Logical-to-Physical Address Translation 



Memory Each memory segment is assigned several 

Protection attributes that are used to provide memory 

access protection. A memory request from the 
Z8001 CPU is accompanied by status infor- 
mation that indicates the attributes of the 
memory request. The MMU compares the 
memory request attributes with the segment 
attributes and generates a Trap Request 
whenever it detects an attribute violation. Trap 
Request informs the Z8001 CPU and the 
system control program of the violation so that 
appropriate action can be taken to recover. 
The MMU also generates the Suppress signal 
SUP in the event of an access violation. Sup- 
press can be used by a memory system to inhi- 
bit stores into the memory and thus protect the 
contents of the memory from erroneous 
changes. 

Five attributes can be associated with each 
segment. When an attempted access violates 
any one of the attributes associated with a seg- 
ment, a Trap Request and a Suppress signal 
are generated by the MMU. These attributes 
are read only, execute only, system access 
only, inhibit CPU accesses and inhibit DMA 
accesses. 



Segments are specified by a base address 
and a range of legal offsets to this base 
address. On each access to a segment, the off- 
set is checked against this range to insure that 
the access falls within the allowed range. If an 
access that lies outside the segment is attemp- 
ted. Trap Request and Suppress are generated. 

Normally the legal range of offsets within a 
segment is from to 256N + 255 bytes, where 
0<N<255. However, a segment may be 
specified so that legal offsets range from 256N 
to 65,535 bytes, where 0sN<255. The later 
type of segment is useful for stacks since the 
Z8000 stack manipulation instructions cause 
stacks to grow toward lower memory locations. 
Thus when a stack grows to the limit of its 
allocated segment, additional memory can be 
allocated on the correct end of the segment. 
As an aid in maintaining stacks, the MMU 
detects when a write is performed to the lowest 
allocated 256 bytes of these segments and 
generates a Trap Request. No Suppress signal 
is generated so the write is allowed to proceed. 
This write warning can then be used to indi- 
cate that more memory should be allocated to 
the segment. 



166 



MMU The MMU contains three types of registers: 

Register Segment Descriptor, Control and Status. A 

Organization set of 64 Segment Descriptor Registers supplies 
the information needed to map logical memory 
addresses to physical memory locations. The 
segment number of a logical address deter- 
mines which Segment Descriptor Register is 
used in address translation. Each Descriptor 
Register also contains the necessary informa- 
tion for checking that the segment location 
referenced is within the bounds of the segment 
and that the type of reference is permitted. It 
also indicates whether the segment has been 
read or written. 

In addition to the Segment Descriptor 
Registers, the Z8010 MMU contains' three 8-bit 
control registers for programming the device 
and six 8-bit status registers that record infor- 
mation in the event of an access violation. 

Segment Descriptor Registers. Each of the 64 
Descriptor Registers contains a 16-bit base 
address field, an 8-bit limit field and an 8-bit 
attribute field (Figure 5). The base address 
field is subdivided into high- and low-order 
bytes that are loaded one byte at a time when 
the descriptor is initialized. The limit field con- 
tains a value N that indicates N + 1 blocks of 
256 bytes have been allocated to the segment.* 

The attribute field contains eight flags 
(Figure 6). Five are related to protecting the 
segment against certain types of access, one 
indicates the special structure of the segment, 
and two encode the types of accesses that have 
been made to the segment. A flag is set when 
its value is 1 . The following brief descriptions 
indicate how these flags are used. 

Read-Only (RD). When this flag is set, the segment is read 
only and is protected against any write access. 

System-Only (SYS). When this flag is set, the segment can 
be accessed only in System mode, and is protected against 
any access in Normal mode. 

CPU-Inhibit (CPUI). When this (lag is set, the segment is 
not accessible to the currently executing process, and is 
protected against any memory access by the CPU. The 
segment is, however, accessable under DMA. 

Execute-Only (EXC). When this flag is set, the segment 
can be accessed only during an instruction fetch or access 
by the relative addressing mode cycle, and thus is pro- 
tected against any access during other cycles. 

DMA-Inhibit (DMAI). When this flag is set, the segment 
can be accessed only by the CPU, and thus is protected 
against any access under DMA. 

Direction and Warning (DIRW). When this flag is set, the 
segment memory locations are considered to be organized 
in descending order and each write to the segment is 
checked for access to the last 256-byte block. Such an 
access generates a trap to warn of potential segment 
overflow, but no Suppress signal is generated. 

Changed (CHG). When this flag is set, the segment has 
been changed (written). This bit is set automatically during 
any write access to this segment if the write access does not 
cause any violation. 

Referenced (REF). When this flag is set, the segment has 
been referenced (either read or written). This bit is set 
automatically during any access to the segment if the 
access does not cause a violation. 

'In the stack mode, segment size is 64K-256N. 



BAH63 1 6AL63 L63 A63 



Figure 5. Segment Descriptor Registers 



Figure 6. Attribute Field in Segment Descriptor Register 

Control Registers. The three user-accessible 
8-bit control registers in the MMU direct the 
functioning of the MMU (Figure 7). The Mode 
Register provides a sophisticated method for 
selectively enabling MMUs in multiple-MMU 
configurations. The Segment Address Register 
(SAR) selects a particular Segment Descriptor 
Register to be accessed during a control 
operation. The Descriptor Selection Counter 
Register points to a byte within the Segment 
Descriptor Register to be accessed during a 
control operation. 

6 5 4 3 2 1 



^SEf^TRNS 



1 DESCRIPTOR 

DSC I SELECTION 
L_ I COUNTER 



Figure 7. Control Registers 

The Mode Register contains a 3-bit iden- 
tification field (ID) that distinguishes among 
eight enabled MMUs in a multiple-MMU con- 
figuration. This field is used during the seg- 
ment trap acknowledge seguence (refer to the 
section on Segment Trap and Acknowledge). 
In addition, the Mode Register contains five 
flags. 

Multiple Segment Table (MST). This flag indicates whether 
multiple segment tables are present in the hardware con- 
figuration. When this flag is set, more than one table is 
present and the N/S line must be used to determine 
whether the MMU contains the appropriate table. 

Normal Mode Select (NMS). This flag indicates whether 
the MMU is to translate addresses when the N/S line is 
High or Low. If the MST flag is set, the N/S line must 
match the NMS flag for the MMU to translate segment 
addresses, otherwise the MMU Address lines remain 
3- stated. 



167 



MMU 

Register 
Organization 

(Continued) 



Upper Range Select (URS). This flag is used to indicate 
whether the MMU contains the lower-numbered segment 
descriptors or the higher-numbered segment descriptors. 
The most significant bit of the segment number must match 
the URS flag for the MMU to translate segment addresses, 
otherwise the MMU Address lines remain 3-stated. 

Translate (TRNS). This flag indicates whether the MMU is 
to translate logical program addresses to physical memory 
locations or is to pass the logical addresses unchanged to 
the memory and without protection checking. In the non- 
translation mode, the most significant byte of the output is 
the 7-bit segment number and the most significant bit is 0. 
When this flag is set, the MMU performs address transla- 
tion and attribute checking. 

Master Enable (MSEN). This flag enables or disables the 
MMU from performing its address translation and memory 
protection functions. When this flag is set, the MMU per- 
forms these tasks; when the flag is clear the Address lines 
of the MMU remain 3-stated. 

The Segment Address Register (SAR) points 
to one of the 64 segment descriptors. Control 
commands to the MMU that access segment 
descriptors implicitly use this pointer to select 
one of the descriptors. This register has an 
auto-incrementing capability so that multiple 
descriptors can be accessed in a block 
read/write fashion. 

The Descriptor Selection Counter Register 
holds a 2-bit counter that indicates which byte 
in the descriptor is being accessed during the 
reading or writing operation. A value of zero 
in this counter indicates the high-order byte of 
the base address field is to be accessed, one 
indicates the low-order byte of the base 
address, two indicates the limit field and three 
indicates the attribute field. 

Status Registers. Six 8-bit registers contain 
information useful in recovering from memory 
access violations (Figure 8). The Violation 
Type Register describes the conditions that 
generated the trap. The Violation Segment 
Number and Violation Offset Registers record 
the most-significant 15 bits of the logical 
address that causes a trap. The Instruction 
Segment Number and Offset Registers record 
the most-significant 15 bits of the logical 
address of the last instruction fetched before 
the first accessing violation. These two 
registers can be used in conjunction with 
external circuitry that records the low-order 
offset byte. At the time of the addressing viola- 
tion, the Bus Cycle Status Register records the 
bus cycle status (status code, read/write mode 
and normal/system mode). 

The MMU generates a Trap Reguest for two 
general reasons: either it detects an access 



violation, such as an attempt to write into a 
read-only segment, or it detects a warning 
condition, which is a write into the lowest 256 
bytes of a segment with the DIRW flag set. 
When a violation or warning condition is 
detected, the MMU generates a Trap Reguest 
and automatically sets the appropriate flags. 
The eight flags in the Violation Type Register 
describe the cause of a trap. 

Read-Only Violation (RDV). Set when_the CPU attempts to 
access a read-only segment and the R/W line is Low. 

System Violation (SYSV). Set_when the CPU accesses a 
system-only segment and the N/S line is High. 

CPU-Inhibit Violation (CPUIV). Set when the CPU 
attempts to access a segment with the CPU-inhibit flag set. 

Execute-Only Violation (EXCV). Set when the CPU 
attempts to access an execute-only segment in other than 
an instruction letch or load relative instructions cycle. 

Segment Length Violation (SLV). Set when an offset falls 
outside of the legal range of a segment. 

Primary Write Warning (PWW). Set when an access is 
made to the lowest 256 bytes of a segment with the DIRW 
flag set. 

Secondary Write Warning (SWW). Set when the CPU 
pushes data into the last 256 bytes of the system stack and 
EXCV, CPUIV, SLV, SYSV, RDV or PWW is set. Once this 
flag is set, subsequent write warnings for accessing the 
system stack do not generate a Segment Trap request. 

Fatal Condition (FATL). Set when any other flag in the 
Violation Type Register is set and either a violation is 
detected or a write warning condition occurs in Normal 
mode. This flag is not set during a stack push in System 
mode that results in a warning condition. This flag 
indicates a memory access error has occurred in the trap 
processing routine. Once set, no Trap Request signals are 
generated on subsequent violations. However, Suppress 
signals are generated on this and subsequent CPU viola- 
tions until the FATL flag has been reset. 



PWW EXCV CPUIV SLV 



SEGMENT NUMBER 



8US 

CYCLE 

STATUS 



SEGMENT NUMBER 



Figure 8. Status Registers 



168 



Segment The Z8010 MMU generates a Segment Trap 

Trap and when it detects an access violation or a 
Acknowledge write warning condition. In the case of an 

access violation, the MMU also activates Sup- 
press, which can be'used to inhibit memory 
writes and to flag special data to be returned 
on a read access. Segment Trap remains Low 
until a Trap Acknowledge signal is received. If 
a CPU-generated violation occurs, Suppress is 
asserted for that cycle and all subsequent CPU 
instruction execution cycles until the end of 
the instruction. Intervening DMA cycles are 
not suppressed, however, unless they generate 
a violation. Violations detected during DMA 
cycles cause Suppress to be asserted during 
that cycle only — no Segment Trap Requests are 
ever generated during DMA cycles. 

Segment traps to the Z8001/3 CPU are han- 
dled similarly to other types of interrupts. To 
service a segment trap, the CPU issues a seg- 
ment trap acknowledge cycle. The acknow- 
ledge cycle is always preceded by an instruc- 
tion fetch cycle that is ignored (the MMU has 
been designed so that this dummy cycle is 
ignored). During the acknowledge cycle all 
enabled MMUs use the Address/Data lines to 
indicate their status. An MMU that has 
generated a Segment Trap Request outputs a 1 
on the A/D line associated with the number in 
its ID field; an MMU that has not generated a 
segment trap request outputs a on its 
associated A/D line. A/D lines for which no 
MMU is associated remain 3-stated. During a 



segment trap acknowledge cycle, an MMU 
uses A/D line 8 + i if its ID field is i. 

Following the acknowledge cycle the CPU 
automatically pushes the Program Status onto 
the system stack and loads another Program 
Status from the Program Status Area. The Seg- 
ment Trap line is reset during the segment trap 
acknowledge cycle. Suppress is not generated 
during the stack push. If the store creates a 
write warning condition, a Segment Trap 
Request is generated and is serviced at the 
end of the Program Status swap. The SWW 
flag is also set. Servicing this second Segment 
Trap Request also creates a write warning con- 
dition, but because the SWW flag is set, no 
Segment Trap Request is generated. If a viola- 
tion rather than a write warning occurs during 
the Program Status swap, the FATL flag is set 
rather than the SWW flag. Subsequent viola- 
tions cause Suppress to be asserted but not 
Segment Trap Request. Without the SWW and 
FATL flags, trap processing routines that 
generate memory violations would repeatedly 
be interrupted and called to process the trap 
they created. 

The CPU routine to process a trap request 
should first check the FATL flag to determine 
if a fatal system error has occurred. If not, the 
SWW flag should be checked to determine if 
more memory is required for the system stack. 
Finally, the trap itself should be processed and 
the Violation Type Register reset. 



Virtual Several features of the MMU can be used in 

Memory conjunction with external circuitry to support 

virtual memory for the Z8001. Segment Trap 
Request can be used to signal the CPU in the 
event that a segment is not in primary memory. 
The CPU-Inhibit Flag can be used to indicate 
whether a segment is in the memory or in 



secondary storage. The Changed and Altered 
Flags in the attribute field for each segment 
can aid in implementing efficient segment 
management policies. The Status Registers can 
be used in recovering from virtual memory 
access faults. 



Multiple MMU architecture directly supports two 

MMUs methods for multiple MMU configurations. The 

first approach extends single-MMU capability 
for handling 64 segments to a dual-MMU con- 
figuration that manages the 128 different 
segments the Z8001 can address. This 
scheme uses the URS flag in the Mode Register 
in connection with the high-order bit of the 
segment number (SN6). 

The second approach uses several MMUs to 
implement multiple translation tables. Multiple 
tables can be used to reduce the time required 
to switch tasks by assigning separate tables to 
each task. Multiple translation tables for multi- 



task environments can use the Master Enable 
Flag to enable the appropriate MMUs through 
software. Multiple translation tables may also 
be used to extend the physical memory size 
beyond 16 megabytes by separating system 
from normal memory and/or program from 
data memory. The MST and NMS flags in the 
Mode _Register can be used in conjunction with 
the N/S line to select the MMU that contains 
the appropriate table. Special external cir- 
cuitry that monitors the CPU Status lines can 
manipulate the MMU N/S line to perform this 
selection. 



169 



DMA in either the System or Normal mode of 
operation. For each memory access, the seg- 
ment attributes are checked and if a violation 
is detected. Suppress is activated. Unlike a 
CPU violation that automatically causes Sup- 
press signals to be generated on subsequent 
memory accesses until the next instruction, 
DMA violations generate a Suppress only on a 
per memory access basis. 

The DMA device should note the Suppress 
signal and record sufficient information to 
enable the system to recover from the access 
violation. No Segment Trap Request is ever 
generated during DMA, hence warning 
conditions are not signaled. Trap Requests are 
not issued because the CPU cannot 
acknowledge such a request. 



iy *.u'*vs UK, , , , i Ul a 

DMA cycle. A Low DMASYNC inhibits the 
MMU from using an indeterminate segment 
number on lines SNn-SNg. When the DMA 
logical memory address is valid, the 
DMASYNC line must be High before a rising 
edge of Clock and the MMU then performs its 
address translation and access protection func- 
tions. Upon the release of the bus at the ter- 
mination of the DMA cycle the DMASYNC line 
must again be High. After two clock cycles of 
DMASYNC High, the MMU assumes that the 
CPU has control of the bus and that subse- 
quent memory references are CPU accesses. 
The first instruction fetch occurs at least two 
cycles after the CPU regains control of the 
bus. During CPU cycles, DMASYNC should 
always be High. 



MMU The various registers in the MMU can be 

Commands read and written using Z8001 CPU special I/O 
commands. These commands have machine 
cycles that cause the Status lines to indicate an 
SIO operation is in progress. During these 
machine cycles the MMU enters command 
mode. In this mode, the rising edge of the 
Address Strobe indicates a command is pres- 
ent on the AD 8 -ADi 5 . If Chip Select is 
asserted and if this command indicates that 
data is to be written into one of the MMU 
registers, the data is read from ADs-ADis 
while Data Strobe is Low. If the command indi- 
cates that data is to be read from one of the 
MMU registers, the data is placed on 
AD8-AD]5 while Data Strobe is Low. 

There are ten commands that read or write 
various fields in the Segment Descriptor 
Register. The status of the Read/Write line 
indicates whether the command is a read or a 
write. 

The auto-incrementing feature of the Seg- 
ment Address Register (SAR) can be used to 
block load segment descriptors using the 
repeat forms of the Special I/O instructions. 
The SAR is autoincremented at the end of the 
field. In accessing the base field, first the 
high-order byte is selected and then the low- 
order byte. The command accessing the entire 
Descriptor Register references the fields in the 
order of base address, limit and attribute. 



Opcode (Hex) 


Instruction 


08 


Read/Write Base Field 


09 


Read/Write Limit Field 


OA 


Read/Write Attribute Field 


OB 


Read/Write Descriptor (all fields) 


0C 


Read/Write Base Field; Increment SAR 


OD 


Read/Write Limit Field; Increment SAR 


0E 


Read/Write Attribute Field; Increment 




SAR 


OF 


Read/Write Descriptor; Increment SAR 


15 


Set'All CPU-Inhibit Attribute Flags 


16 


Set All DMA-Inhibit Attribute Flags 



Three commands are used to read and write 
the control registers. 

Opcode (Hex) Instruction 

00 Read/Write Mode Register 

01 Read/Write Segment Address Register 
20 Read/Write Descriptor Selector Counter 

Register 

The Status Registers are read-only registers, 
although the Violation Type Register (VTR) 
can be reset. Nine instructions access these 
registers. 



Opcode (Hex) 

02 
03 
04 
05 
06 

07 



Instruction 

Read Violation Type Register 

Read Violation Segment Number Register 

Read Violation Offset (High-byte) Register 

Read Bus Status Register 

Read Instruction Segment Number 



Read Instruction Offset (High-byte) 
Register 

1 1 Reset Violation Type Register 

13 Reset SWW Flag in VTR 

14 Reset FATL Flag in VTR 



170 



MMU The Z8010 translates addresses and checks 

Timing for access violations by stepping through 

sequences of basic clock cycles corresponding 
to the cycle structure of the Z8001 CPU. The 
following timing diagrams show the relative 
timing relationships of MMU signals during the 
basic operations of memory read/write and 
MMU control commands. For exact timing 
information, refer to the composite timing 
diagram. 



Memory Read and Write. Memory read and 
instruction fetch cycles are identical, except 
for the status information on the ST0-ST3 
inputs. During a memory read cycle (Figure 9) 
the 7-bit segment number is input on SN0-SN6 
one clock period earlier than the address off- 
set; a High on DMASYNC during T3 indicates 
that the segment offset data is valid. The most 
significant eight bits of the address offset are 
placed on the AD0-AD15 inputs early in the 



ST0-ST3 





r, 


T 2 








x 






>c 












r— 

i 


SEGMENT NUMBER 


Y DON'T 


X 
















a r 

< 


ADORE 


SS VALID 


>— 
















\ 


/ 












\ 










MEMORY ADDRE 


— V 

ss y — 
— 1 


^ OATAIN ^ 














\ 


/ 










/ 









Figure 9. Memory Read Timing 



00-2046-03 



171 



MMU first clock period. Valid address offset data is 

Timing indicated by the rising edge of Address 

(Continued) Strobe. Status and mode information become 
valid early in the memory access cycle and 
remain stable throughout. The most significant 
16-bits of the address (physical memory loca- 
tion) remain valid until the end of T3. Segment 
Trap Request and Suppress are asserted in T2. 



Segment Trap Request remains Low until Seg- 
ment Trap Acknowledge is received. Suppress 
is asserted during the current machine cycle 
and terminates during T3. Suppress is 
repeatedly asserted during CPU instruction 
execution cycles until the current instruction 
has terminated. 



CLOCK 


T, » 


• T, » 


T, ► 

L 




HIS, 
STo-ST, 


X 






xz 












SNo-SNa < 

\— — 


SEGMENT NUMBER 


x 


x 














DMASYNC / 
—J 


\ 




/ 


\ 










u 


~\ r 

— < 








PHYSICAL ADDRESS 










/ 




SUP 




\ 








SIOT 




\ 








»D S -AD,5 


X OFFSET 


X 


DATA OUT 


x_ 












OS 
WW 


\ 


\ 


/ 


r 



Figure 10. Memory Write Timing 



172 



2046-010 



MMU MMU Command Cycle. During the command 

Timing cycle of the MMU (Figure 11), commands are 

(Continued) placed on the Address/Data lines during 1\. 

The Status lines indicate that a Special I/O 
instruction is in progress, and the Chip Select 
line enables the appropriate MMU for that 
command. Data to be written to a register in 
the MMU must be valid on the Address/Data 
lines late in T2. Data read from the MMU is 



placed on the Address/Data lines late in the 
TwA cycle. 

Input/Output and Refresh. Input/Output and 
Refresh operations are indicated by the status 
lines ST0-ST3. During these operations, the 
MMU refrains from any address translation or 
protection checking. The address lines A8-A23 
remain 3-stated. 



IDC 



\ 



S 



>• 



DATA INTO CPU 



c 



INPUT / DS 



s 



IDC 



X 



DATA OUT OF CPU TO MMU 



\ 



Figure 11. I/O Command Timing 



173 



signal; a software reset is performed by a 
Z8000 Special I/O command. A hardware reset 
clears the Mode Register, Violation Type 
Register and Descriptor Selection Counter. If 
the Chip Select line is Low, the Master Enable 
Flag in the Mode Register is set to 1 . All other 
registers are undefined. After reset, the 
AD8- AD 15 and A8-A23 lines are 3-stated. The 
SUPand SEGT open-drain outputs are not 
driven. If the Master Enable flag is not set dur- 
ing reset, the MMU does not respond to subse- 
quent addresses on its A/D lines. To enable an 
MMU after a hardware reset, an MMU com- 
mand must be used in conjunction with the 
Chip Select line. 

A software reset occurs when the Reset 
Violation Type Register command is issued. 
This command clears the Violation Type 
Register and returns the MMU to its initial 
state (as if no violations or warnings had 
occurred). Note that the hardware and software 
resets have different effects. 
Segment Trap and Acknowledge. The Z8010 
MMU generates a segment trap whenever it 
detects an access violation or a write into the 
lowest block of a segment with the DIRW flag 



siyaai oan ue useu 10 inniDii memory writes. 
The Segment Trap remains Low until a Trap 
Acknowledge signal is received. If a violation 
occurs. Suppress is asserted for that cycle and 
all subsequent CPU cycles until the end of the 
instruction; intervening DMA cycles are not 
suppressed, however, unless they generate a 
violation. Violations detected during DMA 
cycles cause Suppress to be asserted during 
that cycle only, but no Trap Request is 
generated. 

When the MMU issues a Segment Trap 
Request it awaits a Segment Trap Acknowl- 
edge. Subsequent violations occurring before 
the Trap Acknowledge is received are still 
detected and handled appropriately. During 
the Segment Trap Acknowledge cycle, the 
MMU drives one of its Address/Data lines 
High; the particular line selected is a function 
of the identification field of the mode register. 
After the Segment Trap has been acknowl- 
edged by the Z8001 CPU, the Violation 
Status Register should be read via the Special 
I/O commands in order to determine the cause 
of the trap. The Trap Type Register should also 
be reset so that subsequent traps will be 
recorded correctly. 




Figure 12. Segment Trap and Acknowledge Timing 



Pin A8-A23. Address Bus (outputs, active High, 

Description 3-state). These address lines are the 16 most- 
significant bits of the physical memory 
location. 

AD8-AD15. Address/Data Bus (inputs/outputs, 
active High, 3-state). These multiplexed 
address and data lines are used both for com- 
mands and for logical addresses intended for 
translation. 

AS. Address Strobe (input, active Low). The 
rising edge of AS indicates that AD0-AD15, 
ST0-ST3, R/W and N/S are valid. 

CLK. System Clock (input). CLK is the 5 V 
single-phase time-base input used for both the 
CPU and MMU. 

CS. Chip Select (input, active Low). This line 
selects an MMU for a control command. 

DMASYNC. DMA/Segment Number Syn- 
chronization Strobe (input, active High). A 
Low on this line indicates that the segment 
number lines are 3-state; a High indicates that 
the segment number is valid. It must always be 
High during CPU cycles. If a DMA device 
do es not use the MMU for address translation, 
the BUSACK signal from the CPU may be 
used as an input to DMASYNC. 

DS. Data Strobe (input, active Low). This line 
provides timing for the data transfer between 
the MMU and the Z8001 CPU. 

N/S. Normal/System Mode (input, Low = 
System Mode). N/S indicates the Z8001 CPU 
or Z8016 DMA is in the Normal or System 
Mode. The signal can also be used to switch 
between MMUs during different phases of an 
instruction. 



Reserved. Do not connect. 



RESET. Reset (input, active Low). A Low on 
this line resets the MMU. 

R/W. Read/Write (input, Low = write). R/W 
indicates the Z8001 CPU or Z8016 DTC is 
reading from or writing to memory or the 
MMU. 



SEGT. Segment Trap Request (output, active 
Low, open dram). The MMU interrupts the 
Z8001 CPU with a Low on this line when the 
MMU detects an access violation or write 
warning. 

SNo-SNg. Segment Number (inputs, active 
High). The SN0-SN5 lines are used to address 
one of 64 segments in the MMU; SNg is used to 
selectively enable the MMU. 

ST0-ST3. Status (inputs, active High). These 
lines specify the Z8001 CPU status. 
ST 3 -STp Definition 

Internal operation 

1 Memory refresh 

10 I/O reference 

11 Special I/O reference (e.g., to an MMU) 

10 Segment trap acknowledge 

10 1 Nonmaskable interrupt acknowledge 

110 Nonvectored interrupt acknowledge 

111 Vectored interrupt acknowledge 

10 Data memory request 

10 1 Stack memory request 

10 10 Data memory request (EPU) 

10 11 Stack memory request (EPU) 

110 Instruction space access 

110 1 Instruction fetch, first word 

1110 Extension processor transfer 

SUP . Suppress (output, active Low, open 
drain). This signal is asserted during the cur- 
rent bus cycle when any access violation 
except write warning occurs. 



3 



Figure 13. The MMU in a Z8001 System 



175 




176 



AC Characteristics 
No. Symbol 



Parameter 



Z8010 
6 MHz 
Min Max 



Z8010 
10 MHz 
Min Max 



Notes* 



8 
9 

lO- 
ll 

12 

13 

14 

15" 

16 

17 

18 

19 

20- 

21 

22 
23 
24 
25" 



36 
37 



39 
40 - 
41 
42 



TcC 
TwCh 
TwCl 
TfC 
■TrC — 



TdDSA(RDv) 

TdDSA(RDl) 

TdDSR(RDv) 
TdDSR(RDf) 
-TdC(WDv) — 
ThC(WDn) 



TwAS 

TsOFF(AS) 

ThAS(OFFn) 

-TdAS(C) 

TdDS(AS) 
TdAS(DS) 
TsSN(C) 
ThC(SNn) 

- TdDMAS(C) - 
TdSTNR(AS) 

TdC(DMA) 

TdST(C) 

TdDS(STn) 

- TdOFF(Av) — 



26 TdST(Ad) 



Clock Cycle Time 
Clock Width (High) 
Clock Width (Low) 
Clock Fall Time 

- Clock Rise Time 

DS 1 (Acknowledge) to Read Data 

Valid Delay 
DS I (Acknowledge) to Read Data 
_Float Delay 

DS I (Read) to AD Output Driven Delay 
DS I (Read) to Read Data Float Delay 

• CLK I to Write Data Valid Delay 

CLK 1 to Write Data Not Valid 

Hold Time 
Address Strobe Width 
Offset Valid to AS' I Setup Time 
AS I to Offset Not Valid Hold Time 

- AS I to CLK 1 Delay 

DS I to AS I Delay 

AS I to DS I Delay 

SN Data Valid to CLK I Setup Time 

CLK t to SN Data not Valid Hold Time 

■ DMASYNC Valid to CLKJ Delay 

Stajus (ST -ST 3 , N/S, R/W) Valid to 

AS I Delay 
CLK 1 to DMASYNC I Delay 
Status (ST -ST 3 ) Valid to CLK 1 Delay 
DS I to Status Not Valid Delay 
Offset Valid to Address Output 

Valid Delay 
Status Valid to Address Output 

Driven Delay 



DS I to Address Output Float Delay 
AS I to Addres Output Driven Delay 
CLK I to Address Output Valid Delay 



27 TdDS(Af) 

28 TdAS(Ad) 

29 TdC(Av) 

30 — TdAS(SEGT) AS 1 to SEGT I Delay 

31 TdC(SEGT> 

32 TdAS(SUP) 

33 TdDS(SUP 

34 TsCS(AS) 



CLK I toSEGT I Delay 
AS I to SUP 1 Delay 
DS I to SUP I Delay 
Chip Select Input Valid to AS 1 Setup 



35 — ThAS(CSn) - 



TdAS(C) 
TsCS(RST) 



• AS I to Chip Select Input Not Valid - 
Hold Time 
AS I to CLK I Delay 



38 ThRST(CSn) 



TwRST 
- TdC(RDv) - 
TdDS(C) 
TdC(DS) 



Chip Select Input Valid to RESET I 

Setup Time 
RESET 1 to Chip Select Input Not 

Valid Hold Time 
RESET Width (Low) 

- CLK t to Read Data Valid Delay 

DS I to CLK I Delay 
CLK I to DS I Delay 



165 
70 
70 



60 



20 

50 
35 
40 
-90- 
30 
40 
40 


-80- 
30 

15 
60 




10 



-40- 



10 
-15- 
80 

60 

80 
60 
-80- 



-90- 
75 

130 
70 

155 
-100- 

200 
90 

100 



10 
100 



2TcC 

-460 300- 



100 
40 
40 



10 

30 

20 

20 
-50- 

15 

30 

30 

~0 
-60- 

10 

10 
30 




10 
-20- 



10 
60 





2TcC 



10 
-10- 
60 

45 

60 
45 
-50- 



-60- 
45 

100 
40 

100 
-60- 

100 
55 
60 



-190- 



1 
1 
1 

-1,2- 
1,2 
1,2 
1,2 



20 




10 




NOTES: 

1. 50 pf Load. 

2. 2.2K Pull-up. 

* Units in nanoseconds (ns). 



Timing measurements are made at the following voltages: 

High Low 
Clock 4.0 V 0.8 V 

Output 2.0 V 0.8 V 

Input 2.0 V 0.8 V 

Float AV ±0.b V 



177 



tunings operating /imDient 

Temperature See Ordering Information 

Storage Temperature -65°C to + 150°C 



condition above those indicated in the operational sections 
of these specifications is not implied. Exposure to absolute 
maximum rating conditions for extended periods may affect 
device reliability. 



Standard 
Test 

Conditions 



The DC characteristics and capacitance sec- 
tion below apply for the following standard test 
conditions, unless otherwise noted. All voltages 
are referenced to GND. Positive current flows 
into the referenced pin. 

Standard conditions are as follows: 



■ +4.75 V < V cc < +5.25 V 



GND = V 

0°C < T A < +70°C 




DC Symbol Parameter Min Max Unit Condition 

Character- V CH Clock Input High Voltage V cc -0.4 V C c + 0.3 V Driven by External Clock Generator 

IStlCS c)ock Inpu( Low Vo i, age _ 3 o 45 v Driven by External Clock Generator 

V M Input High Voltage 2.0 V cc + 0.3 V 

Vil Input Low Voltage -0.3 0.8 V 

V H Output High Voltage 2.4 V Iqh = -250 fiA 

Vql Output Low Voltage 0.4 V I L = +2.0 mA 

IlL Input Leakage ±10 nA 0.4 s V ]N s +2.4V 

lOL Output Leakage ±10 /iA 0.4<V B < + 2.4 V 

Iqq Vcc Supply Current 300 mA 

NOTE: The on-chip back-bias voltaqe generator takes approximately 20 ms to pump the back-bias voltage to -2.5 V alter the power has 
been turned on. The performance of the Z8010 Z-MMU is not guaranteed during this period. 



178 



8085-0209 



Zilog 



Product Specification 



Z8016 Z8000® Z-DTC 
Direct Memory Access 
Transfer Controller 



FEATURES 

■ Memory-to-peripheral transfers up to 2.66M bytes per 
second at 4 MHz. 

■ Memory-to-memory transfers up to 1.33M bytes per 
second at 4 MHz. 

■ Two fully independent, multi-function channels. 

■ Masked data pattern matching for Search and 
Transfer-and-Search operations. 

■ Funneling option that permits mixing of byte and word 
data during transfer operations. 



GENERAL DESCRIPTION 

The Z8016 DMA Transfer Controller (DTC) is a high per- 
formance data transfer device designed to match the 
power and addressing capability of the Z8000 CPUs. In 
addition to providing block data transfer capability be- 
tween memory and peripherals, each of the two DTC 
channels can perform peripheral-to-peripheral and 
memory-to-memory transfers. A special Search mode of 
operation compares data read from memory or 
peripherals with the contents of a pattern register. A 
search can be performed concurrently with transfers or 
as an operation in itself. 

In all operations (Search, Transfer, and Transfer-and- 
Search), the DTC can operate in either Flowthrough or 
Flyby transfer mode. In the Flowthrough mode, data is 
stored temporarily within the DTC on its way from source 
to destination. In this mode transfers can be made be- 
tween a word-oriented memory and a byte-oriented 
peripheral through the bidirectional byte/word funneling 
option. In Flyby mode, data is transferred in a single step 
(from source to destination), thus providing twice the 
throughput. 

The Z8016 DTC takes full advantage of the Z8000 
memory management scheme by interfacing directly to 
the Z8010 Memory Management Unit (MMU) or the 
Z8015 Paged Memory Management Unit (PMMU). In this 
configuration, 8M bytes of logical address range are pro- 
vided for each CPU address space. Alternatively, the 



October 1988 



■ Can operate in logical address space with Zilog 
Memory Management Units, providing an 8M byte 
logical addressing range and 16M byte physical ad- 
dressing range. 

■ Programmable chaining operation provides automatic 
loading of control parameters from memory into each 
channel. 

■ Software- or hardware-controlled Wait state insertion. 

■ Z-BUStm daisy-chain interrupt hierarchy and bus- 
request structure. 



Z8016 DTC can operate independently* of an MMU, 
directly addressing up to 16M bytes of physical address 
space. 

In addition to providing a hardware WAIT input to accom- 
modate different memory or peripheral speeds, the 
Z8016 DTC allows the user to program the automatic in- 
sertion of either zero, one, two, or four Wait states for 
either source or destination addresses. Alternatively, the 
WAIT input pin function can be disabled and these 
software-programmed Wait states used exclusively. 

The Z8016 DTC minimizes CPU involvement by allowing 
each channel to load its control registers from memory 
automatically when a DMA operation is complete. By 
loading the address of the next block of control 
parameters as part of this operation, command chaining 
is accomplished. The only action required of the CPU is 
to load the address of the control parameter table into 
the channel's Chain Address register and then issue a 
Start Chain command. 

In some DMA applications, data is transferred con- 
tinuously between the same two locations. To service 
these repetitive DMA operations, base registers are pro- 
vided on each channel to reinitialize the current source 
and destination address registers. This re- initialization 
eliminates the need for reloading registers from memory 
tables. 



179 



The Z8016 DTC is directly Z-BUS compatible, and 
operates within the Z8000 daisy-chain vectored-priority 
interrupt scheme. The Demand Interleave operation 
allows the DTC to surrender the bus to the external 
system, or to alternate between internal channels. This 
capability allows for parallel operations between dual 
channels or between a DTC channel and the CPU. 

The DTC can be used to provide a central DMA function 



for the CPU or to provide dispersed DMA operations in 
conjunction with a wide variety of Z8000 Family 
peripheral controllers. 

The Z8016 DTC is packaged in a 48-pin DIP and uses a 
single + 5 V power supply. 

The Z8016 DTC pin functions and assignments are 
shown in Figures 1 and 2, respectively. 



SEGMENT 
NUMBER 



STATUS < 



BUS 
CONTROL 



BUS 
TIMING 



SN 




AD 


SN, 




AD, 


SN 2 




AD 2 


SN 3 




AD 3 


SN„ 




AD 4 


SN 5 




ADs 


SN 6 




AD 6 


SN//MMUSYNC 


AD 7 






AD 8 


ST 




ADg 


ST, 




AD,o 


ST 2 


Z8016 


ADu 


ST 3 


DTC 


AD« 


mw 




AD i3 


B/W 




ADh 


N/S 




ADis 


BUSREQ 




CSIWATf 


BAj 


DREQi. DREQ2 


BAO 


5ack,,dack 2 






EOP 


AS 






as 




INT 






IEI 






IEO 


t 

+ 5V 


t 

GND 


CLK 



DATA 



DMA 



INTERRUPT 
CONTROL 



BAI £ 


1 




48 


BUSREQ [_ 


2 




47 


BAO C 


3 




46 


+ 5V C 


4 




45 


A Do C 


5 




44 


AD, C 


6 




43 


AD 2 C 






42 


AD 3 C 


« 




41 


AD 4 L 






40 


ADsC 


10 




39 


ADeC 


11 


280 16 
DTC 


38 


ADrC 


12 


37 


ADg rj^ 


13 




36 


ADsC 


14 




35 


AD,oC 


15 




34 


AD„ □ 


16 




33 


AD«C 


" 




32 


AD, 3 C 


18 




31 


ADu C 


19 




30 


AD, 6 C 


20 




29 


SN 6 C 


21 




28 




22 




27 




23 




26 




24 




25 



IEO 

INT 

IEI 

CLK 

AS 

DS 

CSfWAIT 

R/W 

DACK, 

DACK 2 

EOP 

DREQ2 

DREQ, 

B/W 

ST 3 

ST 2 

ST, 

ST 

N/S 

SN 

SN, 

SN7/MMUSYNC 
GND 



Figure 1. Pin Functions 



Figure 2. 48-pin Dual-ln-Line Package (DIP), 
Pin Assignments 



SIGNAL DESCRIPTIONS 

AD0-AD15. Address/Data Bus (bidirectional, active 
High, 3-state) pins 5-20. These multiplexed Ad- 
dress/Data lines are used for all I/O and memory trans- 
actions. 

AS. Address Strobe (bidirectional, active Low, 3-state) 
pin 44. When the DTC is bus master the rising edge of AS 
(while DS is High) indicates that addresses are valid. 
When the DTC is not bus master, the address lines are 
sampled on the rising edge of AS. There are no timing re- 
quirements between AS as an input and the DTC clock, 
because the Z-BUS does not use a bused clock. If AS 
and DS are simultaneously Low, the DTC will be reset. 



BAI. Bus Acknowledge In (input, active Low) pin 1. 
Signals that the bus has been released for DTC control. 
In multiple-DTC configurations, the BAl pin of the 
highest-priority DTC is normally connected to the Bus 
Acknowledge pin of the CPU. Each lower-priority DTC 
has its BAI connected to the BAO of the next higher- 
priority DTC. 

BAO. Bus Acknowledge Our (output, active Low) pin 3. In 
a multiple-DMA configuration, this pin signals that no 
higher-priority DTC has requested the bus. BAI and BAO 
form a daisy chain for multiple-DTC priority resolution. 



180 



BUSREQ. B us Reque st (bidirectional, active Low, open- 
drain) pin 2. BUSREQ is used by the DTC t o obtain c on- 
trol of the bus from the CPU. Before driving BUSREQ ac- 
tive, the DTC samples this line to ensure that another re- 
quest is not already being made by another device. 
Since th e DTC internally syn chronizes the sampled 
BUSREQ signal, transitions on BUSREQ can be asyn- 
chronous with respect to the DTC clock. 

B/W. Byte/Word (output, 3-state) pin 35. This output in- 
dicates the type of data transferred on the Address/Data 
(AID) bus. A High on this line indicates a byte (8-bit) 
transfer and a Low indicates a word (16-bit) transfer. This 
signal is activated when AS goes Low and remains valid 
for the duration of the transaction. 

CLK. DTC Clock (input) pin 45. The Clock signal controls 
internal operations and the rates of data transfer. It is 
usually derived from a master system clock or an 
associated CPU clock. When the DTC is used with an 
MMU, both must be driven from the same clock signal. 
While many DTC input signals a re asy nchronous, transi- 
tions for other signals (such as WAIT inputs) must meet 
setup and hold requirements relative to the DTC clock. 
(See the timing diagrams for details.) 

CS/WAIT. Chip Select/Wait (input, active Low) pin 42. 
When the DTC is not in control of the system bus, this pin 
serves as a Chip Select (CS) input. A CPU or other exter- 
nal device uses CS to activate the DJC for reading and 
writing the DTC's internal registers. (CS can be held Low 
for multiple transfers to and from the DTC, provided that 
AS and DS are enabled for each transfer.) There are no 
timing requirements between the CS input and the DTC 
clock; the CS input timing requirements are only defined 
relative to AS. 

When the DT C is i n control of the system bus, this pin 
serves as the W AIT inp ut. Slow memories and peripheral 
devices carujse WAIT to extend DS duri ng bu s transfers. 
Unlike the CS input, transitions on the WAIT input must 
meet certain timing requirements relative to the DTC 
cloc k (see the Active State timing diagram for details). 
The WAIT function can be disabled using a control bit in 
the Master Mode register, in which case this input is 
treated as a Chip Select only and is ignored when the 
DTC is in control of the system bus. 

DACK-i, DACK 2 . DMA Acknowledge (output, active Low) 
pins 39 and 40. There is one DM A Ackn owledge line 
associated with each channel. The DACK lines are pro- 
grammed in the Channel Mode register to be pulsed, 
held active, or held inact ive du ring DMA transfers. Dur- 
ing Flyby operations the DACK line is used for two pur- 
poses. It selects the peripheral involved in the transfer, 
and it provides timing information on whe n to ac cess the 
bus. During flowthrough operations the DACK line can 
be progr ammed to be active or inactive during a DMA 
transfer. DACK is not output during chaining operations. 



DREQ-1, DREQ 2 . DMA Request (input, active Low) pins 
36 and 37. There is a DMA Request line associated with 
each channel. These lines can make transitions indepen- 
dent of the DTC clock. They are used by external logic to 
initiate and control DMA operations performed by the 
DTC. 

DS. Dafa Srrobe (bidirectional, _active Low, 3-state) pin 
43. A Low on this signal while AS is High indicates that 
the AID bus is being used to transfer data. When the CPU 
is bus master and is transferring information to or from 
the DTC, DS is a timing input used by the DTC to move 
data to or from the AID bus. 

EOP. End of Process (bidirectional, active Low, open- 
drain, asynchronous) pin 38. This line is output when a 
Terminal Count (TC) or Match Condition (MC) termination 
occurs (see Termination section). An external source 
can termi nate a DMA operation in progress by driving 
EOP Low. EOP alw ays a pplies to the active channel; if no 
channel is active, EOP is ignore d. Th e Suppress output 
of the MMU can be connected to EOP to terminate DMA 
accesses that violate the MMU protection settings. To 
provide full access protection, an external EOP is ac- 
cepted even during chaining. 

1 El. Interrupt Enable In (input, active High) pin 46. IEI is 
used with IEO to form an interrupt daisy chain when 
there is more than one interrupt-driven device. A High 
IEI indicates that no other higher-priority device has an 
interrupt under service or is requesting an interrupt. 

IEO. Interrupt Enable Out (output, active High) pin 48. 
IEO is High only if IEI is High and the CPU is not servic- 
ing an interrupt from the requesting DTC. IEO is con- 
nected to the next lower-priority device's IEI input and 
thus inhibits interrupts from lower-priority devices. 

INT. Interrupt Request (output, open-drain, active Low) 
pin 47. This signal is pulled Low when the DTC requests 
an interrupt. 

N/S. Normal/System (output, 3-state) pin 30. The N/S 
signal is activated when the DTC is bus master. The N/S 
signal indicates which memory space is being accessed 
by going High for normal memory and Low for system 
memory. 

R/W. Read/Write (bidirectional, 3-state, Low = write) pin 
41 . When the DTC is not bus master, R/W is a status in- 
put used to indicate whether data is being read from 
(High) or wj^tten to (Low) the DTC. When the DTC is bus 
master, R/W is an output used to indicate whether the 
DTC is reading or writing the addressed location. During 
Flyby DMA operations, the "Flyby peripheral" (Figure 3) 
inverts the R/W signal to determine whether it must read 
or write. 



181 



proviae me segment number tieia ot a 23-bit segmented 
address. The SN -SN 6 I/O address information can be 
used to increase the DTC's logical I/O address space 
beyond that of the CPU. In physical address configura- 
tion, these lines provide bits 23 through 17 of a 24-bit 
linear address. The 24th bit (MSB) is output on SN 7 /MMU 
Sync. 

SN7 or MMU Sync. Segment Number 7 or MMU Sync 
(output, 3-state) pin 27. In a logical address space con- 
figuration (with MMU), this line outputs an active High 
pulse prior to each machine cycle. The MMU uses this 
signal to synchronize access to its translation table and 
to differentiate between CPU and DTC control. The MMU 
ignores MMUSYNC if the status lines (ST -ST 3 ) indicate 



the Master Mode register is set. 

In a physical address space configuration (without 
MMU), this line outputs SN 7 , which becomes the 24th 
address bit in a linear address space. The 24-bit linear 
address configuration allows the DTC to access 16M 
bytes of memory. This pin floats to the high impedance 
state when the DTC is not bus master and the MM1 bit is 
cleared. 

ST0-ST3. Status (bidirectional, 3-state) pins 31-34. 
When the DTC is bus master, these lines are outputs in- 
dicating the type of memory or I/O transaction being per- 
formed. When the DTC is not bus master, the status lines 
are inputs used to detect Interrupt and Segment Trap 
Acknowledge cycles (Table 1). 



Table 1. Status Codes 



Status Code 



ST 3 


ST 2 


ST, 


ST„ 


Transaction/Operation 


Generated/Decoded 














Internal Operation 













1 


Memory Refresh 










1 





I/O Transaction 


Generated 








1 


1 


Special I/O Transaction 


Generated 





1 








Segment Trap Acknowledge 


Decoded 





1 





1 


Nonmaskable Interrupt Acknowledge 


Decoded 





1 


1 





Nonvectored Interrupt Acknowledge 


Decoded 





1 


1 


1 


Vectored Interrupt Acknowledge 


Decoded 













Memory Transaction for Data/DTC Chaining 


Generated 










1 


Memory Transaction for Stack 


Generated 







1 





Reserved 









1 


1 


Reserved 






1 








Memory Transaction for Program Fetch (Subsequent Word) 


Generated 




1 





1 


Memory Transaction for Program Fetch (First Word) 






1 


1 





Reserved 






1 


1 


1 


Reserved 





FUNCTIONAL DESCRIPTION 

Channel Initialization 

The Z8016 DTC operates with a minimum of interaction 
with the host CPU. Each channel's operation is deter- 
mined by the settings of its own set of control registers. 
Each channel is initialized when the DTC loads its con- 
trol parameters from memory into its control registers 
during the chaining operation. To initiate the chaining 
operation, the CPU is required to program the Master 
Mode register and each channel's Chain Address 
register. Then each channel's control registers are 
automatically loaded by the DTC with control 
parameters stored in a chain control table in memory, 
located at the address pointed to by that channel's Chain 
Address register. Once the channel registers are loaded, 
the DTC is ready to perform DMA operations. 



Initiating DMA Operations. DMA operations can be 
initiated in three ways: 

■ Software Request. The CPU can issue Software Re- 
quest commands to start DMA operations on a 
specific channel. This channel must then request con- 
trol of the bus and perform transfers. 

■ Hardware Request. DMA o perations can be started by 
forcing a channel's DREQ input Low, as described in 
the Transfer Modes section. 

■ Starting After Chaining. If the Software Request bit of 
the Channel Mode register is loaded with a 1 during 
chaining, the channel will perform the programmed 
DMA operation at the end of chaining. If the channel is 



182 



programmed for Single Operation or Demand mode, it 
will perform the operation immediately. The channel 
will give up the bus after chaining and before the 
operation if the CPU Interleave bit in the Master Mode 
register is set. Note that once a channel starts a 
chaining operation by fetching a reload word, it re- 
tains bus control at least until all of the registers 
specified in the reload word have been loaded from 
memory. 

Transfers 

The Z8016 DTC uses three basic types of operation: 
Transfer, Search, and Transfer-and-Search. 

During a Transfer operation, the DTC obtains control of 
the system AID bus from the CPU. Data is read from one 
addressable port (source) and is written to another ad- 
dressable port (destination) in words or bytes. This ap- 
plies to both Flyby and Flowthrough transfers. 



Flyby transfers use a single addressing/transfer cycle, in 
which data is transferred directly from the source to the 
destination with no intermediate storage (Figure 3). This 
method of transfer provides higher throughput than 
Flowthrough transfers but cannot be used for memory- 
to- memory transfer. 

Flowthrough transfers are used for all combinations of 
addressable memory and I/O spaces. These transfers 
use independent double Addressing/Transfer cycles, in 
which data is stored temporarily in the DTC while being 
transferred from source to destination (Figure 4). 
Flowthrough transfers can use the tunneling option, 
which allows mixing of data sizes between source and 
destination. For example, a byte-oriented peripheral can 
conveniently supply data to a word-oriented memory. 
This option requires no added circuitry for either 
memory or peripherals. 



I/O OR 
MEMORY 



Z8016 
DTC 



MEMORY 
ADDRESS" 



DACK 



FLYBY 
PERIPHERAL 
(e.g., FIO) 



DATA- 



SYSTEM BUS 



Figure 3. Configuration of a Flyby Transaction 



PERIPHERAL 
OR 
MEMORY 



Z8016 
DTC 



TEMPORARY 
REGISTER 



PERIPHERAL 
OR 
MEMORY 



SYSTEM BUS 



Figure 4. Configuration of a Flowthrough Transaction 



183 



During a Search operation, data is read from the source 
port and compared byte-by-byte with a pattern register 
containing a programmable match byte. The Search 
operation can be programmed to stop either when the 
read data matches (Stop-on- Match) or when it fails to 
match the masked pattern (Stop-on-No-Match). For 
word reads, the Channel Mode register can be used to 
select either 8- or 16-bit compares. 

Transfer-and-Search operations combine the transfer 
and search functions to facilitate the transfer of variable- 
length data blocks. While data is being transferred be- 
tween two ports, a simultaneous search is made for a 
bit-maskable byte match. Transfer-and-Search can be 
performed in either Flowthrough or Flyby mode. A Flyby 
Transfer-and-Search can be used to increase 
throughput for transfers between peripherals or between 
memory and a peripheral; it cannot be used for memory- 
to-memory transfers. 

Transfer Modes. The Z8016 DTC operates in either of 
two transfer modes: Single or Demand. The Demand 
mode is further divided into the Demand Dedicated with 
Bus Hold, Demand Dedicated with Bus Release, and De- 
mand Interleave modes. 

The Single mode is used with peripherals that transfer 
single bytes or words at irregular intervals. Each Soft- 
ware Request command causes the channel to perform 
a single DMA operation and each application of a High- 
to-Low transition on the DREQ input also initiates a DMA 
operation. Each time a Single mode DMA operation 
ends, the channel relinquishes the bus unless a new 
transition has occurred on DREQ. 

In the Demand mode, when the DREQ input is active, 
transfer cycles are executed repeatedly until the 
transfer is completed. In the Demand Dedicated with 
Bus Hold mode, the active channel retains control of the 
bus until the transfer is complete, even after the DREQ 
input has gone inactive. In the Demand Dedicated with 
Bus Release mode, the ac tive channel releases control 
of the bus when the DREQ input goes inactive. When the 
DREQ input becomes active again, control of the bus is 
re-acquired and the transfer operation continues. 

The Demand Interleave mode has two options, program- 
mable in the Master Mode register bit MM2. If MM2 is 
set, the DTC relinquishes and re- requests bus control 
after every DMA operation. 

This permits the CPU and other devices to gain bus con- 
trol. If both channels receive active DREQ inputs, each 



channel relinquishes control to the CPU after each 
operation. In the second option (MM2 is 0), control can 
pass from one channel to the other without requiring the 
DTC to rele ase bus control. If both channels receive ac- 
tive DREQ inputs, control alternates between channels 
and the DTC retains bus control until all channel opera- 
tions are complete. 

Wait States. The Z8016 DTC can insert Wait cycles in- 
to the DMA Transacti on cy cle under hardware or soft- 
ware control. The CS/WAIT input can be multiplexed to 
function as a Chip Select for the DTC w hen it does not 
have control of the bus, and as a WAITjnput when the 
DTC is the bus controller. Multiplexing CS and WAIT re- 
quires external logic, but the DTC can be programmed to 
insert Wait states automatically without external logic 
when accessing either I/O or memory addresses. Either 
zero, one, two, or four Wait states can be added. Wait 
states can be programmed separately for the Current 
Address registers and for the Chain Address register. 
Programmable Wait cycle insertion allows memories 
and peripherals of different speeds to be associated with 
I/O and memory addresses. 

Interrupts. On the Z8016 DTC, each channel is an inter- 
rupt source and has its own vector register for identify- 
ing the source of the interrupt during a CPU/DTC Inter- 
rupt Acknowledge transaction. An interrupt can result 
from a Match Condition (MC), End-Of-Process (EOP), or 
Terminal Count (TC) on either channel. The user selects 
the action to be performed by setting bits in the Channel 
Mode register. 

Three bits in each channel's Status register control inter- 
rupts. These are the Channel Interrupt Enable (CIE) bit, 
the Interrupt Pending (IP) bit, and the Interrupt Under 
Service (IUS) bit. 

Devices connected to any of the CPU's three interrupt 
inputs resolve priority conflicts with an interrupt daisy 
chain, as shown in Figure 5. The daisy chain has two 
functions. During an Interrupt Acknowledge transaction, 
it determines which interrupt source is being 
acknowledged. At all other times, it determines which in- 
terrupt sources can initiate an interrupt request. 

The Z8016 DTC has an interrupt queuing capability, 
which includes a two-deep interrupt queue on each 
channel. This allows the DTC to continue normal opera- 
tion between the time an interrupt is issued and the time 
the Interrupt Acknowledge is received. 






VI 




NVi 




NMI 


CPU 




ST0-ST3 





TO LOWER 
" DEVICES 



Figure 5. Interrupt Daisy Chain 



2129-005 



185 



operation can end and two ways a Transfer operation can 
end. When a channel's Current Operation Count goes to 0, 
the DM A operation ends; this is called a Terminal Count (TC) 
termination. A DMA operation can also be stopped by 
driving the EOP pin Low with external logic; this is called an 
EOP termination. Match Condition (MC) is the last method of 
termination which occurs when the data being 
Transferred-and-Searched or Searched meets the match 
condition programmed in Channel Mode register bits 
CM-|7-CM 16 . These bits allow the user to stop when a match 
occurs between the unmasked Pattern register bits and the 
data read from the source, or when a no-match occurs. Both 
byte and word matches are supported. MC terminations do 
not apply to Transfer operations since the pattern matching 
logic is disabled in Transfer mode. 

End of Process 

The End-of-Process (EOP) int erfac e pin is a bidirectional 
signal. Whenev er a T C, MC, or EOP termination occurs, the 
DTC drives the EOP pin Low. During DMA o perati ons, the 
EOP pin is sampled by the DTC to determine if EOP is being 
drive n Low by external logic. Figure 1 9 shows when internal 
EOPs are generated marking termination of all Transfers and 
when the EOP pin is s ampl ed during the DMA iteratio n. Th e 
generation of internal EOPs and sampling of external EOPs 
for Transfer-and-Searches follow s the same timing used for 
Transfers. Since there is a single EOP pin for both channels, 
EOPs should only be driven Low by a channel while that 
channel is bein g serv iced. This can be accomplished by 
selecting a leve l PACK outp ut (CMR 18 = 0) and gating each 
channel's EOP request with DACK, as shown in Figure 5A 



OREd 
DACK i 










PERIPHERAL 1 








Z8516/Z9516 
DTC 

EOP 


f-^rVv + 5V 






OREO! 
DACK 2 










PERIPHERAL 2 









SYSTEM BUS 



Notes: 

1. External E OP st ops channel. 

2. DTC drives EOP Active on T C and MC. 

3. Channel should apply EOP only it its DACK is active. 

Figure 5A. EOP Connection 

If an EOP is detected while the channel is trying to reload the 
Chain Address register, the new Chain Address Offset and 
Segment are discarded and the old address +2 is 
preserved to allow inspection of the erroneous address. 



completion Status held ot the channels Status register 
(Figure 7). This information is retained until the next DMA 
operation ends at which time the Status register is updated 
to reflect the reason(s) for the latest termination. More than 
one bit in the Completion Field could be set to 1 . All three of 
the channel's Status register completion bits would be set to 
1 under the following conditions; If a channel decremented 
its Current Operation Count to causing a TC termination, 
input data from the source generat ed a match causing an 
MC t ermination, and a Low on the EOP pin resulted in an 
EOP termination. 

When a DMA operation ends, the channel can: 

(a) Issue an Interrupt request (i.e., setting the IP or SIP bit of 
the channel's Status register) 

(b) Perform Base-to-Current reloading 

(c) Chain reload the next DMA operation 

(d) Perform any combination of the above or 

(e) None of the above 

The user selects the action to be performed by the channel 
in the Completion option field of the Channel Mode register. 
For each type of termination (TC, MC or EOP) the user can 
choose which action or actions are to be taken. If no 
reloading is selected for the type of termination that 
occurred, the NAC bit in the Status register is set. 

More than one action can occur when a DMA operation 
ends. This may arise because more than one action was 
programmed for the applicable termination. The priorities of 
those actions are Interrupt request, Base-to-Current 
reloading, and chaining. The Interrupt cannot be serviced 
unless the DTC has relinquished the bus. 

Interrupts 

To permit the DTC to begin a new DMA operation after 
issuing an interrupt but before the CPU acknowledges that 
interrupt, a two-deep interrupt queue is provided on each 
channel of the DTC. Interrupt handling by the Z8000 
microprocessor is summarized in this section, followed by a 
brief discussion of the DTC's queuemg capability and its 
implications for the system. 

A complete Interrupt cycle on the Z8000 CPU consists of an 
Interrupt Request followed by an Interrupt Acknowledge 
transaction. The request, which consists of the CPU's 
Interrupt pin being pulled Low by a peripheral, notifies the 
processor that an interrupt is pending. The Interrupt 
Acknowledge cycle, initiated by the CPU as a result of the 
interrupt request, performs two functions: it selects the 
peripheral whose interrupt is to be acknowledged and it 
obtains a vector that identifies the device involved and the 
reason for the interrupt. 



186 



The DTC has two sources of interrupt. Each source has 
three bits that control its interrupt generation. These bits are 
the Channel Interrupt Enable (CIE), Interrupt Pending (IP), 
and Interrupt Under Service (IUS) bits. Since each channel 
on the DTC contains all three of these bits (bits CM-i 5-CM 13), 
they are seen by the CPU as two separate interrupt sources. 
Each channel also has its own vector register for identifying 
the source of the interrupt during an Interrupt Acknowledge 
interchange with the CPU. The Disable Lower Chain (DLC) 
and No Vector (NV) bits in the DTC's Master Mode register 
control this behavior for the entire chip. 

Once a channel issues an interru pt, it is desirable to allow the 
channel to proceed with the next DMA operation before the 
interrupt is acknowledged. This could lead to problems if the 
DTC channel attempted to chain reload the Vector register 
contents. In such a situation, it may not be clear whether 
the old or new vector would be returned during the 
acknowledge. This dilemma is resolved in the DTC by 
providing each channel with an Interrupt Save register. 
When the channel sets IP as part of the procedure followed 
to issue an interrupt, the contents of the vector register and 
some of the Status register bits are saved in an I nterrupt Save 
register (Figure 9). When an Interrupt Acknowledge cycle is 
performed, the contents of the Interrupt Save register are 
driven onto the bus. Although the use of an Interrupt Save 
register allows the channel to proceed with a new task, 
problems can still arise if a second interrupt is to be issued 
by the channel before the first interrupt is acknowledged. To 
avoid conflicts between the first and second interrupt, each 
channel has a Second Interrupt Pending (SIP) bit in its Status 
register. When a second interrupt is issued before the first 
interrupt is acknowledged, the SIP bit is set and the channel 
relinquishes the bus until an acknowledge occurs. For 
compatibility with polled interrupt schemes, the Interrupt 
Save register can be read without wait states by the host 
CPU. As an aid to debugging a system's interrupt logic, 
whenever IP is set, the Interrupt Save register is loaded from 
the Vector and Status registers. 

Note that the SIP bit is transferred to the IP bit when IP is 
cleared by the host CPU. Whenever CIE is set, INT goes Low 
when IP is set. 

Base-to-Current Reloading. When a channel finishes a 
DMA operation, the user may select to perform a 



Base-to-Current Reload. (Base-to-Current reloading is also 
referred to as Auto-reloading in this document.) In this type 
of reload, the Current Address registers A and B are loaded 
with the data in the Base Address registers A and B 
respectively, and the Current Operation Count register is 
loaded with the data in the Base Operation Count. The 
Base-to-Current reload operation facilitates repetitive DMA 
operations without the multiple memory accesses required 
by chaining. Although the channel must have bus control to 
perform Base-to-Current reloading, the complete reloading 
operation occurs in four clock cycles (TAU ( through TAU 4 ). If 
the channel has to relinquish the bus because two 
unacknowledged interrupts are queued, it has to regain bus 
control to perform any Base-to-Current reloading (or 
chaining). In this case it acquires the system bus once an 
interrupt acknowledge is received, even if it immediately 
afterward relinquishes the bus because no hardware or 
software request is present. 

Chaining. If the channel is programmed to chain at the end 
of a DMA operation, it uses the Chain Address register to 
point to a Chain Control Table in memory. The first word in 
the table is a Reload word, specifying the register(s) to be 
loaded. Following the Reload word are the data values to be 
transferred into the register(s). Chaining is described in 
detail in the Channel Initialization section. 

Because chaining occurs after Base-to-Current reloading, it 
is possible to reset the Current Address registers A and B 
and the Current Operation Count register to the values used 
for previous DMA operations and then chain reload one or 
two of these registers to some special value. If the Base 
values are not reloaded during chaining, the channel can 
revert back to the Base values at a later cycle. 

If an all zero Reload word is fetched during chaining, the 
chain operation does not reload any registers but performs 
like any other chaining operation. Thus, the Chain Address 
is incremented by 2 to point to the next word in memory and, 
at the end of the all Zero-Reload word chain operation, the 
channel is ready to perform a DMA operation. All zero 
Reload words are useful as "Stubs" to start or terminate 
linked lists of DMA operations traversed by chaining. Care 
must be taken in their use since the channel may perform an 
erroneous operation if it is unintentionally started after the 
chaining operation. 



MEMORY MANAGEMENT 

The DTC can be configured to operate in physical ad- 
dress space or logical address space. When the DTC is 
operated in logical address space, the segment and off- 
set portions of the address registers combine to form 
23-bit logical addresses. In conjunction with a CPU, DMA 
operations can be handled through the Z8010 MMU. 

MMUs offer dynamic segment reloca- 
tion, segment protection, and other memory manage- 
ment features. 



In the physical address space configuration, the seg- 
ment and offset portions of the DTC's address registers 
are combined with the SN 7 output to form a single 24-bit 
linear address. The extended I/O addressing capability 
of the DTC can be used to increase the DTC's physical 
I/O address space beyond that of the CPU. Figure 6 il- 
lustrates various DTC configuration options with the 
Z8000 CPUs and MMUs. 



187 



DTC WITH Z8001 (SEGMENTED) CPU 



Z8001 
CPU 




Z8016 
DTC 








[I 



h 16- 



OFFSET 



SYSTEM BUS 



DTC WITH Z8002/4 (NONSEGMENTED) CPU 



Z8002 




Z8016 


CPU 




DTC 



SYSTEM BUS 



OFFSET 



DTC WITH Z8001 (SEGMENTED) CPU AND MMU 



Z8001 




Z8016 


CPU 




DTC 



1L 



-16- 



OFFSET 



Z8010 
MMU 



-24- 



LINEAR ADDRESS 



SYSTEM BUS 



Figure 6. DTC Configurations 



188 



INTERNAL STRUCTURE 



The internal structure of the Z8016 DTC includes driver services all internal logic and registers, as illustrated in 
and receiver circuitry for interfacing with Zilog's Z-BUS. the DTC block diagram (Figure 7). 
The DTC's internal bus interfaces with the Z-BUS and 



EXTERNAL BUS 




INTERFACE 
TO 

PERIPHERALS 



Figure 7. DTC Block Diagram 



REGISTER DESCRIPTION 

The DTC contains chip-level control registers as well as 
channel-level registers that are duplicated for each 
channel. Registers on the DTC that can be read by the 
CPU are either fast- or slow- readable. CPU I/O instruc- 
tions can read fast-readable registers without Wait 
states. Slow- readable registers can be read by the CPU 
only if Wait states are inserted. This requires external 
logic to gener ate an d time the application of Low signals 
on the CPUs WAIT input if the slow-readable registers 
are to be read. 

Control Registers 

The four control registers direct the functioning of the 
DTC. (Figure 8.) 

Master Mode Register. This register selects the way in 
which the DTC interfaces to the system. The following 
descriptions indicate how the individual bits in the 
Master Mode register are used. The Master Mode 
register is fast- readable. 

Chip Enable (CE). The setting of this bit enables the DTC 
to request the bus, perform DMA operations and reload 
registers. 



Logical/Physical Address Space (LPA). The setting of 
this bit determines how the system will view the segment 
and offset portions of the Current ARA and ARB 
registers. When LPA is set to 1 (Logical Address Space), 
the segment and offset portions of the Current ARA and 
ARB registers are treated as separate portions of the ad- 
dress. The 16-bit offset portion of the address will ap- 
pear on pins AD0-AD15 when AS is Low. The 7-bit seg- 
ment number appears on pins SN -SN6 for the duration 
of the transaction. 

When this bit is set to (Physical Address Space), the 
segment and offset portions of the Current ARA and ARB 
registers are treated as a single address and all eight 
segment bits in the register are used. Both the I/O and 
the memory addresses in Physical Memory Space are 
generated by loading the offset portion of the Current Ad- 
dress register onto the AD0-AD-15 bus and the segment 
portion of that register onto the SN -SN 7 bus. (In con- 
junction with the nonsegmented Z8000 CPUs, either 
Logical or Physical Address Space setting may be used.) 

Wait Line Enable (WLE ). This bit is set to enable sam- 
pling of the CS/WAIT line during memory and I/O 
transactions. 



189 



DLC is 0, the DTC generates Low and High signals on the 
IEO output in response to IEI. 

No Vector on Interrupt (NVI). This bit determines 
whether the DTC channel or a peripheral returns a vec- 
tor during Interrupt Acknowledge cycles. While the bit is 



the AID bus while DS is Low. While this bit is set, inter- 
rupts are serviced in an identical manner, but the A/D 
bus remains in a high impedance state throughout the 
Acknowledge cycle. 



MASTER MODE REGISTER 



COMMAND REGISTER 



D, D 6 D 5 D, 



1 P3 | P 2 1 Pi j Dpi 



NVI ACKNOWLEDGE 

VI ACKNOWLEDGE 

NMi ACKNOWLEDGE 
SEGMENT TRAP 
ACKNOWLEDGE 



CHIP ENABLE 

LOGICAL/PHYSICAL 
ADDRESS SPACE 

CPU INTERLEAVE 
ENABLE 

WATT LINE ENABLE 
DISABLE LOWER CHAIN 
NO VECTOR ON INTERRUPT 



j D, I D 6 I D 5 I D, I D 3 I D 2 I D, [ d7| 


















1 





1 








1 


1 


1 








1 





1 


1 


1 





1 


1 


1 



CHANNEL 2/CHANNEL 1 
• SET/CLEAR 
■ INTERRUPT PENDING 

- INTERRUPT UNDER SERVICE 

- INTERRUPT ENABLE 



RESET 

INTERRUPT CONTROL 
SOFTWARE REQUEST 
FLIP BIT 

HARDWARE MASK 
START CHAIN 
NOT RECOGNIZED 
NOT RECOGNIZED 



CHAIN CONTROL REGISTER 

(CHAIN LOADABLE ONLY) 
(WRITE ONLY) 



| D9 | Da | P7 | D6 | D5 | D« | D3 | D2 | Pi Pol 



CHAIN ADDRESS (2 WORDS) 
CHANNEL MODE (2 WORDS) 
INTERRUPT VECTOR (1 WORD) 
PATTERN AND MASK (2 WORDS) 
BASE OP-COUNT (1 WORD) 
BASE ARB (2 WORDS) 
BASE ARA (2 WORDS) 
CURRENT OP-COUNT (1 WORD) 
CURRENT ARB (2 WORDS) 
CURRENT ARA (2 WORDS) 



TEMPORARY REGISTER 



[d^ D 1a D13 D12I D11 Dip [ D 9 j D 8 I D7 I De I P5 I P4 j P3 D2 | Pi "dq\ 



190 



Figure 8. Control Registers 



2129008 



Interrupt Acknowledge Field (two bits). This field is used 
to select the type of Interrupt Acknowledge cycle the 
DTC is to respond to. The setting of this field must cor- 
respond to the IEI/IEO daisy chain on which the DTC is 
located. The DTC can respond to Nonmaskable Interrupt 
(NMI), Nonvectored Interrupt (NVI), or Segment Trap 
Acknowledge cycles. 

CPU Interleave Enable. When this bit is set, interleaving 
of bus use between the CPU and the DTC is enabled. 

Chain Control Register. This 16-bit register specifies 
which registers are to be loaded from memory during a 
chaining operation. The Chain Control register is loaded 
from the memory location pointed to by the Chain Ad- 
dress register. The Chain Control register is chain 
loadable only and cannot be accessed by the CPU. 

Command Register. The Command register is an 8-bit 
write-only register written to by the host CPU to execute 
commands. The Command register is loaded from the 
data on AD7-AD0; the data on ADis-ADg is disregarded. 

Temporary Register. This 16-bit register is used to 
hold data during Flowthrough transfers, Search opera- 
tions, and Transfer-and-Search operations. The Tem- 
porary register cannot be written or read by the CPU. 

Channel- Level Registers 

Each of the DTC's two channels has a complete set of 
channel-level registers. This set consists of both 
General-Purpose and Special-Purpose registers, as il- 
lustrated in Figure 9. The General-Purpose registers are 
commonly found on DMA devices and can be read or 
written by the CPU. The Special-Purpose registers pro- 
vide additional features specific to the Z8016 DTC. 

General-Purpose Registers. The General-Purpose 
register set on each channel consists of the Current Ad- 
dress registers A and B, the Base Address registers A 
and B, the Base and Current Operation Count registers, 
and the Channel Mode register (Figure 10). 

Current and Base Address Registers A and B. The 

Current Address registers A and B are used to point to 
the source and destination for DMA operations. The con- 
tents of the Base Address registers A and B are transfer- 
red into the Current Address registers A and B at the end 
of a DMA operation if the user enables base-to-current 
reloading in the Completion field of the Channel Mode 
register. The base-to-current reload operation facilitates 
repetitive DMA operations without the multiple memory 
accesses required by chaining. 

Each of the Base and Current Address registers A and B 
consist of two words. The first word contains a 7-bit Tag 
field and an 8-bit Segment Number field. The second 
word contains a 16-bit offset. The use of the Tag field is 



described below. The use of the Segment Number field 
depends upon the setting of the LPA bit in the Master 
Mode register. The Base and Current Address registers 
are fast- readable and can be loaded by chaining. 

Programmable Wait Field. This field allows the insertion 
of zero, one, two, or four Wait states into memory or I/O 
accesses addressed by the offset and segment fields. 

Address Control Field. At the end of each iteration of a 
DMA operation, the address can be incremented, 
decremented, or left unchanged. Memory addresses are 
changed by one if the address points to a byte operand 
or by two if the address points to a word operand. 

Address Reference Field. This portion of the Tag field is 
used to select whether the address pertains to memory 
space or I/O space. The N/S output line is always Low 
(indicating System) for I/O space but can be either High 
(Normal) or Low (System) for memory space. 

Current and Base Operation Count Registers. The 

16-bit Current Operation Count register specifies the 
number of words or bytes to be transferred, searched, or 
transferred-and-searched. For word-to-word operations 
and byte-word tunneling, this register must be program- 
med with the number of words to be transferred or 
searched. 

The Base Operation Count register reinitializes the cur- 
rent source and destination in the Current Operation 
Count register. Each time data is transferred or search- 
ed, the Current Operation Count register is decremented 
by one. Once all of the data is transferred or searched, 
the Current Operation Count register will contain zero. If 
the transfer on search stops before the Current Opera- 
tion Count register reaches zero, the contents of the 
register indicate the number of bytes or words remaining 
to be transferred or searched. This allows a channel to 
be restarted from where it left off without requiring 
reloading of the Current Operation Count register. The 
Current and Base Operation Count registers are slow- 
readable and can be loaded by chaining. 

Channel Mode Register. This register selects the type 
of DMA operation the channel is to perform, how the 
operation is to be executed, and what action is to be 
taken when the operation finishes. The Channel Mode 
register is slow- readable and can be loaded by chaining. 

Data Operation and Transfer Type Field. These fields 
are used to select the type of operation the channel is to 
perform along with the operand size. The specific codes 
are listed in Tables 2 and 3. The Flip bit is used to select 
which of the Current Address Registers A (ARA), or B 
(ARB), points to the source and which points to the 
destination address. 



191 



DTC INTERNAL 
BUS 











CURRENT 
ADDRESS REGISTER A 






CURRENT OPERATION 
COUNT REGISTER 










BASE 

ADDRESS REGISTER A 


BASE OPERATION 
COUNT REGISTER 










CURRENT 
ADDRESS REGISTER B 


CHANNEL MODE 
REGISTER 












BASE 

ADDRESS REGISTER B 









GENERAL-PURPOSE CHANNEL REGISTERS 



PATTERN 
REGISTER 



MASK 
REGISTER 



CHAIN ADDRESS 
REGISTER 



DTC INTERNAL 
BUS 



STATUS 
REGISTER 



INTERRUPT 
SAVE REGISTER 



INTERRUPT 
VECTOR REGISTER 



SPECIAL-PURPOSE CHANNEL REGISTERS 



Figure 9. Channel-Level Registers 



192 



2129-009 



BASE AND CURRENT ADDRESS 
REGISTERS A AND B 



c 












1 


1 





1 


1 



WAIT STATES 

1 WAIT STATE 

2 WAIT STATES 
4 WAIT STATES 












1 


1 


X 



INCREMENT ADDRESS 
DECREMENT ADDRESS 
HOLD ADDRESS 


















1 





1 








1 


1 


1 








1 





1 


1 


1 





1 


1 


1 



SYSTEM DATA MEMORY 
SYSTEM STACK MEMORY 
SYSTEM PROGRAM MEMORY 
I/O 

NORMAL DATA MEMORY 
NORMAL STACK MEMORY 
NORMAL PROGRAM MEMORY 
SPECIAL I/O 



BASE AND CURRENT OPERATION COUNT REGISTERS 

\d7s D m |Di 3 |d 12 Dn Dip D 9 Ds D7 Ds | D5 D4 | D 3 D2 | Pi | Dp | 



CHANNEL MODE REGISTER 



CHAIN 
ENABLE 

B TO C 
RELOAD 
ENABLE 



INTERRUPT 
ENABLE 





D4 1 D 3 1 D 2 


D1 


Do 


1 



■ match control field 

■ pulsed Back 
hardware request mask 

■ software request 



Pi5|Di4|Di3[dT2 D11 Dio| D9 08 | D7 | De 



TC 
MC - 

EOP - 
TC - 
MC - 

EOP - 
TC - 
MC " 

EOP " 



J 



D 5 | D 4 | D 3 | D2 | D1 | Do I 



■ DATA OPERATION FIELD 

- FLIP BIT 

(0) — ARA = src, ArB = dst 

(1) -ARA = dst, ArB m src 

■ TRANSFER TYPE FIELD 



Figure 10. General-Purpose Channel Registers 



2129-010 



193 





Operand Size 


Transaction 


Code/Operation 


ARA ARB 


Type 


Transfer 


0001 


Byte Byte 


Flowthrough 


100X 


Byte Word 


Flowthrough 


0000 


Word Word 


Flowthrough 


0011 


Byte Byte 


Flyby 


0010 


Word Word 


Flyby 


Transfer- and- Search 


0101 


Byte Byte 


Flowthrough 


110X 


Byte Word 


Flowthrough 


0100 


Word Word 


Flowthrough 


0111 


Byte Byte 


Flyby 


0110 


Word Word 


Flyby 


Search 


1111 


Byte Byte 


N/A 


1110 


Word Word 


N/A 


101X 


Illegal 





Completion Field. This field is used to program the ac- 
tion taken by the channel at the end of a DMA operation. 
When a DMA operation ends, the channel can perform 
any combination of the following options: 

■ Interrupt the CPU (Interrupt Enable field) 

■ Base-to-Current reload (B to C Reload field) 

■ Chain reload the next DMA operation (Chain Enable 
field) 

The options are performed according to the bits set in 
the Interrupt Enable, B to C Reload, and Chain Enable 
fields for each type of termination that occurs; the NAC 
bit in the Status register is automatically set on comple- 
tion of a DMA operation. 

Match Control Field. This 2-bit field determines whether 
matches use an 8-bit or 16-bit pattern and whether the 
channel is to Stop-On-Match or Stop-On-No-Match. The 
specific codes for the Match Control field are listed in 
Table 3. 



Table 3. Transfer Type Field and Match Control Field 



Code 


Transfer Type 


Match Control 


00 


Single Transfer 


Stop on No Match 


01 


Demand Dedicated/Bus Hold 


Stop on No Match 


10 


Demand Dedicated/Bus 






Release 


Stop on Word 






Match 


11 


Demand Interleave 


Stop on Byte Match 



active whenever the channel is performing a DMA 
operation, regardless of the type of transaction. While 
the PD bit is set, the DACK pin is inactive during chain- 
ing, Flowthrough Transfer s, Flow through Transfer-and- 
Searches, and Searches. DACK is pulsed active during 
Flyby Transfers and Flyby Transfer-and-Searches at the 
time necessary to strobe data into, or out of, the Flyby 
peripheral. 

Hardware Request Mask (HRM). If this bit is set, a DMA 
operation can be started by applying a Low on the chan- 
nel's DREQ input. 

Software Request (SR). If this bit is set during chaining, 
the channel performs the programmed DMA operation at 
the end of the chaining operation. 

Special Purpose Registers. The Special-Purpose 
registers on each channel are the Pattern and Mask 
registers, the Status register, the Interrupt Vector 
register, the Interrupt Save registers, and the Chain Ad- 
dress register (Figure 11). 

Pattern and Mask Registers. These registers are used 
in Search and Transfer-and-Search operations. The Pat- 
tern register contains the pattern that the read data is 
compared to. The Mask register allows the user to ex- 
clude or mask selected Temporary register bits from 
comparison by setting the corresponding Mask register 
bit to 1. The Pattern and Mask registers are slow- 
readable and can be loaded by chaining. 

Status Register. The Status register on each channel 
reports the status of that channel. The functions of the 
individual bits are indicated in the following field descrip- 
tions. The Status register is fast- readable. 

Completion Status Field. Three bits indicate whether the 
DMA operation ended as a result of TC, MC, or EOP. The 
TC bit is set if the Operation Count (reaching zero) ends 
the DMA operation. The MC bit is set if a pattern match 
termination occurs. The EOP bit is set when an EOP ter- 
mination ends a DMA transfer. The appropriate combina- 
tion of the TC, MC, and EOP bits is set if multiple reasons 
exist for ending a DMA operation. The Match Condition 
High byte (MCH) and Match Condition Low byte (MCL) 
bits report the match states of the upper and lower com- 
parator bytes of the last word transferred. The MCH and 
MCL bits are updated with each transfer. 

These bits are set when the associated comparator 
bytes are matched, regardless of whether Stop-on- 
Match or Stop-on-no-Match is programmed. 

Hardware Interface Status Field. The Hardware Re- 
quest (HR Q) bit provides a me ans of monitoring the 
channel's DREQ input line. While DREQ is Low, the HRQ 
bit is set. While the Hardware Mask (HM) bit is s et, the 
DTC is prevented from responding to a Low on the DREQ 
line. H owever, the HRQ bit always reports the status of 
DREQ regardless of the status of the HM bit. 



194 



DTC Status Field. This field reports the current channel 
status to the CPU. The "channel initialized and waiting 
for request" status is implicitly indicated if bits ST12 
through STg are clear. 

Second Interrupt Pending (SIP). When a second inter- 
rupt is to be issued before the first interrupt is 
acknowledged, this bit is set and the channel relin- 
quishes the bus until an Acknowledge occurs. 

Waiting for Bus (WFB). This bit is set when the channel 
is waiting for bus control to perform a DMA operation. 

No Auto-Reload or Chaining (NAC). This bit is set under 
the following conditions: 

■ A channel completes a DMA operation and neither 
Base-to-Current reloading nor auto-chaining is en- 
abled. 

■ A channel is issued an EOP during chaining. 

■ A Reset is issued to the DTC. 

Chaining Abor t (CA). This bit is set when a channel is 
issued an EOP during chaining or a Reset is issued to the 
DTC. The Chain Abort (CA) bit holds the No Auto-Reload 
or Chaining (NAC) bit in the set state until the EOP bit is 
cleared. The CA bit is cleared when a new Chain Address 
Segment and Tag word or Offset word is loaded into the 
channel. 

Interrupt Status Field. The Channel Interrupt Enable 
(CIE), Interrupt Pending (IP), and Interrupt Under Service 
(IUS) bits are used to control the way a channel 
generates an interrupt. An interrupt source with its IP bit 
set makes an interrupt request if all of the following con- 
ditions are met: Interrupts are enabled, (CIE bit = 1), 
there is no Interrupt Under Service (IUS bit = 0), no 
higher priority interrupt is being serviced, and no Inter- 



rupt Acknowledge transaction is in progress. When an 
interrupt source has an Interrupt Under Service (IUS 
= 1), all lower priority interrupt sources are prevented 
from requesting interrupts. 

Interrupt Vector and Interrupt Save Registers. The 

8-bit Interrupt Vector register contains the vector or 
identifier to be output during an Interrupt Acknowledge 
cycle. When an interrupt occurs, the contents of the In- 
terrupt Vector register and bits ST9-ST15 of the Status 
register are stored in the 16-bit Interrupt Save register. 
Because the vector and status are stored, a new vector 
can be loaded during chaining and a new DMA operation 
can be performed before an Interrupt Acknowledge cy- 
cle occurs. If another interrupt occurs on the channel 
before the first is acknowledged, further channel activity 
is suspended. When a clear IP command is issued, the 
status and vector for the second interrupt are loaded into 
the Interrupt Save register and channel operation 
resumes. The DTC can retain only two interrupts for 
each channel. The Interrupt Save register is fast- 
readable. 

Chain Address Register. This register points to the 
chain control table in memory containing data to be load- 
ed into the channel's registers. The Chain Address 
register consists of two words (Figure 1 1 ). The first word 
consists of a Segment and Tag field. The second word 
contains the 16-bit offset portion of the memory address. 
Bit 15 in the Segment field is ignored when the DTC is 
configured for logical address space (LPA = 1 ). The Tag 
field contains two bits used to designate the number of 
Wait states to be inserted during accesses to the Chain 
Control table. The Chain Address register is fast- 
readable and is loadable by chaining. 

Table 4 provides a list of register addresses. 



195 



STATUS REGISTER 



)CIE 
IUS 
IP 

CA 
,NAC 
STATUS )WFB 
SIP 

RESERVED 



|Di 5 |Ph|Di3|Di2 D11 D10 D 9 Del D7 De | Ds P< | D3 | D2 O1 | Do | 



TC 
EOP 
MC 
MCL 
MCH 

HRQ \ HARDWARE 



COMPLETION 
STATUS 



HM 



INTERFACE 
STATUS 



RESERVED 



INTERRUPT SAVE REGISTER 



D, 4 



D13 



D10 



D 9 



D 6 



D 7 



D 6 O5 D, 



D 3 



D 2 D, 



Do 



VECTOR 

CHANNEL NUMBER 

= CH1 

1 = CH2 

TC 
EOP 

■ MC 

CHAIN ABORTED 

• MCL 

■ MCH 

• HARDWARE REQUEST 



CHAIN ADDRESS REGISTER 



WAIT STATES 

1 WAIT STATES 

2 WAIT STATES 
4 WAIT STATES 

.THIS BIT IS 
FOR PHYSICAL 
ADDRESS ONLY 



PATTERN AND MASK REGISTERS 



INTERRUPT VECTOR REGISTER 



|Di 5 |Di 4 |Di3|Di2|Dii|Dio| D9 | Ds | D? | De | D5 D4 D3 I D2 "dTTdqI 



|D 7 |D6|Ds|D4lD3|P2|Ol|Do| 



I 



INTERRUPT 
" VECTOR 



Figure 11. Special-Purpose Channel Registers 



196 



Table 4. Register Address Summary 



Address 






(AD 7 -ADg) 


(Hex) 


Control Registers 


X 1 1 1 X 


38 


Master Mode 


X 1 1 1 1 X 


2E 


Command Channel 1 


X 1 1 1 X 


2C 


Command Channel 2 


General-Purpose Channel Registers 


X00 1 1 1 X 


1A 


Current Address Register A-Channel 1, Segment/Tag 


X 1 1 X 


OA 


Current Address Register A-Channel 1, Offset 


XOO 1 1 OOX 


18 


Current Address Register A-Channel 2, Segment/Tag 


xooo 1 oox 


08 


Current Address Register A-Channel 2, Offset 


X 1 1 X 


12 


Current Address Register 8-Channel 1, Segment/Tag 


X0 1 X 


02 


Current Address Register B-Channel 1, Offset 


X 1 X 


10 


Current Address Register B-Channel 2, Segment/Tag 


xoooooox 


00 


Current Address Register B-Channel 2, Offset 


X 1 1 1 1 X 


1E 


Base Address Register A-Channel 1, Segment/Tag 


XOOO 1 1 1 X 


OE 


Base Address Register A-Channel 1, Offset 


XO 1 1 1 X 


1C 


Base Address Register A-Channel 2, Segment/Tag 


XO 1 1 X 


OC 


Base Address Register A-Channel 2, Offset 


X 1 1 1 X 


16 


Base Address Register B-Channel 1, Segment/Tag 


XOOOO 1 1 X 


06 


Base Address Register B-Channel 1, Offset 


X 1 1 X 


14 


Base Address Register B-Channel 2, Segment/Tag 


X 1 X 


04 


Base Address Register B-Channel 2, Offset 


X 1 1 1 X 


32 


Current Operation Count Channel 1 


XO 1 1 ooox 


30 


Current Operation Count Channel 2 


X 1 1 1 1 X 


36 


Base Operation Count Channel 1 


XO 1 1 1 OX 


34 


Base Operation Count Channel 2 


Special-Purpose Channel Registers 


X 1 1 1 X 


4A 


Pattern Channel 1 


X 1 1 X 


48 


Pattern Channel 2 


X 1 1 1 1 X 


4E 


Mask Channel 1 


X 1 1 1 X 


4C 


Mask Channel 2 


XO 1 1 1 1 X 


2E 


Status Channel 1 


XO 1 1 1 ox 


2C 


Status Channel 2 


X 1 1 1 X 


2A 


Interrupt Save Channel 1 


XO 1 1 oox 


28 


Interrupt Save Channel 2 


X 1 1 1 1 x 


5A 


Interrupt Vector Channel 1 


X 1 1 1 OOX 


58 


Interrupt Vector Channel 2 


X 1 1 1 X 


26 


Chain Address, Channel 1 Segment/Tag 


XO 1 OOO 1 X 


22 


Chain Address, Channel 4 Offset 


XO 1 00 1 OX 


24 


Chain Address, Channel 2 Segment/Tag 


X 1 X 


20 


Chain Address, Channel 2 Offset 


X 1 1 1 1 X 


56 


Channel Mode Channel 1 High 


X 1 1 1 X 


52 


Channel Mode Channel 1 Low 


X 1 1 1 X 


54 


Channel Mode Channel 2 High 


X 1 1 X 


50 


Channel Mode Channel 2 Low 



NOTE: X = ignored. 



197 



ADDRESSING 



The address generated by the DTC is always a byte ad- 
dress, even though the memory is organized as 16-bit 
words. All word-sized data is word-aligned and must be 
addressed by even addresses (An, = 0). With byte 
transfers, the least significant address bit determines 
which half of the A/D bus is used for the transfer. An 



even address specifies the most significant byte 
(AD 8 -AD-| 5 ), and an odd address specifies the least 
significant byte (AD0-AD7). This addressing mechanism 
applies to memory accesses as well as to I/O and 
Special I/O accesses. 



COMMANDS 

The Z801 6 DTC responds to several commands that give 
the CPU direct control over operating parameters. The 
commands described below are executed immediately 
after being written by the CPU into the DTC's Command 
register. A summary of the DTC commands is given in 
Table 5. 

Reset 

The Reset command forces the DTC into an idle state, in 
which it waits for a Start Chain command. The Start 
Chain command initiates a chain operation on either 
channel. 



Software Request 

A channel's Software Request command initiates a 
previously programmed transfer. If both channels are 
active, Channel 1 has priority. 

Set/Clear Hardware Mask 

The Set/Clear Hardware Mask command sets or clears 
the Hardware Mask bit in the selected channel's Mode 
register. 



Table 5. DTC Command Summary 



Example 
Opcode Bits Code 
Command 7654 3210 (HEX) 

Reset 000X XXXX 00 

Start Chain Channel 1 101X XXXO AO 

Start Chain Channel 2 101X XXX 1 A1 



Clear Software Request Channel 1 


01 OX 


xxoo 


40 


Clear Software Request Channel 2 


01 OX 


XX01 


41 


Set Software Request Channel 1 


01 OX 


XX10 


42 


Set Software Request Channel 2 


01 OX 


XX11 


43 


Clear Hardware Mask Channel 1 


100X 


xxoo 


80 


Clear Hardware Mask Channel 2 


100X 


XX01 


81 


Set Hardware Mask Channel 1 


100X 


XX10 


82 


Set Hardware Mask Channel 2 


100X 


XX11 


83 


Clear CIE, IUS, IP Channel 1 


001 E 


SPOO 


* 


Clear CIE, IUS, IP Channel 2 


001 E 


SP01 


* 


Set CIE, IUS, IP Channel 1 


001 E 


SP10 


* 


Set CIE, IUS, IP Channel 2 


001 E 


SP11 


* 


Clear Flip Bit Channel 1 


011X 


xxoo 


60 


Clear Flip Bit Channel 2 


011X 


XX01 


61 


Set Flip Bit Channel 1 


011X 


XX10 


62 


Set Flip Bit Channel 2 


01 1X 


XX11 


63 



•NOTES: 1. E = Set to 1 to perform set/clear on CIE. Clear to for no ettect on CIE. 

2. S = Set to 1 to perform set/clear on IUS, Clear to for no effect on IUS. 

3. P = Set to 1 to perform set/clear on IP, Clear to for no effect on IP. 

4. X = "don't care" bit. This bit is not decoded and may be or 1. 

5. Flip bit = reset to for ARA = src, ARB = dst. Set to 1 for ARA = dst, 
ARB = src. 



198 



Set/Clear IP, IUS, and CIE 



Set/Clear Flip Bit 



The Set/Clear IP, IUS, and CIE commands manipulate 
the Interrupt Control bits located in each channel's 
Status register. These bits implement the interrupt daisy- 
chain control. The IP, IUS, and CIE bits for each channel 
can be set and cleared individually or in combination. 



The Set/Clear Flip Bit command reverses the source and 
destination, thereby reversing the direction of data 
transfer without reprogramming the channel. 



TIMING 



The following descriptions and timing diagrams refer to 
the relative timing relationships of DTC signals during 
basic operations. For exact timing information, refer to 
the composite timing diagrams. 

Bus Request And Acknowledge 

Before the DTC can peTform a DM A operatio n , it must 
gain control of the system bus: The BUSREQ, BAl, and 
BAO interface pins provide connections between the 
DTC and the host CPU and other DMA devices to ar- 
bitrate which device has control of the system bus. 
When th e DTC wants to gain bus control, it drives 
BUSREQ Low. Bus Request and Acknowledge timing is 
shown in Figure 12. 

Flowthrough Transactions 

Timing for Flowthrough I/O and Flowthrough Memory 
transactions (Figures 13 and 14, respectively) is iden- 
tical. There are two types of I/O space on the Z8016: I/O 
and Special I/O. Status lines ST0-ST3 specify when an 
I/O operation is being performed and which of the two 
I/O spaces is being accessed. During an I/O transaction, 



status signal N/S will be Low to indicate a System Level 
operation. 

The timing for I/O operations is identical to the timing of 
Flowthrough memory transactions. An I/O cycle consists 
of three states: T-|, T2, and T3. The TWA state is a Wait 
state that can be inserted into the transaction cycle. The 
AS output is pulsed Low to mark the beginning of_a 
T-cycle^The N/S line is set Low (System) and the R/W 
and B/W lines select Read or Write operations for bytes 
or words. The N/S, R/W and B/W lines become stable 
during T1 and remain stable until the end of T 3 . 

I/O address space is byte-addressed but both 8- and 
16-bit data sizes are supported. During I/O transactions, 
the B/W output is High for byte transactions and Low for 
word transactions. 

The R/W output is High during Read operations and Low 
during Write operations. DS is driven Low to signal the 
peripherals that data can be gated onto, or received 
from, the bus. DS is driven High to signal the end of the 
I/O transaction. 



ST0-ST3, AS , 
SS, RIW 
BfW, HIS | 

(SNo-SNgj* 

AD -AD,5 I 

(SNo-SN,)" 



For logical addressing only. 
"For physical addressing only. 



-if- 



-ft-/ 



-fj-l 



-v- 



-u- 
-ff- 



T 



-tj- 



-if- 



f 



-fj- 



J~ 



— c 

/A- 



IK- 



Figure 12. Bus Request and Acknowledge Timing 



199 



CLOCK 



WAIT 




ST0-ST3, B/W 

(SN0-SN7)** 



N/S 



AS 



MMUSYNC* 



(SMo-SMe)* 







LOW 
















"A 








V 


/ 













READ 
IN 



AD PORT ADDRESS ^ - 



DS 



\ 



WRITE 
OUT 



AD 



"" ^ PORT ADDRESS ^ 



DS 



R/W 



* For logical addressing only. 
**For physical addressing only. 



DATA 



DATA OUT 















\ 


/ 


r 









Figure 13. Flowthrough I/O Transaction Timing 



200 



2129-013 



CLOCK 



WAIT 



ST0-ST3, B/W 
N/S 

(SN0-SN7)* * 



(SN -SN 6 ( 



MMUSYNC 



READ < 



WRITE < 




R/W 



AD 



R/W 



*For logical addressing only. 
"For physical addressing only. 



Figure 14. Flowthrough Memory Transaction Timing 



Flyby Transactions 

A Flyby operation is performed during three T-states. AS 
is pulsed during Ti to signal the output of address infor- 
mation. R/W is High if the current ARA specifies source, 
and Low if the current ARB specifies destination. DS and 



DACK are driven active during I2 to initiate the transfer, 
and driven inactive during T3 to conclude the transfer. 
Wait states can be inserte d betw een T2 and T3 to extend 
the active time to DS and DACK. Flyby transaction tim- 
ing is shown in Figure 15. 



CLOCK 



ST 0; ST, —I V/ 

, n/s**- y 




INSERT WAIT STATE 



B/W 

(SN0-SN7) 



AS 



MMUSYNC * 



f 



r 



(SNo-SN«)* 



SEGMENT NUMBER 



TO FLYBY 
PERIPHERAL 



■5 



ADDRESS (A) 



FROM FLYBY 



zx 



X 



xz 



^ DATA IN ^ — — 



I/O — - I/O 
I/O MEM 



ADDRESS (B) 



DACK 



DATA OUT 



\ 



f 



xz 



'Toggles for memory access in logical t 

* * For physical addressing only. 

* * N/S will be low lor I/O transactions. 



(A) Address Is current ARA 

(B) Address Is current ARB 



Figure 15. Flyby Transaction Timing 



202 



2129-015 



DREQ Timing 

The following section describes DREQ timing for various 
operations. 



A High-to-Low transition of DREQ causes a single itera- 
tion of a DMA operation. A new transition can occur after 
the Low-to-High AS transition on the first memory or I/O 
access of the DMA iteration. Figure 16 shows the timing 
for a new transition to be applied and recognized to 
avoid giving up the bus at the end of the current iteration. 



In Bus Hold mode, DREQ is sampled when a channel 
gains bus control. If DRE Q is Lo w, an iteration of a DMA 
operation is performed. If DREQ is High, the channel re- 
tains bus control and continues to drive all bus control 
signals active or inactive, but performs no DMA 
operation. 



In Demand mode during DMA operation, DREQ is sam- 
pled to determine whether the channel should perform 
another cycle or release the bus (Figure 17). 



DREQ is sampled after each End o f Chain ing or Base-to- 
Current Reloading operation. If DREQ is active, the 
channel begins performing DMA operations immedi- 
ately, without releasing the bus. 



DACK Timing 

During I/O and memory transactions, WAIT is sampled in 
the middle of T 2 . If WAIT is High, and no programmable 
Wait states are selected, the DTC proceeds toJY Other- 
wise, one or more Wait states are inserted. WAIT is also 
sampled during Twa- If WAIT is High the DTC proceeds 
to T 3 , otherwise, additional Wait states are inserted. 
When both h ardwa re and software Wait states are in- 
serted, each WAIT time is sampled. A Low causes a 
hardware Wait state to be inserted in the next cycle. 
Software Wait state insertion is suspended until WAIT is 
High. Hardware Wait states can be ins erted any time 
during the software Wait state sequence. DACK timing is 
shown in Figure 18. 

EOP Timing 

EOP is driven Low when a TC, MC, or EOP term inati on 
occurs. When a DMA operation has terminated, EOP is 
sampled on the falling edge of T 3 to determine if EO P has 
been driven Low. Th e gen eration of internal EOPs and 
sampling of external EOPs for Transfers-an d-Se arches 
follows the same timing used for Transfers. EOP timing 
is shown in Figure 19. 



FIRST ACCESS OF DMA ITERATION LAST ACCESS OF DMA ITERATION 
Tl *f* T 2 // TwA or T 2 — ^ T 3 - 



CLOCK 




DREQ 



-fj- 



\ L 



Figure 16. Sample DREQ During Single Transfer DMA Operations 



203 



DREQ 



(A) Sampling of DREQ While in Bus Hold Mode 



LAST ACCESS OF DMA ITERATION 
-T 2 or T-, »-|-«— T WA or T 2 » |- « T 3 



CLOCK 



FIRST ACCESS OF NEXT DMA ITERATION 
T, *lm T 2 J 




DREQ 



(B) DREQ Sampling in Demand Mode During DMA Operations 



CLOCK 




DREQ 



(C) Sampling DREQ at the End of Chaining 



CLOCK 




DREQ 



(D) Sampling DREQ at End of Base-to-Current Reloading 



Figure 17. DREQ Sampling in Demand Mode 



204 



2129-017 



LEVEL 
DACK 



f 

PULSED V TO _/ ZTi 

DACK(FLYBY) \ FLYBY^/ / f 

I/O— ►I/O 

I/O — ►ME 

. .. a w 



FROM 
FLYBY 



MEM- 



Figure 18. DACK Timing 




2129-018. 019 



205 



ACTIVE STATE TIMING 




2129020 



AC CHARACTERISTICSt 

Timing for DTC as Bus Master 









4 MHz 


6 MHz 




■jy iiiuui 


Pllf HI III! Ill 1 11 


Min 


Max 


Min 


Max 


1 


TcC 


Clock Cycle Time 


250 


2000 


165 




2 


TwCh 


Clock Width (High) 


105 




70 




3 


TwCI 


Clock Width (Low) 


105 




70 




4 


TfC 


Clock Fall Time 




20 




10 


5 


TrC 


Clock Rise Time 




20 




15 


6 


TdC(SNv) 


Clock t to Segment Number Valid (50pf Load) Delay* * * 




110 




90 


7 


THP/^NIn^ 

I Uu\OI N I if 


Olnpk t tfi ^pnmpnl Mi imhpr Vtaliri DpIsa/ 

\_/ 1 \JK^ r\ 1 LU uCLjl t IL.I 11 INUI 1 IUC?I Vdlivj L/Cloy 






1 n 

I V 




8 


TdC(Bz) 


Clock t to Bus Float Delay 




65 




50 


9 


TdC(A) 


Clock t to Address Valid Delay 




100 




90 


10 


TdC(Az) 


Clock t to Address Float Delay 




65 




50 


11 


TdA(DI) 


Address Valid to Data In Required Valid Delay 


400 




305 




12 


TsDI(C) 


Data In to Clock 1 Setup Time 


20 




15 




13 


TdDS(A) 


DS t to Address Active Delay 


80 




45 




1 A 




(""li-ir-i/ t tri Plata Hi it \/aliH rial aw 




1UU 




an 


15 


ThDI(DS) 


DSt to Data In Hold Time 












16 


TdDO(DS) 


Data Out Valid to DS t Delay 


230 




200 




21 


TdDO(SW) 


Data Out Valid to DS t (Write) Delay 


55 




35 




24 


TdC(ASf) 


Clock t to AS I Delay 




70 




60 


25 


TdA(AS) 


Address Valid to AS t Delay 


50 




35 




26 


TdC(ASr) 


Clock J to AS t Delay 




80 




60 


27 




mo i lu udld hi ncquucu vdiiu ucidy 




ouu 






28 


TdDS(AS) 


DSttoASiDelay 


75 




35 




29 


TwAS 


AS Width (Low) 


80 




60 




30 


TdAS(A) 


AS t to Address Valid Delay 


60 




45 




31 


TdAz(DSR) 


Address Float to DS (Read) I Delay 












32 


TdAS(DSR) 


ASttoDSi(Read) Delay 


75 




40 




33 


TdDSR(DI) 


DS (Read) i to Data In Required Valid Delay 


165 




155 




34 


TdC(DSr) 


Clock i to DS t Delay 




70 




65 


35 


TdDS(DO) 


DS t to Data Out (Write Only) and Status Valid (Read 














and Write) Delay 


85 




45 




36 


TdA(DSR) 


Address Valid DS (Read) i Delay 


120 




110 




37 


TdC(DSR) 


Clock f to DS (Read) J Delay 




60 




60 


38 


TwDSR 


DS (Read) Width (Low) 


275 




185 




39 


TdC(DSW) 


Clock i to DS (Write) i Delay 




60 




60 


40 


TwDSW 


DS (Write) Width (Low) 


160 




150 




41 


TdDSI(DI) 


DS (Input) i to Data In Required Valid Delay 




325 




210 


42 


TdC(DSf) 


Clock i to DS (I/O) I Delay 




60 




60 


43 


TwDS 


DS (I/O) Width (Low) 


150* 




150 




47 


TdC(S) 


Clock t to Status Valid Delay 




110 




80 


48 


TdS(AS) 


Status Valid to AS t Delay 


60 




35 




62 


TsWT(C) 


WAIT to Clock I Setup Time 


20 




20 




63 


ThWT(C) 


WAIT to Clock i Hold Time 


30 




30 




96 


TdC(SNr) 


Clock 1 to SN7/MMUSYNC t Delay* * 




110 




110 


97 


TdC(SNf) 


Clock t to SN7/MMUSYNC * Delay* * 


20 


110 




110 



NOTES: 

'Wait states should be inserted by programming a hardware when accessing slow peripherals. * " * 130 ns max with Logical Addressing. 

' * Logical Addressing only. tUnits in nanoseconds (ns). 



207 



INACTIVE STATE TIMING 



AD -AD,5 < 



DS < 




INTERRUPT 
ACKNOWLEDGE 



ST -ST 3| 



*i p ® — *T"-@-»" 



X 



BUS EXCHANGE TIMING 




ST0-ST3, AS, 
OS, R/Wj 
B/W, N/S 

(SNo-SNn)- 



"For logical addressing only. 
"For physical addressing only. 

Note 1: The DTC will begin driving the bus on the clock cycle following the clock cycle in which the set up parameters ate met. 



208 



2129-021. 022 



AC CHARACTERISTICS! 

Timing for DTC as Bus Slave and CPU-DTC Bus Exchange 









4 MHz 


6 MHz 


Number 


Symbol 


Parameters 


Min 


Max 


Min 


Max 


64 


TwDRQ 


DREQ Pulse Width (Single Transfer Mode) 


20 




20 




65 


TsDRQ(C) 


DREQ Valid to Clock t Setup Time 


60 




50 




66 


ThDRQ(C) 


Clock t to DREQ Valid Hold Time 


20 




20 




67 


TdC(BRQf) 


Clock t to BUSREQ I Delay 




150 




120 


CO 

DO 


I CIO(DnUr) 


OIOCK 4- TO oUontU T ueiay 




165 




150 


69 


TdBRQ(BUSc) 


BUSREQ t to Control Bus Float Delay 




140 




110 


70 


TdBRQ(BUSd) 


BUSREQ t to AD Bus Float Delay 




140 




110 


71 


TdDSA(RDV) 


DS J (Acknowledge) to Data Output Valid Delay 




135 




120 


72 


TdDSA(RDZ) 


DS t (Acknowledge) to Data Output Float Delay 




80 




75 


73 


TdDSR(DOD) 


DS J (IOR) to Data Output Driven Delay 




135 




120 


74 


TdDSR(RDZ) 


DS t (IOR) to Data Output Float Delay 




80 




75 


75 


TwAS 


AS Low Width 


70 




50 




76 


TsA(AS) 


Address Valid to AS t Setup Time 


30 




10 




77 


ThAS(Av) 


AS t to Address Valid Hold Time 


50 




40 




78 


TdAS(DS) 


AS f to DS * Delay (I/O) 


50 




40 




79 


TsCS(AS) 


CS Valid to AS t Setup Time 












80 


ThCS(AS) 


AS t to CS Valid Hold Time 


40 




30 




81 


TwAS(DS) 


AS and DS Simultaneously Low Time (Reset) 


3TcC 




3TcC 




82 


TdBAI(Az) 


BAI t to SNrj-SN/, AD -AD 15 Float Delay (Reset) 




135 




120 


83 


TdBAI(ST) 


BAI t to ST0-ST3, R/W, B/W, N/S Float Delay (Reset) 




100 




80 


84 


TdBAI(DS) 


BAI t to DS, AS Float Delay (Reset) 




100 




85 


85 


TdDS(Dn) 


DS f (IOW) to Data Valid Hold Time 


40 




40 




86 


TdAC(DRV) 


Address Valid to Data (IOR) Required Valid Delay 




540 




345 


87 


TdAZ(DS) 


Address Float to DS J (IOR) Delay 












88 


TwDS(IO) 


DS (IO) Low Width 


150* 




150 




89 


TsD(DS) 


Data (IOW) Valid to DS t Setup Time 


40 




40 




90 


TrDS(W) 


DS t (IOW) to DS J (IOW) (Write Recovery Time 














applies only for issuing Command) 


4TcC 




4TcC 




91 


TsBAK(C) 


BAI Valid to Clock t Setup Time 


60 




50 




92 


TdAS(DS) 


ASttoDSi(ACK)Delay 


100 




100 




93 


TwDS(AK) 


. DS (ACK) Low Width 


150 




150 




94 


TdBRQ(BAI) 


BUSREQ i to BAI 1 Required Delay 












95 


TsS(AS) 


Status Valid to AS t Setup Time 


40 









98 


TdBAI (BAO) 


BAi t, i to BAO t, i Delay 




80 




70 


. 99 


TdlEI(IEO) 


IEI U to lEOf. 4. Delay 




80 




60 



NOTES: 

"2000 ns for reading slow-readable registers (worst case) 
tUnits in nanoseconds (ns). 



209 



ABSOLUTE MAXIMUM RATINGS 



Voltages on all pins with respect 

toGND -0.3V to +7.0V 

Operating Ambient 

Temperature See Ordering Information 

Storage Temperature - 65 °C to + 1 50 °C 



Stresses greater than those listed under Absolute Maximum Ratings may 
cause permanent damage to the device. This is a stress rating only; 
operation of the device at any condition above those indicated in the 
operational sections of these specifications is not implied. Exposure to 
absolute maximum rating conditions for extended periods may affect 
device reliability. 



STANDARD TEST CONDITIONS 



The DC characteristics and capacitance sections below 
apply for the following standard test conditions, unless 
otherwise noted. All voltages are referenced to GND. 
Positive current flows into the referenced pin. 

Standard conditions are as follows: 

■ + 4.75V « V cc < + 5.25V 

■ GND = 0V 

■ T A as specified in Ordering Information 

All AC parameters assume a load capacitance of 50 pf max. 



FROM OUTPUT . 
UNDER TEST 




FROM OUTPUT ( 
UNDER TEST 



±1 50 pi 



Standard Test Load 



in Test Load 



DC CHARACTERISTICS 



Symbol 


Parameter 


Min 


Max 


Unit 


Condition 


V C H 


Clock Input High Voltage 


Vcc-04 


V cc + 0.3 


V 


Driven by External Clock Generator 


Vol 


Clock Input Low Voltage 


-0.3 


0.45 


V 


Driven by External Clock Generator 


V,H 


Input High Voltage 


2.0 


Vcc + 0-3 


V 




V|L 


Input Low Voltage 


-0.3 


0.8 


V 




V H 


Output High Voltage 


2.4 




V 


l 0H = -250 iiA 


Vol 


Output Low Voltage 




0.4 


V 


I l = + 2-0 mA 


l|L 


Input Leakage 




+ 10 


fA 


0.4 s V, N s V cc 


lOL 


Output Leakage 




±10 


dA 


0.4 5 V| N < +V CC 


!CC 


V cc Supply Current 




350 


mA 


T A = 0°C 



NOTE: Vqq = 5V ± 5% unless otherwise specified. 



CAPACITANCE 



Symbol 


Parameter 


Min 


Max 


Unit 


CCLOCK 


Clock Capacitance 




40 


pf 


C|N 


Input Capacitance 




5 


Pf 


COUT 


Output Capacitance 




10 


Pf 



T A = 25°C, f = 1 MHz. 
Unmeasured pins returned to ground 



210 



Zilog 



PRELIMINARY 

Product Specification 



October 1988 



Z16C20 CMOS Z-BUS ®GLU 
General Logic Unit 



FEATURES: 

■ Directly Interfaces Z8000 CPU'S To Their Peripherals 

■ 8M Byte Address Range 

■ Eprom Interface 

■ Static RAM Interface 

■ Dynamic RAM Interface / Timing 

■ Eprom Address Accelerator 

■ DMA Controller 

■ Clock Generator 



Reset Circuitry 

Programmable Wait State Generators 

Input/Output Latch Controls 

General Purpose Timers 

Watchdog Timer 

Prioritized Interrupts 

Fully Programmable 

10 MHz and 16 MHz Versions 



GENERAL DESCRIPTION: 

TheZ16C20 CMOS GLU integrates into a single device 
the SSI and MSI logic typically required to interface a 16- 
bit Z8000 CPU in a system environment. It provides, to the 
user, an optimum system design solution in many areas. 
These areas include; cost, parts count, board area, reliabil- 
ty, and performance. This is achieved while simplifying 
hardware design and shortening design cycles. The 
Z16C20GLU supports up to 8M Byte of address space. It 
interfaces directly and simutaneously to EPROMs, SRAMs 
and DRAMs. By programming in their individual address 
space boundaries, the Z16C20 recognizes the type of 
memory being accessed and generates the appropriate 
controls and handshake signals required. 

By anticipating code fetches, EPROM addresses may be 
generated by the GLU ahead of time. This allows slower 
and less expensive EPROMs to be used while maintaining 
high performance within the system. A DMA channel is 
provided for easy bootstrapping on power-up as well as for 
other DMA applications. In addition to that, the GLU has 
elaborate timing circuitry: on-chip clock generator with sys- 
tem clock and 1/2 system clock outputs (for slow 
peripherals), two general purpose, fully programmable, 1 6- 
bit timers, and a watchdog timer. It is also capable of 
automatically inserting wait-states when needed, prioritiz- 
ing the interrupts and issuing synchronized resets. 



?S5„»ol< 
<<«<>«><< «£Stzji;!! o 

, n n nn n nnnnnnnnnn n n nn nn 



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AD4 
A20 
ADS 
AD3 
AD2 
AD1 
A18 
VSS 
CLOCKO 
VDD 
HAS 
B_HW 

R_NW 
NBAI 
NWAIT 
NBUSREQ 
Alt 



' - S S SlSSRt: 



16C20 



\SSSSRSSS 




74 UNCASE 

72 ^HAIS 

71 H MAI 4 

70 □"«'» 
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e. UMA11 

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ea ]«A» 

as ]VDD 

e- ]«A« 
aa 

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at ]«*« 

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aa 

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y 



211 



PIN DESCRIPTIONS: 



AD0-AD15. Address/Data Bus (I/O). Bidirectional multi- 
plexed address and data bus from the CPU. 

AS*. Address strobe (Bidirectional, Active Low). 

B/W. Byte/Word (Input, active High Byte). Selects byte or 
word transfers. 

BAI. Bus Available Input (input, active Low) . BAI is an input 
received from the CPU or peripherals. Indicates to Z1 6C20 
that bus has been 3-stated so that on-chip DMA can take 
control of the CPU bus. 

BUSREQ. Bus Request (Output, Active Low). Output to 
CPU requesting bus control for Z16C20DMA. 

CASe-o. Column Address Strobe even/odd (Outputs, Ac- 
tive Low). Used for the DRAM interface. CASe selects the 
even bank and CASo selects the odd bank. 

CLK. System clock (Output, active High). Capable of being 
programmed so that when certain peripherals are ac- 
cessed, it will shift frequency to 1/2 of normal rate. This is 
necessary for peripherals using CLKD2 as their clock. 

CLKD2. Clock divide-by-2 (Output, active High). The sys- 
tem clock divided by 2. Used to drive peripherals that can- 
not operate at full system clock speed (CLK). 

CSE. Chip Select Enable (Output, active Low). Used for 
selecting the EPROMs. 

C5RX Chip Select I/O (Output, Active Low). Used for 
selecting I/O space F3XX to FEXX. 

CSSe-o. SRAM Chip Selects even/odd (Outputs, active 
Low). Used to select even or odd SRAM banks. 

DMAREQ. DMA Request (Input, active Low). DMAREQ is 
an input received from a flyby peripheral requesting ser- 
vice from the on-chip DMA. 

'US. Data strobe (Bidirectional, Active Low) 

IEI/IEO. Interrupt Enable In (Input, active High). Interrupt 
daisy chain control input. Optionally may be programmed 
to IEO. 

IEO/BAO. Interrupt Enable Output (Output, Active High) In- 
terrupt daisy chain control output. May be optionally 
programmed to BAO-Sos Acknowledge Output. 

TRY. Interrupt (Bidirectional, Active Low) Interrupt to Z8000 
CPU is generated by internal Z16C20 timers and DMA. 
The DMA may also optionally use this signal as a request 
to relinquish the bus back to the CPU so that the pending 
interrupt may be serviced. For example, the internal 



Z1 6C20 interrupt timer could be used to provide DRAM 
refresh during a DMA cycle if that was required. 

INTACK. Interrupt Acknowledge (Output, Active Low). 
INTACK is used for peripheral hand-shake during the in- 
terrupt acknowledge machine cycle. It is decoded from the 
four status inputs. 

MA0-MA15. Memory Address Bus (Outputs, active High). 
Latched address lines for static memory interfaces. For 
DRAM interface, it will output 9 or 10 (256K or 1M) multi- 
plexed address bits. 

PS0-2/A16-18. Peripheral Selects or Upper memory ad- 
dress lines (Outputs, PSO-2 progammable active High or 
Low). Upper memory address lines are transfered SN0- 
2.PS0-2 may be programmed as peripheral selects or latch 
strobes. These selects will also serve as chip select for 
DMA peripherals during DMA operations. PS2 will be the 
default DMA chip select for the Power-On Bootstrap opera- 
tion. 

R/W. Read/Write input. 

RASO-3 . Row Address Strobes (Outputs, Active Low). 
Used for the DRAM interface. Each RAS is capable of ad- 
dressing 2 Mbyte of DRAM. 

RSTO. Reset Output (Output, Active low). Provides a 
synchronized system reset. 

RSTI. Reset Input (input, active Low). Reset input from ex- 
ternal logic. 

SN0-SN6. Segment Number (Inputs, active High). Upper 
address lines from the Z8000 CPU. 

ST3-ST0. Status (Input, active High). Status lines from 
Z8000 CPU. 

WATT. Wait signal to CPU. (Bidirectional, active Low.) 

WD/GPO . Watch Dog or General Purpose Output (Output, 
active Low). This output will be either the terminal count of 
the internal watchdog timer or a general purpose output, 
bit selectable. 

WE". Write Enable (Output, active Low). This signal is used 
to control memory and I/O writes. It is the combination of 
the "WRITE" signal and the "DATA STROBE". 

XTALIN. Crystal input. 

XTALOUT. Crystal output. 



212 



FUNCTIONAL DESCRIPTION: 



Memory Address Configuration 

Address lines are demultiplexed from the CPU ad- 
dress/data bus and latched internally, except for DRAM ac- 
cesses, where they are appropriately multiplexed for the 
programmed DRAM size. The Z16C20 with the use of in- 
ternal boundary registers, is capable of allocating memory 
space for EPROMs, SRAMS, 256K byte DRAMS and 1M 
byte DRAMS. These memory types may co-exist and are 
restricted to location in the 8M byte memory space as fol- 
lows: 

Eprom 

EPROM must start at location and is allocated in 32k byte 
blocks limited only by the memory size up to the boundary 
address. When other memory types overlap with EPROM, 
EPROM accesses will dominate unless EPROM is 
enabled for "code execution only" and in that case, DRAM 
or SRAM accesses would be performed for "DATA" reads 
and writes. The boundary register for EPROM is 8 bits. 
Multiple banks of EPROM require external decoding of the 
upper address bits and the EPROM chip select. The 
power-up default is that the full memory space is allocated 
to EPROM with no RAM overlap. If EPROM is not used, 
other memory devices can take its space. 

Static Ram 

SRAM space is defined by two 8 bit boundary registers. 
Minimum allocation, when SRAM is used, is 32K bytes. 
When the upper 8 address bits, A[23-16], fall within the 
range of the values set in the boundary registers, the 
SRAM will be automatically selected. 

SRAM is completely disabled by programming bit 7 (most 
significant) of the upper boundary with "0" and bit 7 (most 
significant) of the lower boundary with "1". Since in normal 
operation the upper boundary would never be less that the 
lower boundary it is possible to use this condition as the 
disable. With the afore mentioned restrictions, SRAM may 
reside anywhere in the 8M byte memory space. Maximum 
allocation is 8M bytes. If SRAM is disabled, no memory 
space is allocated to it. 

SRAM accesses take precedence over DRAM accesses 
when both are programmed to reside in the same space. 
However DRAM could be accessed by programming away 
the SRAM space. In this case SRAM would be ignored 
even though it physically exists. Multiple banks of SRAM 
require external decoding of the upper address bits and the 
SRAM chip selects. 

Dram 

Control signals and timing allow the GLU to connect direct- 
ly to 256K bit or 1 M bit DRAM devices. Both sizes may co- 
exist. "RAS ONLY" refresh for both memory sizes is 
provided. 

DRAM space is allocated in banks of either 512K bytes or 
2M bytes. Four boundary registers of 4 bits each allow for 



4 banks without external decoding. Banks of 5121'. bytes 
may co-exist with banks of 2M bytes. A second 4 bit 
register exists to indicate which banks are 2M byte banks. 
Other than these boundary restrictions, DRAM may reside 
anywhere in the 8M byte space. 

Additional banks of 51 2K bytes may be accessed by ex- 
ternal decoding. The technique is to program a bank for 
2M byte. SN4 and SN3 may then be externally decoded 
with the appropriate bank select, RASO, RAS1, RAS2, or 
RAS3. In this manner up to four 51 2K byte RAS signals 
may be produced for each 2M byte RAS signal provided 
by the Zt 6C20. If two banks are programmed for the same 
space then the high order bank will be used for code ac- 
cesses while the low order bank will be used for data ac- 
cesses. This feature is only valid for bank pairs with 1 
and 2 with 3. Only DRAMS of the same size may be paired. 

The DRAM RAS strobes are disabled by programming the 
block size to 2M byte and programming the least significant 
bit of the RAS boundary to a "1 ". It was possible to use this 
bit as a disable since it was not used for determination of 
the 2M byte space. 

Memory Interface 

Eprom Interface 

The EPROM interface consists of a single active low chip 
select /CSE and latched address lines MA0-MA15. A bit is 
provided to completely disable EPROM accesses. 

Accesses are made to EPROM whenever the block ad- 
dress for a code transaction is less than that contained in 
the EPROM boundary register. Likewise "memory data 
reads" access EPROM in this space unless programmed 
to access RAM. 

EPROM mode is enabled on power-up/reset and the 
boundary register defaults to hex FF. 

Eprom Address Accelerator 

The EPROM address accelerator may improve EPROM 
performance by as much as 25% depending on number of 
inserted wait states. This means slower and lower cost 
EPROMS can be used in higher performance applications. 

The system takes advantage of the accelerator when 
operating in a sequential addressing mode of EPROM. The 
accelerator works by incrementing the active address (all 
23 bits) so that the next address is available within the 
Z1 6C20before the next address has arrived from the CPU 
and before the present memory cycle is complete. This 
computed address can be placed on the memory address 
bus at the middle of T3 as soon as the previous transac- 
tion has ended. 

The next address from the CPU will not arrive until the mid- 
dle of T1 of the next cycle at which time it will be compared 



213 



ARCHITECTURE (cont): 



(again 23 bits) against the incremented address that is al- 
ready present on the bus. Should the comparison fail, the 
address bus will be updated with the correct address and 
a wait-state will be generated. The new address will be 
latched and Incremented in anticipation of the next sequen- 
tial EPROM access. 

The EPROM accelerator maintains its advantage even 
when accessing different types of memory or I/O. All that 
is required is that the next executed address be sequen- 
tial. This feature is bit enabled, with default being the off 
state. 

Sram Interface 

The st atic RAM interface consists of three signals CSSe, 
CSSo, and WE". The two chip selects (even and odd) allow 
the high and low byte to be individually accessed. 

The WE" output is a combination of DS" AND R/W. 

CSSe decodes B/W and AO. 

CSSo decodes B/W" and AO". 

The static interface is selected by programming the ap- 
propriate boundary registers. 

Dram Interface 

Sixco ntrol outputs RASO , RAS1 , RAS2, RAS3, CASe, and 
CASo and multiplexed address lines MA0-MA9 are used 
to directly drive DRAM memories. These signals provide 
sufficient control to allow direct addressing for 8 
megabytes of DRAM memory. 

The Row/Column address generation is as follows: 



Z16C20 


256K Bit 


1M Bit 


MA Signal 


Row/Col 


Row/Col 


MAO 


A1/A10 


A1/A11 


MA1 


A2/A11 


A2/A12 


MA2 


A3/A12 


A3/A13 


MA3 


A4/A13 


A4/A14 


MA4 


A5/A14 


A5/A15 


MA5 


A6/A15 


A6/SN0 


MA6 


A7/SN0 


A7/SN1 


MA7 


A8/SN1 


A8/SN2 


MA8 


A9/SN2 


A9/SN3 


MA9 


NA 


A10/SN4 



"RAS ONLY" mode of refresh is supported. The refresh is 
CPU driven and the refresh address is simply passed 
through to the memory bus appropriately timed to the RAS 
signal. Since the Z8000 provides only 9 bits of refresh ad- 
dress the Z16C20 generates the 10th bit. 



Peripheral Interface 

The Z16C20 contains provision for allowing a Z8000 or 
Z280 to operate with slower peripherals operating at one- 
half the system frequency. 

A clock output, CLKD2, that is the System clock devided 
by 2, is provided. This clock will drive the clock input of low 
performance peripherals. An access to any of these 
peripherals will cause theZ1 6C20to slow the system clock 
to 1/2 clock frequency at the leading edge of T2. T1 is not 
stretched because status is not available soon enough in 
T1 to make the decision to hold T1. This should not be a 
problem if the peripheral was able to operate with the full 
frequency address strobe during times when it was not 
being accessed. On power up, CLK is defaulted to 1/2 the 
frequency (CLKD2). 

It should be noted that peripherals do have to recognize 
address strobe even when they are not being accessed. 
This is because the peripherals use the AS" to clock the In- 
terrupt Pending bits with. 

If the full frequency "address strobe width" is not sufficient, 
thenTI can be stretched continuously by 1/2 clock period. 
This should provide sufficient width for the address strobe. 
If T1 stretching is enabled, then the first state of any wait 
state sequence will be shortened to 1/2 clock period. Any 
additional wait states after the first one, will be the normal 
full clock period in length. 

All interrupt acknowledge cycles will also be slowed to 1/2 
if when the low performance peripheral interface is en- 
abled. 

If D MARE Q'is held active during the power-up sequence, 
then F3"2 will be DMA chip select. 

Dma Controller 

The DMA circuit contains a 23 bit up/down address counter 
and a 16 bit transaction length counter. The address 
counter may be incremented/decremented by 1 or 2 or 4 
while the transaction counter is decremented by 1 . This al- 
lows the DMA to transfer 65K bytes, words, or longwords 
(with external hardware support) to anywhere in the 8 
Mbyte memory space. In the case of long word transfer the 
B/W pin will indicate L/W. 

Transfers are flyby mode only and bidirectional between a 
flyby peripheral and a memory device. The memory device 
can be DRAM, SRAM, or EPROM (read only). There is the 
restriction that the DMA addresses be within range of the 
programmed Z16C20 memory boundary registers. 

The DMA will support byte or word transfers. When the 
transfer is byte to memory the transfer should be on the 
lower address/data bus. The Z16C20will replicate this 
lower byte to the upper byte so that it may be loaded into 



214 



ARCHITECTURE (cont): 



the proper memory location. When the byte transfer is from 
the memory to I/O the Z16C20 will replicate the upper bus 
on the lower bus when the address is even. This function 
is bit programmable and is normally defaulted to "off' after 
power-up unless the bootstrap option is to be selected In 
this case it will be defaulted to "on" and the direction of 
transfer will be I/O to memory. 

The external DMA interface requi res the foll owi ng signals . 
Outputs are MA[15:0]. Inputs are DMA REQ andB USACK. 
Bidirectionals are AD[15:0}, SN[6:0], BUSREQ, DS~, AS", 
R/W", B/WTand ST0:3. 

The DMA circuit will acknowledge the DMA peripheral 
through the Peripheral select outputs, PS0_A16, PS1/A17, 
and PS2/A18. Any one of these three outputs may be 
programmed to select the DMA peripheral. If the bootstrap 
load mode is enabled on power-up PS2/A1 8 will select the 
DMA peripheral. During DMA operations, the DMA re- 
questing devicemust invert its RAV input after detecting 
that that BUSACK from the processor has gone active. 

DMA transactions can be made in either "BURST", "AL- 
TERNATE CYCLE", or "BUS RELINQUISH ON VEC- 
TORED INTERRUPT" modes. This third mode in 
conjunction with the internal interrupt timer is useful in ser- 
vicing DRAM refresh during long bursts. 

Burst mode means that the DMA will not release BUSREQ 
until a full block has been transferred, unless, of course, 
the interrupt mode has been enabled. When in "Alternate 
Cycle" mode, the DMA releases bus request upon comple- 
tion of each DMA byte or word transfer and then im- 
mediately regenerates BUSREQ upon detecting /AS, the 
CPU address strobe. 

Bit enabled interrupts on "DMA START" and "DMA 
FINISH" are available. Interrupts are prioritized internally 
and externally through the ZBUS daisy chain arrangement 
and provide a vector upon receiving interrupt acknow- 
ledge. 

Zero to three wait states are programmable. When the two 
devices involved in a DMA transfer differ in the number of 
wait states programmed, the transaction will accom- 
modate the slower device. 

Zero to three delay states for inter-transaction padding are 
also programmable. This allows for delaying the next ac- 
cess to the flyby peripheral if there has not been sufficient 
time for recovery from the previous transaction. 

Software reset is provided. 

The DM A circuit ca n also be made to operate in a bootstrap 
mode if DMAREQ is held active during the power-on-reset 
timing cycle. This mode enables the DMA to program itself 



directly from the flyb y peripher al. This is accomplished by 
the DMA generating BUSREQ to the CPU during reset so 
that the CPU will stay off the bus. It then addresses its in- 
ternal registers and generates the appropriate controls so 
that the flyby peripheral can write the bus. After the 
registers have all been loaded the "start address register" 
and the "transaction count register" are both loaded to their 
respective counters and a normal DMA cycle is started. 
This allows the Z16C20to perform a bootstrap load opera- 
tion on power-up. 

Timers 

TheZ16C20 has two 16 bit timers each with its own eight 
bit prescaler. 

Timer A serves the function of an interrupt timer. The 
counter's 16 bit time constant is written to a latch that is 
also readable by the CPU. The latch contents are loaded 
to the counter on the "GO" command and then down 
counted to a terminal count that sets the interrupt if 
enabled. Timer A has priority over Timer B. The counter 
also has a auto-reload mode where the time constant is 
reloaded to the counter upon terminal count. Interrupts in 
this mode will be missed if interrupt service is not provided 
within the timer period. The contents of the 16 bit counter 
are also readable by the CPU. Timer A is disabled on 
power-up/reset. 

Timer B serves the function of an interrupt timer or a 
watchdog timer. The counter is physically identical to 
Timer A and as an interrupt timer also behaves identically 
to timer A except that the Timer A interrupt has priority over 
Timer B. Once the time constant latch has been loaded, a 
"GO" command along with a 'Timer B Enable" will load the 
counter and immediately start a c ount dow n to zero. If the 
terminal count is reached, either a WDOG output or a sys- 
tem reset is generated. The option is bit programmable. 
The requirement here is to service the counter within the 
timer pe riod so the counter is not able to terminate. The 
WDOG output is bit enabled. If disabled, the output then 
becomes a programmable general purpose output. Timer 
B is disabled on power-up/reset so that the general pur- 
pose output is enabled with default value of logic "1". 

Interrupts And Daisy Chain 

Interrupts are generated by the interrupt timers, the DMA, 
external pin and by writing to a predefined I/O address. The 
DMA provides for two interrupts: one on DMA start and the 
other on DMA finish. The HARD interrupt shares function 
with the "WATCHDOG TERMINAL OUTPUT PIN" and is 
bit programmed as an input or an output. A high to low tran- 
sition on this pin, when enabled as an interrupt, will 
generate an interrupt and provide the appropriate vector 
on interrupt acknowledge. Likewise, the Soft interrupt will 
generate an interrupt whenever a write is made to Z1 6C20 
I/O address of FFEO. These interrupts are highest priority 
internal Z16C20 interrupts jand neither can be interrupted 



215 



__S 



ARCHITECTURE (cont): 



by another internal interrupt while under service. All inter- 
rupts are bit enabled and are programmable as to their 
respective priority. Each interrupt also has an associated 
vector that is put on the Address/Data bus during interrupt 
acknowledge. The first 13 bits of the vector are common 
to all four interrupts and are user programmable. Bit is 
always zero. Bits 1 and 2 are determined by the source of 
the interrupt. 



DEVICE 


VECTOR 


Timer A 


XXXXXXXXXXXOOO 


Timer B 


XXXXXXXXXXX010 


DMA start 


XXXXXXXXXXX1 00 


DMA 


XXXXXXXXXXX110 


HARD 


XXXXXXXXXX1000 


SOFT 


XXXXXXXXXX1010 



"XXXXXXXXXXX" is the common programmed value. Any 
value is appropriate but is the same value for all four inter- 
rupts. The least significant four bits are supplied by the 
Z16C2Q 

The Z8000 daisy chain is also supported through three 
pins, IEI, I EO, and INTACK (decoded from status lines and 
output as INTACK fromZ16C20). 

Interrupt vectors will be enabled on to data bus only if the 
IEI is active. If an interrupt is active IEO is driven Low disa- 
bling any lower priority interrupts from generating a vector 
during interrupt acknowledge. 

Clock Generator 

This circuit consists of signals XTALIN, XTALOUT, and 
CLK and CLKD2. The oscillator input will accept either a 
series resonant crystal, a ceramic resonator, or a TTL level 
signal. The CLK output, which is the system clock, has suf- 
ficient drive capability for the CPU clock requirements. 

CLKD2 is a clock output that is 1/2 the system clock (CLK) 
frequency. CLKD2 is used to clock peripherals that can not 
operate at full system clock speed. The system clock can 
be slowed to 1/2 the normal frequency. This occurs when 
accessing peripherals that are operating on CLKD2, after 
programming into the Z16C20 their address space.This 
feature is bit programmable. The power-up/reset default 
is that no peripherals are clocked by CLKD2. After the 
Z16C20 is initialized, the clock is corrected to the 
programmed frequency for the various peripherals. 



The oscillator's maximum frequency is 32 Mhz. It has an 
internal divide by two for the CPU clock (CLK) and an ad- 
ditional divide by two for the CLKD2. 

Reset Synchronization Circuitry 

The reset cir cuit has two signals. RSTI (input) and RSTO 
(output). The RSTO is synchronized with CLK to meet the 
CPU requirements. 

RSTO is activated four ways: 

a) Po wer On Reset.When power is first applied, circuitry will 
hold RSTO active for 30ms. 

b) Watchdog timer times out, a reset will be issued if that 
function is enabled. 

c) RSTI will ac tivate RSTO for at least 16 clock cycles or 
for as long as RSTI is held active. This input is edge trig- 
gered but has normal TTL levels. 

d) Th ere are t wo levels of software reset: One does not ac- 
tivate RSTO, thus resetting only the internal Z16C20 and 
the other activates the internal reset as well as RSTO. 

Wait State Generators 

Programmable zero to three additional wait states can be 
generated for EPROM, RAM, I/O, DMA and Interrupt Ack- 
nowledge. The DRAM wait state generator adds 1/4 clock 
period to the address hold time after RAS and adds 1/4 
clock period from the column address until CAS is 
generated. This allows additional time for the address bus 
to be driven valid as well as allow more liberal timing for 
the RAS before CAS specification. The additional 1/2 clock 
period will be added to the CAS access time. 

The WAIT I/O consists of an inverter circuit of which the 
pull-up device has high impedance, approximately 2K. this 
feature yields additional power savings since it can direct- 
ly drive a cmos gateand by elliminating the need for a 
power consuming pull-up resistors. 

Wait states are defaulted to maximum delay of three wait 
states upon reset. 

Peripheral Interface 

Peripheral chip selects, CSIO and INTACK signals are 
decoded from the status lines. Any one of the three 
peripheral chip selects may be program med to select the 
DMA peripheral during DMA operation. CSIO is active in 
the normal I/O space and pertains to that space not 
specified by other Z16C20 I/O chip selects. 

The peripheral selects PSn are programmable for active 
high or low. These selects are multiplexed with the upper 
address outputs. 



216 



I/O SELECT 



ADDRESS 



PCSO FOXX 

PCS1 F1XX 

PCS2 F2XX 

CSIO F3XX to FEXX 

Z1 6C20 Register Space FFXX 

Internal registers are word wide and read/write with the ex- 
ception of the count values of Timer A, Timer B, DMA trans- 
action counter, and DMA address counter which are read 
only. 



Z16C20 (GLU) BLOCK DIAGRAM 



RESETi- 
RESETo-. 
XTAL1N- 



BAI 



XTALO - 

CLK - 
CLKD2- 



OSC 

ti 
POR 



WAIT 



WAIT 
STATE 
GEN 



SH0-6"-y*- ADDR/DATA 



ADO- 15- 



16 



LATCHES 



ST0-3-.— y*. 

AS, DS - 
R/W, B/W 



STATUS 
DECODE 



~l T 

CSIO INTACK 



IEO 



BUSREQ DMAREQ 

J L 



DMA 

CNTL 



LOW PERFORM 
PERIF INTFCE 



EPROM 
ACCEL 



WATCHDOG 
& SYSTEM 
TIMER 

T 

INT 



I El 



WDOUT 

(OR: CPO. IE. HWI) 



SRAM 
CNTL 



DRAM 
CNTL 



EPROM 
CNTL. 



MEM/ADDR 
DRIVERS 



D[0-15] 



A[0-15] 



7 



24 



A[0-23] 



SCSe 
■ SCSo 
•WE 



-y*. RASO/3 
— » CASe 



-»- CASo 



CSE 



U. MAO- 15 

3 

^ A16-18 

(OR: 
PSO-2 
LSO-2) 



REGISTER DESCRIPTIONS 



WAIT STATE SELECTS REGISTER 

FFEE 

lis|u|i3 ia|n io|9 j 7 e|s 4I3 a|i o| 



- EPROM WAITS 

- SRAM WAITS 

- DRAM WAITS 

- I/O WAITS 

- INTERRUPT WAITS 

- DMA WAITS 

- BURST WAITS 

- SYS CLOCK / Z 

- EPROM SELECT WHILE DS 



INTERRUPT VECTOR/PORT TIMING REGISTER 
FFF3 

I 15 14 13 12 11 10 9 8 7 6 5 4 h |a |l"l>1 



PS0-CLKD2 
F51 -CLKD2 
PS2-CLKD2 
Tl STRETCH 
INT-VECT 



DMA TRANSACTION COUNTER - READ ONLY REGISTER 



COUNTER B VALUE - READ ONLY REGISTER 



FFEF 



15 14 13 12 11 10 9676643210 



VALUE 



FFF4 



15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 o| 



VALUE 



BOUNDARY REGISTER 1 



FFFO 



15 14 13 12 11 10 9 8 7 6 5 4 3 H 1 



RASO 2MByte 
RAS1 2 MByte 
RAS2 2MByte 
RAS3 2MByte 
EPROM CONFIG 

00 DISABLE 

01 ACTIVE-NO RAM 

10 ACTIVE- SRAM 

11 ACTIVE- DRAM 
1RST-INT. RESET 
XRST-EXT. RESET 
EPROM BOUNDARY 

SN8:AD15 



TIMER A - TIME CONSTANT REGISTER 



FFF5 



15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 



- TIME CONSTANT 



COUNTER A VALUE - READ ONLY REGISTER 
FFF6 



15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 



VALUE 



BOUNDARY REGISTER Z 

FFF1 

I 15 14 13 12 11 10 9 e| 7 6 5 4 3 2 1 | 



» 

SRAM LOWER BOUNDARY 

SNB:AD15 
SRAM UPPER BOUNDARY 

SN8:AD15 



TIMER B - TIME CONSTANT REGISTER 



FFF7 



15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 



- TIME CONSTANT 



BOUNDARY REGISTER 3 



FFF2 



[ 15 14 13 izj 11 ID 9 a| 7 6 5 4 U Z 1 1 



RASO BOUNDARY 

SN8:SN3 
RAS1 BOUNDARY 

SN8:SN3 
RAS2 BOUNDARY 

SN6:SN3 
RAS3 BOUNDARY 

SN6:SN3 



218 



REGISTER DESCRIPTIONS (cont.) 



TIMER CONTROL REGISTER 



FFF8 



1E-A TIMER A INT ENABLE 
AR-A TIMER A AUTO LOAD 
GO- A TIMER A ENABLE 
IE-B TIMER B INT ENABLE 
AR-B TIMER B AUTO LOAD 
GO-B TIMER B ENABLE 
GENERAL PURPOSE PIN DEF. 

00 CONT BY BIT 9 

01 EXT HDWR INT 

10 W TERM COUNT 

11 IE PIN FROM Z280 

- "WD RST TO GPO ON TERM CT 

- GPO SET VALUE 

- HOLD TIMER A 

- HOLD TIMER B 

- TIMER A TEST MODE 

- TIMER B TEST MOD 

- DRAM ADDRESS CONFIG 

00 NORMAL PAGE 

01 PAGE MODE 
10 NIBBLE MODE 



EXTENDED ADDRESS AND PERIPHERAL SELECT REGISTER 



FFF9 



is |i4 ji3 [ia hi io| s| e| t| e| &l 



AD16/PS0/LS0 (CODE) 
ADie/PSO/LSO (CODE) 
AD 17 /PS 1 /LSD (CODE) 
AD17/PS1/LS0 (CODE) 
AD18/PSZ/LS0 (CODE) 
AD1B/PS2/LSO (CODE) 
DMA SELECT (CODE) 
DMA SELECT (CODE) 
HIGHER INT. PRIORITY 

DMA 

1 TIMERS 

RES HIGHEST PRIOR. INT 
EN HARDWAARE INT 
EN SOFTWARE INT 
EN MEMORY BURST 
DSY1 PAD CONTROL 
DSY2 PAD CONTROL 
EN EPROM ACCELERATOR 



DMA SEGMENT NUMBER - READ ONLY REGISTER 

FFFA 



6 5 4 3 2 10 



VALUE 



DMA ADDRESS CONSTANT 



FFFB 



15 14 13 12 11 10 9 8 1 6 6 4 3 2 l~o] 



ADDRESS CONSTANT 



REGISTER DESCRIPTIONS (com.) 



DMA SEGMENT NUMBER CONSTANT 



J 6 5 4 3 Z 1 Q 1 



T 



SEGMENT NUMBER 



FF7D 



DMA TRANSACTION COUNTER CONSTANT 



I 15 14 13 1Z 11 10 9 8 7 6 5 4 3 Z 1 



TRANSACTION CONST 



DMA ADDRESS COUNT - READ ONLY REGISTER 



FFFE 



15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 



VALUE 



DMA CONTROL 



FFFF 



15 14 13 12 11 10 9 8 7 6 5 4 3 Z 10 



^-DMA ENABLE 
DATA SIZE 

00 BYTE 

01 WORD 

10 WORD 

1 1 LONG WORD 

DMA ADDR CNT U/D 

DMA RD/WR 

DMA REQ STATUS 

LST SIC TRANS DEL 

MST SIG TRANS DEL 

DMA MODE 

00 BURST 

01 BURST 

10 ALTERNATE 

11 REL ON VEC INT 

VEC INT ON DMA ST 

VEC INT ON DMA END 

DMA I/O ACCEL 

DMA RESET 

TRANS IN PROCESS 

TRANS BYTE UL/LU 



ABSOLUTE MAXIMUM RATINGS: 

Stresses greater than those listed under Absolute Maxi- 
mum Ratings may cause permanent damage to the device. 
This is a stress rating only; operation of the device at any 
condition above those indicated in the operational sections 
of these specifications is not implied. Exposure to absolute 
maximum rating conditions for extended periods may af- 
fect device reliability. 



STANDARD TEST CONDITIONS: 

The DC Characteristics and Capacitance sections below 
apply to the following standard test conditions, unless 
otherwise noted. All voltages are referenced to GND (OV). 
Positive current flows in to the referenced pin. 

Available operating temperatures ranges are: 

S = 0°C to + 70°C 

E = -40°C to + 85°C 

M = -55°C to + 125°C 
Voltage Supply Range: + 5.0V + 10% 



All AC parameters assume a load capacitance of 100 pF. 
Add 10 ns delay for each 50 pF increase in load up to a 
maximum of 200 pF for the data bus and 1 00 pF for the ad- 
dress and control lines. AC timing measurements are 
referenced to 1.5 volts (except for CLOCK, which is 
referenced to the 10% and 90% points). 



DC CHARACTERISTICS: 



Symbol 


Parameter 


min 


max 


Unit 


Condition 


VlHC 


Input Clock High Voltage 


Vcc-1.0 


VcC + 0.3 


V 


Driven by Ext. Clock 


VlLC 


Input Clock Low Voltage 


-0.3 


1.0 


V 


Driven by Ext. Clock 


VlH 


Input High Voltage 


2.2 


VCC + 0.3 


V 


VlL 


Input Low Votlage 


-0.3 


0.8 


V 




VOHC 


Output Clock High Voltage 


Vcc-0.6 




V 




VOH 


Output High Voltage 


2.4 






IOH = -250^A 


Vol 


Output Low Voltage 




0.4 


V 


IOL = 2.0mA 


VOLW 


Output Low Voltage (Wait) 




0.5 


V 


IOL = 5.0mA 


In. 


Input Leakage Current 




±10 


pA 




ice 


Power Supply Current 




30 


mA 


f = 8.0MHz 








40 


mA 


f= 10.0MHz 












Vcc = 5V 












Vih =\cc-0.2V 












Vil = 0.2V 


Ci 


Input Capacitance 




5 


PF 




Co 


Output Capacitance 




10 


PF 





Voltage on Vcc with respect to Vss 

-0.3Vto +7.0V 

Voltages on all inputs with respect to Vss 

-0.3VtoVcc + 0.3V 

Operating Ambient Temperature 

See Ordering Information 

Storage Temperature 

-65°Cto + 150°C 



The Ordering Information section lists temperature ranges 
and product numbers. Package drawings are in the Pack- 
age Information section. Refer to the Literature List for ad- 
ditional documentation. 

+5V 



FROM OUTPUT 
UNDER TEST C- 



2.1K 



100 
PF 



-L A* 250 
uA 



221 



\ 



Zilog 



Product Specification 



October 1988 



Z80C30 CMOS Z-BUS SCC/ 
Z85C30 CMOS SCC Serial 
Communications Controller 



Features 

■ Low power CMOS. 



Synchronous mode with internal or external 



■ Pin compatible to NMOS versions. 

■ Two independent, to 2.5M bit/second, full— duplex 
channels, each with a separate crystal oscillator, 
baud rate generator, and Digital Phase-Locked Loop 
for clock recovery. 

■ Multi-protocol operation under program control, 
programmable for NRZ, NRZI, or FM data encoding 

■ Asynchronous mode with five to eight bits and one. 
one and one-half, or two stop bits per character, 
programmable clock factor; break detection and 
generation; parity, overrun, and framing error 
detection. 



General Description 

The 280C30/Z85C30 CMOS SCC Serial Communications 
Controller is a CMOS version of the industry standard 
NMOS SCC. It is a dual channel, multi-protocol data 
communications peripheral that easily interfaces to 
CPU's with either multiplexed or non— multiplexed 
address/data buses. The advanced CMOS process 
offers lower power consumption, higher performance, and 
superior noise immunity. The programming flexibility of 
the internal registers allows the SCC to be configured to 
satisfy a wide variety of serial communications 
applications. The many on— chip features such as baud 
rate generators, digital phase locked loops, and crystal 
oscillators dramatically reduce the need for external 
logic. Additional features including a 10 X 19-bit 
status FIFO and 14-bit byte counter were added to 
support high speed SDLC transers using DMA 
controllers. 



character 

synchronization on one or two synchronous 
characters and CRC generation and checking with 
CRC-16 or CRC-CCITT preset to either Is or Os. 

■ SDLC/HDLC mode with comprehensive frame-level 
control, automatic zero insertion and deletion, I— field 
residue handling, abort generation and detection, 
CRC generation and checking, and SDLC Loop mode 
operation. 

■ Local Loopback and Auto Echo modes. 

■ Supports Tl digital trunk. 

■ Enhanced DMA support 

-10 X 19-bit status FIFO 
— 14-bit byte counter 



The SCC handles asynchronous formats, synchronous 
byte— oriented protocols such as IBM Bisync, and 
synchronous bit— oriented protocols such as HDLC and 
IBM SDLC. This versatile device supports virtually any 
serial data transfer application (cassette, diskette, tape 
drives, etc.). 

The device can generate and check CRC codes in any 
synchronous mode and can be programmed to check 
data integrity in various modes. The SCC also has 
facilities for modem controls in both channels. In 
applications where these controls are not needed, the 
modem controls can be used for general-purpose I/O. 

The daisy-chain interrupt hierarchy is also supported — 
as is standard for Zilog peripheral components. 



222 





D 7 TxDA 
D 6 RxDA 
5 TRxCA 

d, rtxCA 

D 3 SYNCA 
D z W/REQA 


— 








■ " 




D, DTRfREQA 

o„ hTsa 

RD CTSA 
WR DCDA 
A/B TxDB 
CE RxOB 
DfC TRxCB 
INT RTxCB 
INTACK SYNCB 
IE! wmEOB 




















IEO OTR/REQ6 
RTSB 

zascso ctsb 

DCDB 













t \ I 



• I CHANNEL 
I CLOCKS 



CHANNEL 
CONTROLS 
FOR K 
DMA, OR 
OTHER 



> CH-A 



ADDRESS' 
DATA BUS 



BUS . 
TIMING 
AND RESET 1 



' I CHANNEL 
| CLOCKS 



CHANNEL 
CONTROLS 
FOR MODEM 
DMA, OR 
OTHER 



> CH-B 



TxDA 
RxDA 
TRxCA 
RTxCA 
5YNCA 
W/REQA 



EO DTR/REQB 
RTSB 

Z80C30 CTSB 
DCOB 



CHANNEL 
CONTROLS 
FOR MODEM, 
DMA, OR 
OTHER 



> CH-A 



' I SERIAL 
. | DATA 

' 1 CHANNEL 
-| CLOCKS 



CHANNEL 
CONTROLS 
FOR MODEM, 
DMA, OR 
OTHER 



>CH-I 



+ S V GND PCLK 

Figure la. Pin Functions, Z85C30 



t t t 

+ 5V GND PCLK 

Figure lb. Pin Functions, Z80C3O 





1 


^ .0 


3". 






a 


3°> 






» 


3* 


<hC 




<* 


3". 


INT C 


5 


» 


3 RD 


160 C 


6 


35 


3 WR 


*c 




« 


J A/B 


INTACK C 


• 


a 


361 




9 


32 


3 D/C 


W/REQA £ 


10 


ZS5C30 3 , 


] GND 


SYNCA C 


" 


30 


3 wTreqb 


RTxCA C 


12 


23 


3 SYNCB 


RxDA L 


13 


28 


□ RT.CB 


TRxCA C 


14 


27 


] RlDB 


TxDA C 


15 


26 


3 TRxCB 


OTR/REQA £ 


16 


25 


3 TxDB 


RTSA C 


17 


» 


J DTR/REQB 


CTSA C 


18 


23 


] RTSB 


DCDA £ 


IB 


22 


□ CTSB 


PCLK C 


20 


! ' 


3 DCDB 



Figure 2b. DIP Pin Assignments, Z85C30 



AO, C 




W 40 


3 AD,, 


AO, C 


2 


39 


] ADj 


AD S £ 


3 


38 


] AD, 


AO, C 


4 


3T 


3 AD, 


INT C 


5 


36 


3 OS 


IEO C 


6 


35 


] AS 


i»C 




« 


] RIW 


INTACK C 


• 


33 


] CSo 


+ 5 V C 




32 


]cs, 


W/REOA Q 


ID 


zeocio j, 


] GND 


SYNCA C 




30 


3 WfREQB 


RTxCA C 


12 


29 


2 SYNCB 


RxDA C 


13 


28 


□ RTxCB 


TRxCA C 


14 


27 


J RxDB 


TxDA C 


15 


2G 


3 TRxCB 


DTRIREQA £ 


16 


25 


] TxDB 


RTSA C 




2« 


J DTR/REQB 


CTSA C 


« 


23 


J RTSB 


DCDA C 


1» 


22 


3 CTSB 


PCLK C 


20 


2, 


3 DCDB 



Figure 2b. DIP Pin Assignments, Z80C30 





(—1 


5 4 3 2 1 44 43 42 41 










5 4 3 2 1 44 43 42 41 


4 


•\ 




IEO 


T 


38 


A/B 


IEO 


7 






39 


R/W 


IEI 


B 




38 


Cf 


IEI 


i 






3B 


as 


INTACK 


• 




37 


D/C~ 


INTACK 


9 






37 


CS, 


+ 5V 


10 




36 


NC 


+ 5V 


10 






36 


NC 


W/rTeQa 


11 




35 


GND 


W/REOA 


11 






35 


GND 


SYNCA 


12 


ZBSC30 


34 


W/REQB 


SYNCA 


12 


Z80C30 




34 


WsffEOB 


RTxCA 


13 




33 


SYNCB 


RTxCA 


13 






33 


SVNCB 


RxDA 


14 




32 


RfxCB 


RxDA 


14 






32 


RTtXB 


TRxCA 


15 




31 


RkDB 


TRxCA 


15 






31 


RxDB 


TV DA 


IS 




30 


TRxCB 


TxDA 


16 






30 


TRxCB 


NC 


17 


20 


TxDB 


NC 


17 






29 


TxDB 






19 20 21 22 23 24 25 28 2 7 21 / 






^» 


19 20 21 22 23 24 25 26 27 


'/ 






Figure 2c. Chip Carrier Pin Assignments, Z85C30 Figure 2d. Chip Carrier Pin Assignments, Z80C30 



Pin Description 



The following section describes the . pin functions 
common to the Z85C30 and the Z80C30. Figures 1 
and 2 detail the respective pin functions and pin 
assignments. 

CTSA, CTSB. Clear To Send (inputs, active Low). 
If these pins are programmed as Auto Enables, a Low 
on the inputs enables the respective transmitters. If not 
programmed as Auto Enables, they may be used as 
general-purpose inputs. Both inputs are Schmitt- 
trigger buffered to accommodate slow rise— time inputs. 
The SCC detects pulses on these inputs and can 
interrupt the CPU on both logic level transitions. 



OCDA, DCDB. Data Carrier Detect (inputs, active 
Low). These pins function as receiver enables if they 
are programmed for Auto Enables; otherwise they may 
be used as general— purpose input pins. Both pins are 
Schmitt— trigger buffered to accommodate slow rise-time 
signals. The SCC detects pulses on these pins and can 
and can interrupt the CPU on both logic level 
transitions. 

DTR/REQA, DTR/REQB. Data Terminal 

Ready/Request (outputs, active Low). These outputs fol- 
low (he state programmed into the DTR bit. They can also 
be used as general-purpose outputs or as Request lines 
for a DMA controller. 

IEI. Interrupt Enable In (input, active High). IEI is 
used with IEO to form an interrupt daisy-chain when 
there is more than one interrupt driven device. A High 
IEI indicates that no other higher priority device has an 
interrupt under service or is requesting an interrupt. 

IEO. Interrupt Enable Out (output, active High). IEO 
is High only if IEI is High and the CPU is not servicing 
an SCC interrupt or the SCC is not requesting an 
interrupt (Interrupt Acknowledge cycle only). IEO is 
connected to the next lower priority device's IEI input 
and thus inhibits interrupts from lower priority devices. 

INT. Interrupt Request (output, open-drain, active 
Low). This signal is activated when the SCC requests 
an interrupt. 



INTACK. Interrupt Acknowledge (input, active Low). 
This signal indicates an active Interrupt Acknowledge 
cycle. During this cycle, the SCC interrupt daisy chain 
settles. When RD or DS becomes active, the SCC 
places a n interru pt vector on the data bus (if IEI is 
High). INTACK is latched by the rising edge of PCLK. 

PCLK. Clock (input). This is the master SCC clock 
used to synchronize internal signals. PCLK is a TTL 
level signal. PCLK is not required to have any phase 
relationship with the master system clock. 



RxDA, RxDB. Receive Data (inputs, active High). 
These input signals receive serial data at standard TTL 
levels. 

RTxCA RTxCB. Receive/Transmit Clocks (inputs, 
active Low). These pins can be programmed in s everal 
different modes of operation. In each channel, RTxC 
may supply the receive clock, the transmit clock, the 
clock for the baud rate generator, or the clock for the 
Digital Phase— Locked Loop. These pi ns ca n also be 
programmed for use with the respective SYNC pins as a 
crystal oscillator. The receive clock may be 1, 16, 32, 
or 64 times the data rate in Asynchronous modes. 



RTSA, RTSB. Request To Send (outputs, active 
Low). When the Request To Send (RTS) bit in Write 
Register 5 (Figure 11) is set, the RTS signal goes Low. 
When the RTS bit is reset in the Asynchronous mode 
and Auto Enable is on, the signal goes High after the 
transmitter is empty. In Synchronous mode or in 
Asynchronous mode with Auto Enable off, the RTS pin 
strictly follows the state of the RTS bit. Both pins 
can be used as general-purpose outputs. 



SYNCA, SYNCB. Synchronization (inputs or outputs, 
active Low). These pins can act either as inputs, 
outputs, or part of the crystal oscillator circuit. In the 
Asynchronous Receive mode (crystal oscillator option not 
select ed), these pins are inputs similar to CTS and 
DCD. In this mode, transitions on these lines affect 
the state of the Synchronous/Hunt status bits in Read 
Register (Figure 10) but have no other function. 

In External Synchronization mode with the crystal 
oscillator not selected, these lines also act as inputs. In 
this mode, SYNC must be driven Low two receive clock 
cycles after the last bit in the synchronous character is 
received. Character assembly begins on the rising edge 
of the re ceive clock immediately preceding the activation 
of SYNC. 

In the Internal Synchronization mode (Monosync and 
Bisync) with the crystal oscillator not selected, these 
pins act as outputs and are active only during the part 
of the receive clock cycle in which synchronous 
characters are recognized. The synchronous condition is 
not latched, so these outputs are active each time a 
synchronization pattern is recognized (regardless of 
character boundaries). In SDLC mode, these pins act 
as outputs and are valid on receipt of a flag. 

TxDA, TxDB. Transmit Data (outputs, active High). 
These output signals transmit serial data at standard 
TTL levels. 



TRxCA, TRxCB. Transmit/Receive Clocks (inputs or 
outputs, active Low). These pins can be programmed 



224 



in several different modes of operation. TRxC may 
supply the receive clock or the transmit clock in the 
input mode or supply the output of the Digital Phase- 
Locked Loop, the crystal oscillator, the baud rate 
generator, or the transmit clock in the output mode. 

W/REQA, W/REQB. Wait/Request (outputs, open- 
drain when programmed for a Wait function, driven High 
or Low when programmed for a Request function). 
These dual— purpose outputs may be programmed as 
Request lines for a DMA controller or as Wait lines to 
synchronize the CPU to the SCC data rate. The reset 
state is Wait. 

Z85C30 

A/B. Channel A/Channel B (input). This signal 
selects the channel in which the read or write operation 
occurs. 

CE. Chip Enable (input, active Low). This signal 
selects the SCC for a read or write operation. 

D — D 7 . Data Bus (bidirectional, 3-state). These 
lines carry data and commands to and from the SCC. 

D/C. Data/Control Select (input). This signal defines 
the type of information transferred to or from the SCC. 
A High means data is transferred; a Low indicates a 
command. 

RD. Read (input, active Low). This signal indicates a 
read operation and when the SCC is selected, enables 
the SCC's bus drivers. During the Interrupt 
Acknowledge cycle, this signal gates the interrupt vector 
onto the bus if the SCC is the highest priority device 
requesting an interrupt. 



WR. Write (input, active Low). When the SCC is 
selected, this signal i ndica tes a write operation. The 
coincidence of RD and WR is interpreted as a reset. 

Z80C30 

AD -AD 7 . Address/Data Bus (bidirectional, active 
High, 3-state). These multiplexed lines carry register 
addresses to the SCC as well as data or control 
information. 

AS. Address Strobe (input, active Low). Addresses on 
AD„-AD 7 are latched by the rising edge of this signal. 

CS . Chip Select (input, active Low). This signal is 
latched concurrently with the addresses on AD„-AD 7 
and must be active for the intended bus transaction to 
occur. 

CSj. Chip Select 1 (input, active High). This second 
select signal must also be active before the intended bus 
transaction can occur. CS t must remain active 
throughout the transaction. 

DS. Data Strobe (input, active Low). This signal 
provides timing for the transfer of data into and out of 
the SCC. If AS and DS coincide, this is interpreted as 
a reset. 

R/W. Read/Write (input). This signal specifies 
whether the operation to be performed is a read or a 
write. 



Functional Description 

The functional capabilities of the SCC can be described 
from two different points of view: as a data 
communications device, it transmits and receives data in 
a wide variety of data communications protocols; as a 
microprocessor peripheral, the SCC offers valuable 
features such as vectored interrupts, polling, and simple 
handshake capability. 

Data Communications Capabilities. The SCC 

provides two independent full-duplex channels 
programmable for use in any common Asynchronous or 
Synchronous data communication protocol. Figure 3 and 
the following description briefly detail these protocols. 

Asynchronous Modes. Transmission and reception can 
be accomplished independently on each channel with five 
to eight bits per character, plus optional even or odd 
parity. The transmitters can supply one, one-and- 
one-half, or two stop bits per character and can 



provide a break output at any time. The receiver 
break— detection logic interrupts the CPU both at the 
start and at the end of a received break. Reception is 
protected from spikes by a transient spike-rejection 
mechanism that checks the signal one— half a bit time 
after a Low level is detected on the receive data input 
(RxDA or RxDB in Figure 1). If the Low does not 
persist (as in the case of a transient), the character 
assembly process does, not start. 

Framing errors and overrun errors are detected and 
buffered together with the partial character on which 
they occur. Vectored interrupts allow fast servicing or 
error conditions using dedicated routines. Furthermore, 
a built— in checking process avoids the interpretation of 
a framing error as a new start bit: a framing error 
results in the addition of one-half a bit time to the 
point at which the search for the next start bit begins. 



225 



START | ST ° P 
MARKING LINE | | P»™ | | | | DATA | ] ' | | DATA~|" 



SYNC DATA 



| CHC, [ CRCj | 



SVNC SYNC DATA DATA CflCi I CRCj 



SIGN A 



I DATA | | DATA | CRC, | CRC, | 

| ADDRESS J~ 



EXTERNAL SVMC 



INFORMATION CRC, CRC, FLAG 



SDLCfHDLC/X.25 



Figure 3. Some SCC Protocols 



The SCC does not require symmetric transmit and 
receive clock signals — a feature allowing use of the 
wide variety of clock sources. The transmitter and 
receiver can handle data at a rate of 1, 1/16, 1/32, or 
1/64 of the clock rate supplied to the receive and 
transmit clock inputs. In Asynchronous modes, the 
SYNC pin may be programmed as an input used for 
functions such as monitoring a ring indicator. 

Synchronous Modes. The SCC supports both byte- 
oriented and bit— oriented synchronous communication. 
Synchronous byte— oriented protocols can be handled in 
several modes, allowing character synchronization with a 
6— bit or 8— bit synchronous character (Monosync), any 
12— bit synchronization pattern (Bisync), or with an 
external synchronous signal. Leading sync characters 
can be removed without interrupting the CPU. 

Five- or 7-bit synchronous characters are detected with 
8- or 16-bit patterns in the SCC by overlapping the 
larger pattern across multiple incoming synchronous 
characters as shown in Figure 4. 

CRC checking for Synchronous byte-oriented modes is 
delayed by one character time so that the CPU may 
disable CRC checking on specific characters. This 
permits the implementation of protocols such as IBM 

Bysinc. 

Both CRC-16 (X 16 + X 15 + X 2 + 1) and CCITT 
(X 16 + X 12 + X s + 1) error checking polynomials are 
supported. Either polynomial may be selected in all 
Synchronous modes. Users may preset the CRC 
generator and checker to all Is or all Os. The SCC 
also provides a feature that automatically transmits CRC 
data when no other data is available for transmission. 



This allows for high speed transmissions under DMA 
control, with no need for CPU intervention at the end 
of a message. When there is no data or CRC to send 
in Synchronous modes, the transmitter inserts 6-, 8—, 
or 16— bit synchronous characters, regardless of the 
programmed character length. 

The SCC supports Synchronous bit— oriented protocols, 
such as SDLC and HDLC, by performing automatic flag 
sending, zero insertion, and CRC generation. A special 
command can be used to abort a frame in transmission. 
At the end of a message, the SCC automatically 
transmits the CRC and trailing flag when the 
transmitter underruns. The transmitter may also be 
programmed to send an idle line consisting of 
continuous flag characters or a steady marking condition. 

If a transmit underrun occurs in the middle of a 
message, as external/status interrupt warns the CPU of 
this status change so that an abort may be issued. 
The SCC may also be programmed to send an abort 
itself in case of an underrun, relieving the CPU of this 
task. One to eight bits per character can be sent, 
allowing reception of a message with no prior 
information about the character structure in the 
information field of a frame. 

The receiver automatically acquires synchronization on 
the leading flag of a frame in SDLC or HDLC and 
provides a synchronization signal on the SYNC pin (an 
interrupt can also be programmed). The receiver can be 
programmed to search for frames addressed by a single 
byte (or four bits within a byte) of a user— selected 
address or to a global broadcast address. In this mode, 
frames not matching either the user— selected or 
broadcast address are ignored. The number of address 



SYNC [ SVNC | SYNC | DATA | DATA j DATA ] DATA | 



Figure 4. Detecting 5— or 7-Blt Synchronous Characters 



226 



bytes can be extended under software control. For 
receiving data, an interrupt on the first received 
character, or an interrupt on every character, or on 
special condition only (end— of— frame) can be selected. 
The receiver automatically deletes all Os inserted by the 
transmitter during character assembly. CRC is also 
calculated and is automatically checked to validate frame 
transmission. At the end of transmission, the status of 
a received frame is available in the status registers. In 
SDLC mode, the SCC must be programmed to use the 
SDLC CRC polynomial, but the generator and checker 
may be preset to all Is or all Os. The CRC is inverted 
before transmission and the receiver checks against the 
bit pattern 0001110100001111. 

NRZ, NRZI or FM coding may be used in any lx 
mode. The parity options available in Asynchronous 
modes are available in Synchronous modes. 

The SCC can be conveniently used under DMA control 
to provide high speed reception or transmission. In 
reception, for example, the SCC can interrupt the CPU 
when the first character of a message is received. The 
CPU then enables the DMA to transfer the message to 
memory. The SCC then issues an end— of— frame 
interrupt and the CPU can check the status of the 
received message. Thus, the CPU is freed for other 
service while the message is being received. The CPU 
may also enable the DMA first and have the SCC 
interrupt only on end— of— frame. This procedure allows 
all data to be transferred via the DMA. 

SDLC Loop Mode. The SCC supports SDLC Loop 
mode in addition to normal SDLC. In an SDLC Loop, 
there is a primary controller station that manages the 
message traffic flow on the loop and any number of 
secondary stations. In SDLC Loop mode, the SCC 
performs the functions of a secondary station while an 
SCC operating in regular SDLC mode can act as a 
controller (Figure 5). 

A secondary station in an SDLC Loop is always 
listening to the messages being sent around the loop, 
and in fact must pass these messages to the rest of 
the loop by re— transmitting them with a one-bit-time 



CONTROLLER 



SECONDARY (T1 ) f SECONDARY M 



SECONDARY #2 ) ( SECONDARY »3 



delay. The secondary station can place its own 
message on the loop only at specific times. The 
controller signals that secondary stations may transmit 
messages by sending a special character, called an EOP 
(End Of Poll), around the loop. The EOP character is 
the bit pattern 11111110. Because of zero insertion 
during messages, this bit pattern is unique and easily 
recognized. 

When a secondary station has a message to transmit 
and recognizes an EOP on the line, it changes the last 
binary 1 of the EOP to a before transmission. This 
has the effect of turning the EOP into a flag sequence. 
The secondary station now places its message on the 
loop and terminates the message with an EOP. Any 
secondary stations further down the loop with messages 
to transmit can then append their messages to the 
message of the first secondary station by the same 
process. Any secondary stations without messages to 
send merely echo the incoming messages and are 
prohibited from placing messages on the loop (except 
upon recognizing an EOP). 

SDLC Loop mode is a programmable option in the SCC. 
NRZ, NRZI, and FM coding may all be used in SDLC 
Loop mode. 

Baud Rate Generator. Each channel in the SCC 
contains a programmable baud rate generator. Each 
generator consists of two 8-bit time constant registers 
that form a 16-bit time constant, a 16-bit down 
counter, and a flip-flop on the output producing a 
square wave. On startup, the flip-flop on the output 
is set in a High state, the value in the time constant 
register is loaded into the counter, and the counter 
starts counting down. The output of the baud rate 
generator toggles upon reaching 0, the value in the time 
constant register is loaded into the counter, and the 
process is repeated. The time constant may be changed 
at any time, but the new value does not take effect 
until the next load of the counter. 

The output of the baud rate generator may be used as 
either the transmit clock, the receive clock, or both. It 
can also drive the Digital Phase— Locked Loop (see next 
section) . 

If the receive clock or transmit clock is not programmed 
to come from the TRxC pin, the output of the baud 
rate generator may be echoed out via the TRxC pin. 

The following formula relates the time constant to the 
baud rate where PCLK or RTxC is the baud rate 
generator input frequency in Hz. The clock mode is 1, 
16, 32, or 64 as selected in Write Register 4, bits D6 
and D7. Synchronous operation modes should select 1 
and Asynchronous should select 16, 32, or 64. 



Figure 5. An SDLC Loop 



_. _ PCLK or RTxC Frequency - 

Time Constant = -^-7= — . , , — , , - 2 
2 (Baud Rate) (C ock Mode 



227 



Digital Phase— Locked Loop. The SCC contains a 
Digital Phase— Locked Loop (DPLL) to recover clock 
information from a data stream with NRZI or FM 
encoding. The DPLL is driven by a clock that is 
nominally 32 (NRZI) or 16 (FM) times the data rate. 
The DPLL uses this clock, along with the data stream, 
to construct a clock for the data. This clock may then 
be used as the SCC receive clock, the transmit clock, or 
both. 

For NRZI encoding, the DPLL counts the 32x clock to 
create nominal bit times. As the 32x clock is counted, 
the DPLL is searching the incoming data stream for 
edges (either 1 to or to 1). Whenever an edge is 
detected, the DPLL makes a count adjustment (during 
the next counting cycle), producing a terminal count 
closer to the center of the bit cell. 

For FM encoding, the DPLL still counts from to 31, 
but with a cycle corresponding to two bit times. When 
the DPLL is locked, the clock edges in the data stream 
should occur between counts 15 and 16 and between 
counts 31 and 0. The DPLL looks for edges only 
during a time centered on the 15 to 16 counting 
transition. 

The 32x clock for t he DP LL can be programmed to 
come from either the RTxC input or the output of the 

baud rate generator. The DPLL output may be 

programmed to be echoed out of the SCC via the TRxC 
pin (if this pin is not being used as an input). 

Data Encoding. The SCC may be programmed to 
encode and decode the serial data in four different ways 
(Figure S). In NRZ encoding, a 1 is represented by a 
High level and a is represented by a Low level. In 
NRZI encoding, a 1 is represented by no change in level 
and a is represented by a change in level. In FM1 
(more properly, bi— phase mark), a transition occurs at 
the beginning of every bit cell. A 1 is represented by 
an additional transition at the center of the bit cell and 
a is represented by no additional transition at the 
center of the bit cell. In FMO (bi-phase space), a 



transition occurs at the beginning of every bit cell. A 
is represented by an additional transition at the center 
of the bit cell, and a 1 is represented by no additional 
transition at the center of the bit cell. In addition to 
these four methods, the SCC can be used to decode 
Manchester (bi-phase level) data by using the DPLL in 
the FM mode and programming the receiver for NRZ 
data. Manchester encoding always produces a transition 
at the center of the bit cell. If the transition is to 
1, the bit is a 0. If the transition is 1 to 0, the bit is 
a 1. 

Auto Echo and Local Loopback. The SCC is capable 
of automatically echoing everything it receives. This 
feature is useful mainly in Asynchronous modes, but 
works in Synchronous and SDLC modes as well. In 
Auto Echo mode, TxD is RxD. Auto Echo mode can 
be used with NRZI or FM encoding with no additional 
delay, because the data stream is not de code d before 
re-transmission. In Auto Echo mode, the CTS input is 
ignored as a transmitter enable (although transitions on 
this input can still cause interrupts if programmed to do 
so). In this mode, the transmitter is actually bypassed 
and the programmer is responsible for disabling 
transmitter interrupts and WAIT/REQUEST on transmit. 

The SCC is also capable of local loopback. In this 
mode TxD is RxD, just as in Auto Echo mode. 
However, in Local Loopback mode, the internal transmit 
data is tied to the internal receive data and Rx D is 
ignored (except to be echoed out via TxD). The CTS 
and DCD inputs are also ignored as transmit and 
receive enables. However, transitions on these inputs 
can still cause interrupts. Local Loopback works in 
Asynchronous, Synchronous and SDLC modes with NRZ, 
NRZI, or FM coding of the data stream. 

I/O Interface Capabilities. The SCC offers the choice 
of Polling, Interrupt (vectored or nonvectored), and 
Block Transfer modes to transfer data, status, and 
control information to and from the CPU. The Block 
Transfer mode can be implemented under CPU or DMA 
control. 




228 



Polling. All interrupts are disabled. Three status 
registers in the SCC are automatically updated whenever 
any function is performed. For example, end-of-frame 
in SDLC mode sets a bit in one of these status 
registers. The idea behind polling is for the CPU to 
periodically read a status register until the register 
contents indicate the need for data to be transferred. 
Only one register needs to be read; depending on its 
contents, the CPU either writes data, reads data, or 
continues. Two bits in the register indicate the need 
for data transfer. An alternative is a poll of the 
Interrupt Pending register to determine the source of an 
interrupt. The status for both channels resides in one 
register. 

Interrupts. When an SCC r esponds to an Interrupt 
Acknowledge signal (INTACK) from the CPU, an 
interrupt vector may be placed on the data bus. This 
vector is written in WR2 and may be read in RR2A or 
RR2B (Figures 10 and 11). 

To speed interrupt response time, the SCC can modify 
three bits in this vector to indicate status. If the 
vector is read in Channel A, status is never included; if 
it is read in Channel B, status is always included. 

Each of the six sources of interrupts in the SCC 
(Transmit, Receive, and External/Status interrupts in 
both channels) has three bits associated with the 
interrupt source: Interrupt Pending (IP), Interrupt Under 
Service (IUS), and Interrupt Enable (IE). Operation of 
the IE bit is straightforward. If the IE bit is set for a 
given interrupt source, then that source can request 
interrupts. The exception is when the MIE (Master 
Interrupt Enable) bit in WR9 is reset and no interrupts 
may be requested. The IE bits are write only. 

The other two bits are related to the interrupt priority 
chain (Figure 7). As a microprocessor peripheral, the 
SCC may request an interrupt only when no higher 
priority device is requesting one, e.g., when IEI is High. 
If the dev ice in question requests an inte rrupt, it pulls 
down INT. The CPU then responds with INTACK, and 
the interrupting device places the vector on the data 
bus. 



In the SCC, the IP bit signals a need for interrupt 
servicing. When an IP bit is 1 and the IEI input is 
High, the INT output is pulled Low, requesting an 
interrupt. In the SCC, if the IE bit is not set by 
enabling interrupts, then the IP for that source can 
never be set. The IP bits are readable in RR3A. 

The IUS bits signal that an interrupt request is being 
serviced. If an IUS is set, all interrupt sources of lower 
priority in the SCC and external to the SCC are 
prevented from requesting interrupts. The internal 
interrupt sources are inhibited by the state of the 
internal daisy chain, while lower priority devices are 
inhibited by the IEO output of the SCC being pulled 
Low and propagated to subsequent peripherals. An IUS 
bit is set during an Interrupt Acknowledge cycle if there 
are no higher priority devices requesting interrupts. 

There are three types of interrupts: Transmit, Receive, 
and External/Status. Each interrupt type is enabled 
under program control with Channel A having higher 
priority than Channel B, and with Receiver, Transmit, 
and External/Status interrupts prioritized in that order 
within each channel. When the Transmit interrupt is 
enabled, the CPU is interrupted when the transmit 
buffer becomes empty. (This implies that the 
transmitter must have had a data character written into 
it so that it can become empty.) When enabled, the 
receiver can interrupt the CPU in one of three ways: 

■ Interrupt on First Receive Character or 
Special Receive Condition. 

■ Interrupt on All Receive Characters or 
Special Receive Condition. 

■ Interrupt on Special Receive Condition Only. 

Interrupt on First Character or Special Condition and 
Interrupt on Special Condition Only are typically used 
with the Block Transfer mode. A Special Receive 
Condition is one of the following: receiver overrun, 
framing error in Asynchronous mode, end-of-frame in 
SDLC mode and, optionally, a parity error. The Special 



PERIPHERAL 

IEI Do- Or INT INTACK IEO 



-7T 



IEI D -D 7 INT INTACK IEO 



nrm 



IEI O0-O7 INT INTACK 



INT . 



+ s v 

1 



Figure 7. Interrupt Schedule 



229 



Receive Condition interrupt is different from an ordinary 
receive character available interrupt only in the status 
placed in the vector during the Interrupt Acknowledge 
cycle. In Interrupt on First Receive Character, an 
interrupt can occur from Special Receive Conditions any 
time after the first receive character interrupt. 

The main function of the External/Status interrupt is to 
monitor the signal transitions of the CTS, DCD, and 
SYNC pins; however, an External/Status interrupt is 
also caused by a Transmit Underrun condition, or a zero 
count in the baud rate generator, or by the detection of 
a Break (Asynchronous mode), Abort (SDLC mode) or 
EOP (SDLC Loop mode) sequence in the data stream. 
The interrupt caused by the Abort or EOP has a special 
feature allowing the SCC to interrupt when the Abort or 
EOP sequence is detected or terminated. This feature 
facilitates the proper termination of the current message, 
correct initialization of the next message, and the 
accurate timing of the Abort condition in external logic 
in SDLC mode. In SDLC Loop mode, this feature 



allows secondary stations to recognize the wishes of the 
primary station to regain control of the loop during a 
poll sequence. 

CPU/DMA Block Transfer. The SCC provides a 
Block Transfer mode to accommodate CPU block 
transfer functions and D MA co n trollers. The Block 
Transfer mode uses the WAIT/REQUEST output in 
conjuc ti on with t he Wait/Request bits in WR1. The 
WAIT/REQUE ST ou tput can be defined under software 
control as a W AIT line in the CPU Block Transfer 
mode or as a REQUEST line in the DMA Block 
Transfer mode. 



To a DMA controller, the SCC REQUEST output 
indicates that the SCC is ready to transfer data to or 
from memory. To the CPU, the WAIT line indicates 
that the SCC is not ready to transfer data, thereby 
reques ting that the CPU extend the I/O cycle. The 
DTR/REQUEST line allows full— duplex operation under 
DMA control. 



Architecture 

The SCC internal structure includes two full-duplex 
channels, two baud rate generators, internal control and 
interrupt logic, and a bus interface to a nonmultiplexed 
bus. Associated with each channel are a number of 
read and write registers for mode control and status 
information, as well as logic necessary to interface to 
modems or other external devices (Figure 8). 



The logic for both channels provides formats, 
synchronization, and validation for data transferred to 
and from the channel interface. The modem control 
inputs are monitored by the control logic under program 
control. All of the modem control signals are general- 
purpose in nature and can optionally be used for 
functions other than modem control. 



INTERNAL 
CONTROL 
LOGIC 



INTERRUPT 
CONTROL 
LINES 



til 

+ 5VONDPCLK 



St It 



DISCRETE 
CONTROL 
A STATUS 



DISCRETE 
CONTROL 
A STATUS 



CHANNEL B 



. j SERIAL DATA 

\ } CHANNEL CLOCKS 

■ SYNC 



. j SERIAL DATA 

\ ) CHANNEL CLOCKS 

SYNC 

WAITIREQUEST 



Figure 8. Block Diagram of SCC Architecture 



230 



CPU 110 



I/O DATA BUFFER 



INTERNAL DATA BUS 



16-BIT DOWN | COUNTER 



HZh 



HUNT MODE (BISYNC) 



NRZI DECODE 



31 



RECEIVE 
ERROR 

LOGIC 



RECEIVE 
SHIR REGISTER 
(8 BITS) 



rr ttt 



CfIC DELAY 
REGISTER 
(6 BITS) 



SDLC CRC CRC CHECKER 



TRANSMIT DATA 



20-BIT TRANSMIT | SHIFT REGISTER | 



li 



CflC GENERATOR 



INTERNAL T«D 



NRZI ENCODE 



- DPLL OUTPUT 



BR GENERATOR OUTPUT - 
DPLL OUTPUT - 
TR*~C - 



• RECEIVE CLOCK 

■ TRANSMIT CLOCK 

• DPLL CLOCK 

- BR GENERATOR CLOCK 



Figure 0. Data Path 



The register set for each channel includes ten control 
(write) registers, two sync-character (write) registers, 
and four status (read) registers. In addition, each baud 
rate generator has two (read/write) registers for holding 
the time constant that determines the baud rate. 
Finally, associated with the interrupt logic is a write 
register for the interrupt vector accessible through either 
channel, a write only Master Interrupt Control register 
and three read registers: one containing the vector with 
status information (Channel B only), one containing the 
vector without status (Channel A only), and one 
containing the Interrupt Pending bits (Channel A only). 

The registers for each channel are designated as follows: 

WR0-WR15 — Write Registers through 
15. 

RR0-RR3, RR10, RR12, RR13, RR15 — 
Read Registers through 3, 10, 12, 13, 
15. 

Table 1 lists the functions assigned to each read or 
write register. The SCC contains only one WR2 and 
WR9, but they can be accessed by either channel. All 
other registers are paired (one for each channel). 

Data Path. The transmit and receive data path 
illustrated in Figure 9 is identical for both channels. 
The receiver has three 8-bit buffer registers in a FIFO 
arrangement, in addition to the 8-bit receive shift 
register. This scheme creates additional time for the 
CPU to service an interrupt at the beginning of a block 
of high speed data. Incoming data is routed through 
one of several paths (data or CRC) depending on the 
selected mode (the character length in Asynchronous 
modes also determines the data path). 

The transmitter has an 8-bit Transmit Data buffer 
register loaded from the internal data bus and a 20— bit 
Transmit Shift register that can be loaded either from 



Programming 

The SCC contains write registers in each channel that 
are programmed by the system separately to configure 
the functional personality of the channels. 

Z85C30 

In the SCC, register addressing is direct for the data 
registers only, which are selected by a High on the D/C 
pin. In all other cases (with the exception of WRO and 
RRO), programming the write registers requires two 
write operations and reading the read registers requires 
both a write and a read operation. The first write is 
to WRO and contains three bits that point to the 
selected register. The second write is the actual control 
word for the selected register, and if the second 
operation is read, the selected read register is accessed. 



the synchronous character registers or from the Transmit 
Data register. Depending on the operational mode, 
outgoing data is routed through one of four main paths 
before it is transmitted from the Transmit Data output 
(TxD). 

Read Roister Function! 

RRO Transmit/Receive buffer status and External status 

RR1 Special Receive Condition status 

RR2 Modified interrupt vector (Channel B only) 

Unmodified interrupt vector (Channel A only) 

RR3 Interrupt Pending bits (Channel A only) 

RR8 Receive buffer 

RR10 Miscellaneous status 

RR12 Lower byte of baud rate generator time constant 

RR13 Upper byte of baud rate generator time constant 

RR15 External/Status interrupt information 



Writ* Register Functions 


WRO 


CRC initialize, initialization commands for the 




various modes. Register Pointers 


WRl 


Transmit/Receive interrupt and data transfer mode 




definition 


WR2 


Interrupt vector (accessed through either channel) 


WR3 


Receive parameters and control 


WR4 


Transmit/Receive miscellaneous parameters and 




modes 


WRS 


Transmit parameters and controls 


WR6 


Sync characters or SDLC address held 


WR7 


Sync character or SDLC flag 


WR8 


Transmit buffer 


WR9 


Master interrupt control and reset (accessed 




through either channel) 


WR10 


Miscellaneous transmitter' receiver control bits 


WR11 


Clock mode control 


WR12 


Lower byte of baud rate generator time constant 


WR13 


Upper byte of baud rate generator time constanl 


WR14 


Miscellaneous control bits 


WR15 


External/Status interrupt control 



Table 1. Read and Writ* Regular Functions 



All of the registers in the SCC, including the data 
registers, may be accessed in this fashion. The pointer 
bits are automatically cleared after the read or write 
operation so that WRO (or RRO) is addressed again. 

Z80C30 

All SCC registers are directly addressable. How the 
SCC decodes the address placed on the address/data 
bus at the beginning of a Read or Write cycle is 
controlled by a command issued in WROB. In the 
Shift Right mode the channel select A/B is taken from 
AD Q and the state of AD 5 is ignored. In the Shift Left 
mode the channel select A/B is taken from AD 5 and 
the state of AD Q is ignored. AD 7 and AD 6 are always 
ignored as address bits and the register address itself 
occupies AD 4 — AD,. 



232 



Z85C30/Z80C30 



The system program first issues a series of commands 
to initialize the basic mode of operation. This is 
followed by other commands to qualify conditions within 
the selected mode. For example, the Asynchronous 
mode, character length, clock rate, number of stop bits, 
even or odd parity might be set first. Then the 
interrupt mode would be set, and finally, receiver or 
transmitter enable. 

Read Registers. The SCC contains eight read registers 
(actually nine, counting the receive buffer (RR8) in each 
channel). Four of these may be read to obtain status 
information (RRO, RR1, RR10, and RR15). Two 



registers (RR12 and RR13) may be read to learn the 
baud rate generator time constant. RR2 contains either 
the unmodified interrupt vector (Channel A) or the 
vector modified by status information (Channel B). 
RR3 contains the Interrupt Pending (IP) bits (Channel 
A). Figure 10 shows the formats for each read register. 

The status bits of RRO and RR1 are carefully grouped 
to simplify status monitoring; e.g., when the interrupt 
vector indicates a Special Receive Condition interrupt, all 
the appropriate error bits can be read from a single 
register (RR1). 



Read Register 

| D T | D« | D, | O. | P, | D, ! D, ^D, 



Li 



Rx character available 

ZERO COUNT 

- T« BUFFER EMPTY 
" DCD 

- SYNCfHUNT 

- CTS 

" Tx UNDERRUNIEOM 
" BREAK/ABORT 



Read Register 10 



D, 0, D, DjD, 0, D, Dj 



Li" 



■ LOOP SENDING 



- TWO CLOCKS MISSING 

- ONE CLOCK MISSING 



Read Register 1 

| D, D t D. ' D. ' Oj ' D; D, ' D D | 



ALL SENT 
RESIDUE CODE 2 

■ RESIDUE CODE 1 

- RESIDUE CODE 

- PARITY ERROR 

■ Rx OVERRUN ERROR 

■ CRC'FRAMING ERROR 

■ END OF FRAME (SDLC) 



Read Register 12 



— TC, 



■ TC, 

■ TC, 

■ TC, 

■ TCs 

■ TC, 

■ TC, 



Read Register 2 



I u 

I Vi 



► INTERRUPT VECTOR ■ 



•MODIFIED IN B CHANNEL 



Read Register 13 

|P T |0 t |D b ; D t |P 3 ] D; ] D, 'fJ,, | 



TC, 
TC, 

TC„ 



• TC„ 
■ TC„ 
TC„ 



Read Register 3 

| D, 1 D, ! D, D, Dj D, i D, ! D | 

I 



CHANNEL B EXT/STAT IP' 
CHANNEL B Tx IP* 
CHANNEL B Ri IP* 
CHANNEL A EXT/STAT IP* 
CHANNEL A Tx IP" 
CHANNEL A Rx IP* 



Read Register 15 

| 0, ' D s j Dj j D« : D 3 j D; j D,[ D | 

L. 



Li 



ZERO COUNT IE 



■ SYNCfHUNT IE 



- TxUNDERRUN/EOMIE 

- BREAK/ABORT IE 



•ALWAYS IN B CHANNEL 



Figure 10. Read Register Bit Functions 



See FIFO section for more register information. 



233 



Write Registers. The SCC contains 13 write registers 
(14 counting WR8, the transmit buffer) in each channel. 
These write registers are programmed separately to 
configure the functional "personality" of the channels. 
In addition, there are two registers (WR2 and WR9) 



shared by the two channels that may be accessed 
through either of them. WR2 contains the interrupt 
vector for both channels, while WR9 contains the 
interrupt control bits. Figure 11 shows the format of 
each write register. 



Write Register (Z8530) 

| D, | D. | D, | D. | D, | D, j D, 1 07| 



Writ* Register 1 



REGISTER 
REGISTER 1 



REGISTER E 
REGISTER » 
REGISTER 10 

11 



EXT INT ENABLE 
Tx INT ENABLE 
PARITY IS SPECIA 

B. INT DISABLE 

Rx INT ON FIRST CHARACTER OR SPECIAL 
INT ON ALL Rx CHARACTERS OR SPECIAL 
flx INT ON SPECIAL CONDITION ONLV 



■ WAIT'DMA REQUEST ON RECEIVE/TRANSMIT 

■ WAIT/DMA REQUEST FUNCTION 



■ WAITlDMA REQUEST ENABLE 



Writ* Register 2 

| D, | D, ; D, I D t j 0, | D, I D, ! Q ~] 



POINT HIGH 

RESET EXT/STAT INTERRUPTS 
SEND ABORT (SDLC) 
ENABLE INT ON NEXT R* CHARACTER 
RESET TxINT PENDINO 



RESET HIGHEST IUS 



I v, 



> INTERRUPT VECTOR 



NULL CODE 

RESET ft* CRC CHECKER 



Write Register 3 

L 



Write Register (Z8030) 

| P. 1 D t i Ds P. ' P 3 j Dj | D, p„ j 



NULL CODE 
NULL CODE 
SELECT SHIFT LEFT M( 
SELECT SHIFT RIGHT k 



Vz 



Rx ENABLE 

SYNC CHARACTER LOAD INHIBIT 
ADDRESS SEARCH MODE (SDLC) 
Rx CRC ENABLE 
ENTER HUNT MODE 
AUTO ENABLES 



Rx S BITS/CHARACTER 
Rx 7 BITS/CHARACTER 
Rx 6 BITS/CHARACTER 
Rx 8 BITSJ CHARACTER 



NULL CODE 
NULL CODE 

RESET EXT/STATUS INTERRUPTS 
SEND ABORT 

ENABLE INT ON NEXT Rx CHARACTER 
RESET Tx INT PENDING 
ERROR RESET 
RESET HIGHEST IUS 



Write Register 6 



| 0. D t D t P. Dj D; D, | | 



NULL CODE 

RESET Rx CRC CHECKER 
RESET Tx CRC GENERATOR 
RESET T. UNDERRUNfEOM LATCH 



' B CHANNEL ONLV 



SYNC? 
SYNCi 
SYNC 7 
SYNCj 
AOR7 



SYNCfi 
SYNCrj 
SYNCg 
SYNCj 
ADR« 
ADR e 



SYNCj 

SYNC S 

SYNCs 

SYNCi 

ADRt 

ADR 4 



r n 

sync 4 sync 3 

SYNC* SYNC3 

SYNC* SYNC3 

SYNCq 1 

ADR* ADRj 

ADR* x 



Write Register 4 

I D, i D t j D^ D, ! Dj ] D, j D, [ I 



li 



PARITY ENABLE 
PARITY EVEN'ODD 



SYNC MODES ENABLE 

1 STOP BIT/CHARACTER 
1V, STOP BIT&CHARACTER 

2 STOP BITS/CHARACTER 



8 BIT SYNC CHARACTER 
16 BIT SYNC CHARACTER 
SDLC MODE 101111110 FLAG) 
EXTERNAL SYNC MODE 



XI CLOCK MODE 
X16 CLOCK MODE 
X32 CLOCK MODE 
X64 CLOCK MODE 



Write Register 5 

|p r I b ' D s I P, [ D : , j D." p . ' p„ I 



CRC ENABLE 
RTS 

SDLCrCRC 16 
Tx ENABLE 
SEND BREAK 



Tx 5 BITS (OR LESSVCHARACTER 
Tx 7 BITS/CHARACTER 
Tx 6 BITS/CHARACTER 
Tx B BITS/CHARACTER 



■ DTR 



SYNC; 
SYNC 2 
SYNCj 



SYNC, SYNCo 
SYNC, SYNCo 
SYNC, SYNCo 



MONOSVNC, 8 BITS 
MONOSYNC. 6 BITS 
BISYNC. 16 BITS 
BISYNC. 12 BITS 
SDLC 

SDLC (ADDRESS RANGE) 



Figure 11. Write Register Bit Functions 



234 



Write Register 7 

| D, | D. i D, | P. | Pi | D, | 0. | P." 



L 



r n 



SYNCt SYNCo SYNCs SYNC. SYNC 3 

SYNCs SYNC* SYNCi SYNC 2 SYNC, 

SYNC.s SYNC,. SYNC, 3 SYNC: SYNC, 

SYNC,, SYNCo SYNC, SYNCo SYNCj 



1 



SYNC; SYNC, SYNCo MONOSYNC. fl BITS 

SYNCo x x MONOSYNC. S BITS 

SYNCo SYNCs SYNCi BISYNC. 16 BITS 

SYNC, SYNCs SYNC. BISYNC, 12 BITS 

1 1 SDLC 



Writ* Register 9 

| D r D t Dj 0, D] 0) 0, ' 0„ | 



NV 

- DLC 

- MIE 

■ STATUS HIGHfSTATUS LOW 



NO RESET 
CHANNEL RESET B 
CHANNEL RESET A 
FORCE HARDWARE RESET 



Write Register 10 

L 



fl BIT78 6TT SYNC 
LOOP MODE 

ABORT/FLAG ON UNDERRUN 
MARK/FLAC IDLE 
GO ACTIVE ON POLL 



NRZ 
NRZI 

FH1 (TRANSITION » 1) 
FMO (TRANSITION = 0) 



Write Register 11 

| D, D t 0, D. D, : D, 0. | 



TRxC OUT = XTAL OUTPUT 
TfixC OUT = TRANSMIT CLOCK 
TRiC OUT = BR GENERATOR OUTPUT 
TRiC OUT = DPLL OUTPUT 
■ TRiC O'l 



TRANSMIT CLOCK = RTxC PIN 

TRANSMIT CLOCK = TRiC PIN 

TRANSMIT CLOCK = BR GENERATOR OUTPUT 

TRANSMIT CLOCK = DPLL OUTPUT 



RECEIVE CLOCK = RTiC PIN 

RECEIVE CLOCK - TflxC PIN 

RECEIVE CLOCK = BR GENERATOR OUTPUT 

RECEIVE CLOCK = DPLL OUTPUT 

RTiC XTAUNO XTAL 



Write Register 12 

[ D. D t P. D, ; 0; D; D, D r | 

L, 



. TCj 
- TCj 

■ TC. 
. TC S 

■ IC, 

■ TC, 



Write Register 13 

I p, I e. ; d, ; p. ; o, ! p. | p, | p,"| 

L TC, 
. TC, 



. TC,j 
. TC,i 
. TC„ 
. TC, 



Write Register U 

| 0; P t Pj D. Dj D; P, P C | 

L 



BR GENERATOR ENABLE 
BR GENERATOR SOURCE 
DTR/REOUEST FUNCTION 
AUTO ECHO 



- LOCAL LOOPBACK 

NULL COMMAND 
ENTER SEARCH MODE 
RESET MISSING CLOCK 
DISABLE DPLL 

SET SOURCE = BR GENERATOR 
SET SOURCE ■ RTiiC 
SET FM MODE 
SET NRZI MODE 



Write Register 15 

| P. ! D t 1 D. ' P, I D ; | D; j D, | Ds [ 

L. 



ZERO COUNT IE 

■ FIFO ENABLE 

■ DCD IE 

- SYNC/MUNT IE 

- CTS IE 

- Tx UNDERRUN' EOM IE 



Figure 11. Write Register Bit Functions (Continued) 

235 



Z85C30 Timing 



The SCC generates internal control signals from WR 
and RD that are related to PCLK, Since PCLK has no 
phase relationship with WR and RD, the circuitry 
generating these internal control signals must provide 
time for metastable conditions to disappear. This gives 
rise to a recovery time related to PCLK. The recovery 
time applies only between bus transactions involving the 
SCC. The recovery time required _for proper operation is 
specified from the falling edge of WR or RD in the first 
transaction involving the SCC to the falling edge of WR 



or RD in the second transaction involving the SCC. 
This time must be at least 4 PCLK regardless of which 
register or channel is being accessed. 

Read Cycle Timing. Figure 12 illustrates Read cycle 
timing. Addresses on A/B and D/C and the status on 
INTACK must remain stable throughout the_ cycle. If 
CE falls after RD falls or if it rises before RD rises, the 
effective RD is shortened. 



Alt, DIC 



ADDRESS VALID 



xz: 



INTACK 



SB 



s 



x 



Figure 12. Read Cycle Timing 



Write Cycle Timing. Figure 13 illustrates Write cycle 
timing. Addresses on A/B and D/C and the status on 
INTACK must remain stable throughout the cycle. If 



CE falls after WR falls or if it rises before WR rises, 
the effective WR is shortened. Data must be valid 
before the falling edge of WR. 



a;b, oic 



AODRESS VALID 



CE 



Figure 13. Write Cycle Timing 



Interrupt Acknowledge Cycle Timing. Figure 14 
illustrates Interrup t Acknowledge cycle timing. Between 
the time INTACK goes Low and the falling edge of RD, 
the internal and external IEI/IEO daisy chains settle. If 
there is an interrupt pending in the SCC and IEI is 



INTACK 



KB 



High when RD falls, the Acknowledge cycle is intended 
for the SCC. In this case, the SCC may be 
programmed to respond to RD Low by placing its 
interrupt vector on D Q — D 7 and it then sets the 
appropriate Interrupt-Under-Service latch internally. 



y 



f 



x 



Figure 14. Interrupt Acknowledge Cycle Timing 



236 



Z80C30 Timing 



The SCC generates internal control signals from AS and 
DS that are related to PCLK. Since PCLK has no 
phase relationship with AS and DS, the circuitry 
generating these internal control signals must provide 
time for metastable conditions to disappear. This gives 
rise to a recovery time related to PCLK. The recovery 
time applies only between bus transactions involving the 
SCC. The recovery time required for proper operation is 
specified from the falling edge of DS in the first 



transaction involving the SCC to the falling edge of DS 
in the second transaction involving the SCC. 

Read Cycle Timing. Figure 15 illustrates Read cycle 
timing. The add ress on AD Q -AD 7 and the state of 
CS. and INTACK are latched by the rising edge of AS. 
R/W must be High to indicate a Read cycle. CS t 
must also be High for the Read cycle to occur. The 
data bus drivers in the SCC are then enabled while DS 
is Low. 



IS L 

7 ^ 



( X DATA VALID ) 

IZ7 ^ 

~7 ^ 
S / 

Figure 15. Read Cycle Timing 



Write Cycle Timing. Figure 16 illustrates Write cycle R/W must be Low to indicate a Write cycle. CS 1 
timing. The address on AD -AD 7 and the state_of must be High for the Write cycle to occur. DS Low 
CS and INTACK are latched by the rising edge of AS. strobes the data into the SCC. 



DS 



^ / 

7 \ 

")( ADDRESS )Q( DATA ) (~ 

\ d 

/ 

\ r 

Figure 16. Write Cycle Timing 



237 



Interrupt Acknowledge Cycle Timing. Figure 17 
illustrates Interrupt Acknowledge cycle timing The 
address on AD Q -AD 7 and the state of CS Q and 
INTACK ar e latche d by the rising edge of_ AS. 
However, if INTACK is Low, the address and CS„ are 
ignored. The state of the R/W and CSj are also 
ignored for the duration of the Interrupt Acknowledge 
cycle. Between the rising edge of AS and the falling 



edge of DS, the internal and external IEI/IEO daisy 
chains settle. If there is an interrupt pending in the 
SCC and IEI is High when DS falls, the Acknowledge 
cycle was intended for the SCC. In this case, the SCC 
may be programmed to respond to RD Low by placing 
its interrupt vector on D -D ? and it then internally sets 
the appropriate Interrupt-Under-Service latch. 



X 



-fj- 
-ff- 



S L 



-tf- 
-/>- 



" X — ) — * — czx 



s 



Figure 17. Interrupt Acknowledge Cycle Timing 



FIFO 



FIFO Enhancements. When used with a DMA 
controller, the Z85C30 FIFO enhancement maximizes the 
SCO's ability to receive high speed back-to-back SDLC 
messages while minimizing frame overruns due to CPU 
latencies in responding to interrupts. 



Additional logic was added to the industry standard 
NMOS SCC consisting of a 10 deep by 19 bit status 
FIFO, 14— bit receive byte counter, and control logic as 
shown in Figure 18. The 10 x 19 bit status FIFO is 
separate from the existing three byte receive data FIFO. 



SCC STATUS REG 
(EXISTING) 



14 BIT BYTE COUNTER 



—RESET ON FLAG DETECT 
- INCREMENT ON BYTE DET 
-ENABLE COUNT IN SDLC 



CRC ERROR 
10X19 BIT FIFO ARRAY 



- - 6 - BITS 



f...R 



6 - BITS 

LBBJ _ 

INTERFACE TO SCC 



BITS . 



— | EN [ 



4 BIT COMPARATOR 
OVER EQUAL 



FIFO DATA AVAILABLE STATUS BIT 
STATUS BIT SET TO 1 
WHEN READING FROM FIFO 



WR(15) BIT 2 
SET ENABLES 
STATUS FIFO 



FIFO OVERFLOW STATUS BIT 

MSB OF RR{7) IS SET ON STATUS FIFO 

OVERFLOW 

IN SDLC MODE THE FOLLOWING DEFINITIONS APPLY 

- ALL SENT BYPASSES MUX AND EQUALS CONTENTS OF SCC STATUS REGISTER 

• PARITY BITS BYPASSES MUX AND DOES THE SAME 

• EOF IS SET TO 1 WHENEVER READING FROM THE FIFO 



Figure 18. SCC Status Register Modifications. 

238 



When the enhancement is enabled, the status in read 
register 1 (RR1) and byte count for the SDLC frame 
will be stored in the 10 x 19 bit status FIFO. This 
allows the DMA controller to transfer the next frame 
into memory while the CPU verifies the message was 
properly received. 

Summarizing the operation, data is received, assembled, 
loaded into the three byte receive FIFO before being 
transferred to memory by the DMA controller. When a 
flag is received at the end of an SDLC frame, the frame 
byte count from the 14-bit counter and five status bits 
are loaded into the status FIFO for verification by the 
CPU. The CRC checker is automatically reset in 
preparation for the next frame which can begin 
immediately. Since the byte count and status are saved 
for each frame, the message integrity can be verified at 
a later time. Status information for up to 10 frames 
can be stored before a status FIFO overrun could occur. 

FIFO Detail. For a better understanding of details of 
the FIFO operation, refer to the block diagram contained 
in Figure 18. 

Enable/Disable. This FIFO is implemented so that it 
is enabled when WR15 bit 2 is set and the SCC is in 
the SDLC/HDLC mode, otherwise the status register 
contents bypass the FIFO and go directly to the bus 
interface (the FIFO pointer logic is reset either when 
disabled or via a channel or power— on reset). When 
the FIFO mode is disabled, the SCC is completely 
downward-compatible with the NMOS Z8530. The 
FIFO mode is disabled on power-up (WR15 bit 2 is 
set to on reset). The effects of backward 
compatibility on the register set are that RR4 is an 
image of RRO, RR5 is an image of RR1, RR6 is an 
image of RR2 and RR7 is an image of RR3. For the 
details of the added registers, refer to Figure 20. The 
status of the FIFO Enable signal can be obtained by 
reading RR15 bit 2. If the FIFO is enabled, the bit 
will be set to 1; otherwise, it will be reset. 

Read Operation. When WR15 bit 2 is set and the 
FIFO is not empty, the next read to any of status 



register RR1 or the additional registers RR7 and RR6 
will actually be from the FIFO. Reading status register 
RR1 causes one location of the FIFO to be emptied, so 
status should be read after reading the byte count, 
otherwise the count will be incorrect. Before the FIFO 
underflows, it is disabled. In this case, the multiplexer 
is switched to allow status to read directly from the 
status register, and reads from RR7 and RR6 will 
contain bits that are undefined. Bit 6 of RR7 (FIFO 
Data Available) can be used to determine if status data 
is coming from the FIFO or directly from the status 
register, since it is set to 1 whenever the FIFO is not 
empty. 

Since not all status bits must be stored in the FIFO, 
the All Sent, Parity, and EOF bits will bypass the 
FIFO. The status bits sent through the FIFO will be 
Residue Bits (3), Overrun, and CRC Error. 

The sequence for proper operation of the byte count and 
FIFO logic is to read the registers in the following 
order: RR7, RR6, and RR1 (reading RR6 is optional). 
Additional logic prevents the FIFO from being emptied 
by multiple reads from RR1. The read from RR7 
latches the FIFO empty/full status bit (bit 6) and 
steers the status multiplexer to read from the SCC 
megacell instead of the status FIFO (since the status 
FIFO is empty). The read from RR1 allows an entry 
to be read from the FIFO (if the FIFO was empty, 
logic is added to prevent a FIFO underflow condition). 

Write Operation. When the end of an SDLC frame 
(EOF) has been received and the FIFO is enabled, the 
contents of the status and byte-count registers are 
loaded into the FIFO. The EOF signal is used to 
increment the FIFO. If the FIFO overflows, the MSB 
of RR7 (FIFO Overflow) is set to indicate the overflow. 
This bit and the FIFO control logic is reset by disabling 
and re-enabling the FIFO control bit (WR15 bit 2). 
For details of FIFO control timing during an SDLC 
frame, refer to Figure 19. 



INTERNAL BYTE STROBE 
INCREMENTS COUNTER 



DONT LOAD 
COUNTER ON 
1ST FLAG 
RESET BYTE 
COUNTER HERE 



RESET 

BYTE COUNTER 
LOAD COUNTER 
INTO FIFO AND 
INCREMENT PTR 



V f v i 1 » ■ » ' » ' 

INTERNAL BYTE STROBE 
INCREMENTS COUNTER 



RESET 

BYTE COUNTER 
LOAD COUNTER 
INTO FIFO AND 
INCREMENT PTR 



Figure 19. SDLC Byte Counting Detail. 



239 



Byte Counter Detail. The 14-bit byte counter allows 
for packets up to 16K bytes to be received. For a 
better understanding of its operation refer to Figures 18 
and 19. 

Enable. The byte counter is enabled in the 
SDLC/HDLC mode. 

Reset. The byte counter is reset whenever an SDLC 
flag character is received. The reset is timed so that 



the contents of the byte counter are successfully written 
into the FIFO. 

Increment. The byte counter is incremented by writes 
to the data FIFO. The counter represents the number 
of bytes received by the SCC, rather than the number 
of bytes transferred from the SCC. (These counts may 
differ by up to the number of bytes in the receive data 
FIFO contained in the SCC). 



T6 

A 1 



BCI BC I BC I BCI BCI BC 



- FIFO DATA AVAILABLE STATUS 

t . STATUS READS WILL COME FROM FIFO 

- STATUS READS WILL COME FROM SCC 

- FIFO OVERFLOW STATUS 

1 - FIFO OVERFLOWED DURING OPERATON 
- NORMAL 



| BC I BC I BC I BC I BC I BC I BC I BC I 
I 7 I 6 I 5 | 4 | 3 | 2 | l|o| 



L 



STATUS FIFO ENABLE CONTROL BIT 
1 . STATUS AND BYTE COUNT WILL BE 

HELD IN THE STATUS FIFO UNTIL READ 
O - STATUS WILL NOT BE HELD (SCC 
EMULATION MODE). 

• - NO CHANGE FROM HMOS SCC OFN 



Figure 20. SCC Additional Registers. 



Absolute Maximum Ratings 

Voltages on all pins with respect 

to GND -0.3 V to +7.0 V 

Operating Ambient 

Temperature See Ordering Information 

Storage Temperature -65°C to +150°C 



Stresses greater than those listed under Absolute Maximum 
Ratings may cause permanent damage to the device. This is 
a stress rating only; operation of the device at any condition 
above those indicated in the operational sections of these 
specifications is not implied. Exposure to absolute maximum 
rating conditions for extended periods may affect device 
reliability. 



Standard Test Conditions 

The DC characteristics and capacitance section below ■ +4.75 V < V cc < +5.25 V 
apply for the following standard test conditions, unless ■ GND = V 

otherwise noted. All voltages are referenced to GND. ■ T A as specified in Ordering Information 
Positive current flows into the referenced pin. 
Standard conditions are as follows: 




Standard Test Load Open-Drain Test Load 



240 



DC Symbol Parameter Mln Typ Max Unit Condition 



Charac- 
teristics 



Capacitance 



VlH 


Input High Voltage 


2.2 V cc + 0.3 


V 




VlL 


Input" Low Voltage 


-0.3 0.8 


V 




VOHI 


Output High Voltage 


2.4 


V 


Ioh = — 1-6 mA 


V OH2 


Output High Voltage 


Vcc-0.8 


V 


Ioh= -250 iiA 


Vol 


Output Low Voltage 


0.4 


V 


Iol= +2.0 mA 


In 

ML 


Input Leakage 


±10.0 


«A 


0.4 £ V IN s +2.4V 


IOL 


Output Leakage 


±10.0 


fA 


0.4 < Vout * +2.4V 


Icci 


Vcc Supply Current 


7 30 


mA 


Vcc = 5V Vih = 4.8V V| L = 0.2V 


V CC = 5 V ± 


5% unless otherwise specified, over specified temperature range. • 


Typical Ice was measured with oscillator off. 


Symbol 


Parameter 


Mln Max 


Unit 


Test Condition 




Input Capacitance 


10 


pF 


Unmeasured Pins 


CoUT 


Output Capacitance 


15 


pF 


Returned to Ground 




Bidirectional Capacitance 20 


pF 




f = 1 MHz, over 


specified temperature range. 









Unmeasured pins returned to ground. 



Miscellaneous Gate Count 6000 



241 



Z85C30 AC CHARACTERISTICS 









8 MHz 


10 


MHz 


Number 


Symbol 


Parameter 


Min Max 


Mln 


Max Notes t 


1 


TwPCI 


PCLK Low Width 


50 1000 


40 


1000 


2 


TwPCh 


PCLK High Width 


50 1000 


40 


1000 


3 


TfPC 


PCLK Fall Time 


10 




10 


4 


TrPC 


PCLIC.Rise Time 


10 




10 


5 


TcPC 


PCLK Cycle Time 


125 2000 


100 


2000 


6 


TsA(WR) 


Address to WR I Setup Time 


70 


50 




7 


ThA(WR) 


Address to WR T Hold Time 










8 


TsA(RD) 


Address to ED 1 Setup Time 


70 


50 




9 


ThA(RD) 


Address to RD T Hold Time 










10 


TslA(PC) 


INTACK to PCLK T Setup Time 


20 


20 





1 1 TslAifWR) 

12 ThlA(WR) 

13 TslAi(RD) 

14 ThlA(RD) 

15 ThlA(PC) 



INTACK to WR I Setup Time 
INTACK toWEl Hold Time 
INTACK to ED I Setup Time 
INTACK to RD T Hold Time 
INTACK to PCLK t Hold Time 



145 


145 

40 



130 


130 

30 



16 


TsCEIfWR) 


CE Low to WR i Setup Time 










17 


ThCEfWR) 


CE to WR f Hold Time 










18 


TsCEh(WR) 


CE" High to WR i Setup Time 


60 


50 




19 


TsCEI(RD) 


CE Low to ED" I Setup Time 








1 


20 


ThCE(RD) 


CE to ED T Hold Time 








1 


21 


TsCEh(RD) 


C"E High to ED I Setup Time 


60 


50 


1 


22 


TwRDI 


ED Low Width 


150 


125 


1 


23 


TdRD(DRA) 


ED l to Read Data Active Delay 










24 


TdRDr(DR) 


ED t to Read Data Not Valid Delay 










25 


TdRDf(DR) 


ED i to Read Data Valid Delay 


140 


120 




26 


TdRD(DRz) 


ED 1 to Read Data Float Delay 


40 


35 





NOTES: 

1. Parameter does not apply to Interrupt Acknowledge transactions. 
tUnits in nanoseconds (ns). 



Reset 

Timing 

Z85C30 



^ J^sH HS>*^ 



\ 



f~ 



Cycle 
Timing 

Z85C30 




f 



f 



-if- 



f 



-fS- 



242 



Z85C30 AC CHARACTERISTICS (Continued) 









8 MHz 


10 


MHz 




Number 


Symbol 


Parameter 


Min Max 


Mln 


Max 


Notes f 


27 


TdA(DR) 


Address Required Valid to Read Data 














Valid Delay 


220 




180 




28 


TwWRI 


WR Low Width 


150 


125 






29 


TsDW(WR) 


Write Data to WR I Setup Time 


10 


10 






30 


ThDW(WR) 


Write Data to WR t Hold Time 












31 


1 dWH(VV) 


wh J to Wait valid Delay 


170 




160 


4 


32 


TdRD(W) 


R?J 1 Wait Valid Delay 


170 




160 


4 


33 


TdWRf(REQ) 


WR 1 to W/REQ Not Valid Delay 


170 




160 




34 


TdRDf(REQ) 


RD I to W/REQ" Not Valid Delay 


170 




160 




35 


TdWRr(REQ) 


WR i DTR/REQ Not Valid Delay 


4TcPC 




4TcPG 




36 


TdRDr(REQ) 


RD t to DTR/REQ Not Valid Delay 


4TcPC 




4TcPC 




37 


TdPC(INT) 


PCLK 1 to INT Valid Delay 


500 




500 


4 


38 


TdlAi(RD) 


INTACK to RD I (Acknowledge) Delay 


150 




125 


5 


39 


TwRDA 


RD (Acknowledge) Width 


150 




125 




40 


TdRDA(DR) 


RD i (Acknowledge) to Read Data 














Valid Delay 


140 




120 




41 


TslEI(RDA) 


IEI to RD i (Acknowledge) Setup 














Time 


95 


95 






42 


ThlEI(RDA) 


IEI to RD t (Acknowledge) Hold Time 












43 


TdlEI(IEO) 


IEI to IEO Delay Time 


95 




90 




44 


TdPC(IEO) 


PCLK t to IEO Delay 


200 




175 




45 


TdRDA(INT) 


RD I to iNT Inactive Delay 


500 




500 


4 


46 


TdRD(WRQ) 


RD T to WR i Delay for No Reset 


15 


15 






47 


TdWRQ(RD) 


WR t to RD I Delay for No Reset 


15 


15 






48 


TwRES 


WR and RD Coincident Low for Reset 


150 


100 






49 


Trc 


Valid Access Recovery Time 


4TcPC 


4TcPC 




3 



NOTES: 

3. Parameter applies only between transactions involving the SCC. 

4. Open-drain output, measured with open-drain test load 

5. Parameter is system dependent. For any SCC in the daisy chain. TdlAi(RD) must be greater than the sum of TdPC(IEO) for the highest priority de- 
vice in the daisy chain, TslEI(RDA) for the SCC, and TdlElf(IEO) for each device separating them in the daisy chain. 



tUnits in nanoseconds (ns). 



243 



Z80C30 AC CHARACTERISTICS 



Preliminary 
8 MHz 10 MHz 



Number 


Symbol 


Parameter 


Min 


Max 


Min Max I 


Motes t 


1 


TwAS 


AS Low Width 


35 




30 




2 


TdDS(AS) 


DS T to AS I Delay 


15 




10 




3 


TsCSO(AS) 


£S" to AS T Setup Time 










1 


4 


ThCSCKAS) 


CS to AS t Hold Time 


30 




20 


1 


5 


TsCS1(DS) 


CSi to D6 i Setup Time 


65 




50 


1 


6 


TriCSKDS) 


CSi to D§ T Hold Time 


30 




20 


1 


7 


TslA(AS) 


INTACK to AS t Setup Time 


10 








8 


ThlA(ASl 


INTACK to AS t Hold Time 

II 'I 1 nvl\ I.KJ r\^J 1 1 IUIU 1 II 1 IC 


150 




125 




9 


TsRWR(DS) 


RAW (Read) to DS 1 Setup Time 


65 




50 




10 


ThRW(DS) 


R/WtoDSt Hold Time 


35 




25 




■j •) 


TsRWWrDSl 
t on v v vv yi_>o y 


R/W fWritfO tn 1 ^ptun Timp 


o 




o 




12 


TdAStDSl 


■ T tn D^> i Dplav 


30 




20 




13 


TwDSI 


1 nw Width 


150 




125 




14 


TrC 


Valiri Arr*p<5c; Rprovprv Timp 

vaiiu r\^^cc>o i icvwci y i hi rc 


4TcPC 




4TcPC 


2 


15 


TsA(AS) 


Address to AS T Setup Time 


10 




10 


1 


16 


ThA(AS) 


Address to AS" t Hold Time 


25 




20 


1 


17 


TsDW(DS) 


Write Data to DS 1 Setup Time 


15 




10 




18 


ThDW(DS) 


Write Data to DS T Hold Time 


20 




15 




19 


TdDS(DA) 


DS 1 to Data Active Delay 












20 


TdDSr(DR) 


DS t to Read Data Not Valid Delay 












21 


TdDSf(DR) 


DS 1 to Read Data Valid Delay 




140 


120 




22 


TdAS(DR) 


AS T to Read Data Valid Delay 




250 


190 




NOTES 



1- Parameter does not apply to Interrupt Acknowledge transactions 
2. Parameter applies only between transactions involving the SCC 

tUmts in nanoseconds (ns). 



246 



Z80C30 AC CHARACTERISTICS (Continued) 



Preliminary 









8 MHz 


10 MHz 




Number 


Symbol 


Parameter 


Min Max 


Min 


Max 


Notes t 


23 


TdDS(DRz) 


DS t to Read Data Float Delay 


40 




35 


3 


24 


TdA(DR) 


Address Required Valid to Read Data 














Valid Delay 


260 




210 




25 


TdDS(W) 


DS i to-Wait Valid Delay 


170 




160 


4 


26 


TdDSf(REQ) 


DS i to W/REQ Not Valid Delay 


170 




160 




27 


TdDSr(REQ) 


DS I to DTR/REQ Not Valid Delay 


4TcPC 




4TcPC 




28 


TdAS(INT) 


AS T to iNT Valid Delay 


500 




500 


4 


29 


TdAS(DSA) 


AS t to DS I (Acknowledge) Delay 


250 


225 




5 


30 


TwDSA 


DS (Acknowledge) Low Width 


150 


125 






31 


TdDSA(DR) 


DS i (Acknowledge) to Read Data 














Valid Delay 


140 




120 




32 


TslEI(DSA) 


IEI to DS I (Acknowledge) Setup Time 


80 


80 






33 


ThlEI(DSA) 


IEI to DS T (Acknowledge) Hold Time 












34 


TdlEI(IEO) 


IEI to IEO Delay 


90 




90 




35 


TdAS(IEO) 


AS t to IEO Delay 


200 




175 


6 


36 


TdDSA(INT) 


DS i (Acknowledge) to INT Inactive 














Delay 


450 




450 


4 


37 


TdDS(ASQ) 


DS T to AS I Delay tor No Reset 


15 


15 






38 


TdASQ(DS) 


AS T to DS I Delay for No Reset 


20 


15 






39 


TwRES 


AS and DS Coincident Low for Reset 


150 


100 




7 


40 


TwPCI 


PCLK Low Width 


50 1000 


40 


1000 




41 


TwPCh 


PCLK High Width 


so 1000 


40 


1000 




42 


TcPC 


PCLK Cycle Time 


125 2000 


100 


2000 




43 


TrPC 


PCLK Rise Time 


10 




10 




44 


TfPC 


PCLK Fall Time 


10 




10 





NOTES: 

3. Float delay is delmed as the time required for a ± 0.5V change in the output with a maximum dc load and a minimum ac load 

4. Open-drain output, measured with open-drain test load. 

5. Parameter is system dependent. For any Z-SCC in the daisy chain, TdAS(DSA) must be greater than the sum of TdAS(IEO) for the highest priority 
device in the daisy chain, TslEI(DSA) for the Z-SCC, and TdlElf(IEO) for each device separating them in the daisy chain. 

6. Parameter applies only to a Z-SCC pulling INT Low at the beginning of the Interrupt Acknowledge transaction. 

7. Internal circuitry allows for the reset provided by the Z8 to be recognized as a reset by the Z-SCC 
All timing references assume 2.0V lor a logic "1" and 0.8V for a logic "0". 

til nits in nanoseconds (ns) 



247 




248 



Z80C30/Z85C30 GENERAL TIMING AC CHARACTERISTICS 









8 


MHz 10 


MHz 




NumhAr 

nun imi 


Symbol 


Parameter 


Min 


Max Min 


Max 


Notes t 


1 


TdPC(REQ) 


PCLK 1 to W/REQ Valid Delay 




250 


250 




2 


TdPC(W) 


PCLK i to Wait Inactive Delay 




350 


350 




3 


TsRXC(PC) 


RxC T to PCLK T Setup Time 














(PCLK 4 case only) 


60 


TwPCL 40 


TwPCL 


1.4 


4 


TsRXD(RXCr) 


RxD to RxC T Setup Time (X1 Mode) 










1 


5 


ThRXD(RXCr) RxD to RxC T Hold Time (X1 Mode) 


150 


150 




1 


6 


TsRXD(RXCf) 


RxD to RxC I Setup Time (X1 Mode) 





n 
U 




1 ,5 


7 


ThRXD(RXCf) 


RxD to RxC I Hold Time (X1 Mode) 


150 


150 




1,5 


8 


TsSY(RXC) 


SYNC to RxC T Setup Time 


-200 


-200 




1 


9 


ThSY(RXC) 


SYNC to RxC t Hold Time 


5TcPC 


5TcPC 




1 


10 


TsTXC(PC) 


TxC I to PCLK T Setup Time 










2.4 


11 


TdTXCffTXD) 


TxC i to TxD Delay (XI Mode) 




200 


150 


2 


12 


TdTxCr(TXD) 


TxC T to TxD Delay (X1 Mode) 




200 


150 


2,5 


13 


TdTXD(TRX) 


TxD to TRxC Delay (Send Clock 














Echo) 






inn 
zUU 




14 


TwRTXh 


RTxC High Width 


■t 

iDU 






b 


1 5 


TwRTXI 


RTxC Low Width 


150 


150 




6 


16 


TcRTX 


RTxC Cycle Time (RxD, TxD) 


500 


400 




6,7 


17 


TcRTXX 


Crystal Oscillator Period 


125 


1000 100 


1000 


3 


18 


TwTRXh 


TRxC High Width 


150 


150 




6 


19 


TwTRXI 


TRxC Low Width 


150 


150 




6 


20 


TcTRX 


TRxC Cycle Time 


500 


400 




6,7 


21 


TwEXT 


Deo or CTS Pulse Width 


200 


200 






22 


TwSY 


SYNC Pulse Width 


200 


200 







NOTES 

1 RxC is RTxC or TRxC , whichever is supplying the receive clock 

2. TxC i s TRx C or RTxC. whichever is supplying the transmit clock 

3. Both RTxC and SYNC have 30 pf capacitors to ground connected to them, 

4. Parameter applies only if the data rate is one-lourth the PCLK rate In all other cases, no phase relationship between RxC and PCLK or TxC and 
PCLK is required. 

5 Parameter applies only to FM encoding/decoding. 

6 Parameter applies only tor transmitter and receiver; DPLL and baud rate generator timing requirements are identical to case PCLK requirements 
7. The maximum receive or transmit data is V* PCLK, 

tUnits in nanoseconds (ns). 



249 




250 



Z80C30/Z85C30 SYSTEM TIMING AC CHARACTERISTICS 









8 MHz 


10 MHz 




Number Symbol 


Parameter 


Min 


Max 


Min 


Max 


Notes t 


1 


I unAL/(ntU) 


RxT t tn W/RFO Valid Dplav 


8 


12 


8 


12 


2 


2 




RxC" 1 to Wait Inactive Delay 


8 


14 


8 


14 


1,2 


3 


TdRXC(SY) 


RxC T to SYNC Valid Delay 


4 


7 


4 


7 


2 


4a. 


TdRXC(INT), Z8530 


RxC~ T to INT Valid Delay 


10 


16 


10 


16 


1,2 


4b. 


TdRXC(INT). Z8030 




Q 
O 


1 n 
\c 


8 


12 


1,2 








+ 2 


+ 3 


+ 2 


+ 3 


4 


5 


tdixu(Rtu) 


TxC I to W/RES Valid Delay 


5 


8 


5 


8 


3 


6 


TdTXC(W) 


TxC 1 to Wait Inactive Delay 


5 


11 


5 


11 


1.3 


7 


TdTXC(DRQ) 


TxC I DTR/REQ Valid Delay 


A 


1 


A 

4 


7 
1 


3 


8a. 


TdTXC(INT). Z8530 


TxC I to InT Valid Delay 


6 


10 


6 


10 


1.3 


8b. 


TdTXC(INT), Z8030 




4 


6 


4 


6 


1.3 








+ 2 


+ 3 


+ 2 


+ 3 


4 


9a. 


TdSY(INT), Z8530 


SYNC Transition to INT Valid Delay 


2 


6 


2 


6 


1 


9b. 


TdSY(INT), Z8030 




2 


3 


2 


3 


1,4 


10a. 


TdEXT(INT), Z8530 


DCD or CTS Transition to INT Valid Delay 


2 


6 


2 


6 


1 


10b. 


TdEXT(INT), Z8030 




2 


3 


2 


3 


1,4 



NOTES 

1 Open- drain o ut put, m easured with open-drain test load 

2 RxC is RTxC or TRxC , whichever is supplying the receive clock 

3 TxC is TRxC or RTxC, whichever is supplying the transmit clock 
4. Units equal to AS. 



TUnits equal to TcPC 



251 



System 
Timing 



RTiC, TR«C 

RECEIVE 



wmco 

BEQUEST 



SYNC 

OUTPUT 



RTiC, THkC 

TRANSMIT 



WfREO 

REQUEST 



WfREO 

WAIT 



A /f \ / V 



-CD- 



-CD- 



-CD- 



J \—/ ^—T 



-©- 



C D- 



> 



I 



SYHC 

INPUT 



X 



-<D- 



-®- 



252 



Zilog 



Product Specification 



Z8030 Z-BUS SCC/ 
Z8530 SCC Serial 
Communications Controller 



October 1987 



Features ■ Two independent, to 2M bit/second, full- 

duplex channels, each with a separate crystal 
oscillator, baud rate generator, and Digital 
Phase-Locked Loop for clock recovery. 

■ Multi-protocol operation under program 
control; programmable for NRZ, NRZI, or 
FM data encoding. 

■ Asynchronous mode with five to eight bits 
and one, one and one-half, or two stop bits 
per character; programmable clock factor; 
break detection and generation; parity, 
overrun, and framing error detection. 

■ Synchronous mode with internal or external 
character synchronization on one or two 



synchronous characters and CRC genera- 
tion and checking with CRC-16 or 
CRC-CCITT preset to either Is or Os. 

SDLC/HDLC mode with comprehensive 
frame-level control, automatic zero insertion 
and deletion, I-field residue handling, abort 
generation and detection, CRC generation 
and checking, and SDLC Loop mode 
operation. 

Local Loopback and Auto Echo modes. 
Supports Tl digital trunk. 



General The SCC Serial Communications Controller 

Description is a dual-channel, multi-protocol data communi- 
cations peripheral designed for use with conven- 
tional non-multiplexed buses and the Zilog 
Z-BUS.® The SCC functions as a serial-to- parallel, 
parallel-to-serial converter/controller. The SCC 
can be software-configured to satisfy a wide vari- 
ety of serial communications applications. The 



device contains a variety of new, sophisticated 
internal functions including on-chip baud rate 
generators, Digital PhaseLocked Loops, and 
crystal oscillators that dramatically reduce the 
need for external logic. 



BUS | 
TIMING 



EO OTR/REOB 
HTS8 

Z6530 CTSB 
DCDB 



I CHANNEL 
I CLOCKS 



CHANNEL 
CONTROLS 
FOR MODEM, 
DMA, OR 
OTHER 



CHANNEL 
CONTROLS 
FOR MODEM, 
DMA, OR 
OTHER 



> CH-A 



> CH-e 



ttt 

+ SV GND PCLK 

Figure la. Pin Functions, Z8530 



ADDRESS! 
DATA BUS 



BUS ( 
TIMING 
AND RESET I 



INTERRUPT 



cs, 
CSo 



DTRfflEQA 
RTSA 
CTSA 
DC DA 
TxDB 
RxDB 
TRxCB 
RTxCB 
SYNCB 
W/REOB 



DTR/REOB 
RTSB 
CTSB 
DCDB 



t t t 



I CHANNEL 
I CLOCKS 



CHANNEL 
CONTROLS 
FOR MODEM 
DMA, OR 
OTHER 



' I SERIAL 
. | DATA 



' I CHANNEL 
_ I CLOCKS 



CHANNEL 
CONTROLS 
FOR MODEM, 
DMA, OR 
OTHER 



+ 5V GND PCLK 

Figure lb. Pin Functions. Z8030 



253 



General The SCC handles asynchronous formats , 

Description Synchronous byte-oriented protocols such as 
(Continued) IBM Bisync, and Synchronous bit-oriented pro- 
tocols such as HDLC and IBM SDLC. This ver- 
satile device supports virtually any serial data 
transfer application (cassette, diskette, tape 
drives, etc.). 

The device can generate and check CRC 
codes in any Synchronous mode and can be 
programmed to check data integrity in various 



modes. The SCC also has facilities for 
modem controls in both channels. In appli- 
cations where these controls are not needed, 
the modem controls can be used for 
general-purpose I/O. 

The daisy-chain interrupt hierarchy is also 
supported — as is standard for Zilog peripheral 
components. 







40 


3oi 


AD, C 






W 


3 ADo 


°.c 




» 


1°, 


AD 3 Q 


a 




39 


3 ADj 


°*c 


3 


39 


1". 


AD S C 


3 




38 


3 A °4 


Ort 




" 


2* 


AD 7 C 


4 




87 


3 *°6 


INT C 






3 RD 


tNT L7 






36 


3 os 


IEO C 


• 


36 


3 WR 


IEO £ 


i 




35 


1 AS 


iaC 




34 


3 A/B 


ihC 






34 


3 R/w 


INTACK Q 


8 


33 


]r E 


INTACK £ 


s 




33 


3 CSo 


+ 5V Q 


9 


32 


3 D/C 


+ 5V Q 


s 




» 


3 cs. 


W/REQA C 




» 


3 GND 


W/REQA £ 


10 


Z8030 


31 


3 GND 


SYNCA C 






] WfREOB 


SVNCA C 


11 




30 


3 wTreqb 


RTxCA C 


12 


29 


3 SYNCS 


RTxCA C 


13 




29 


3 SYNCB 


RxDA C 


" 


» 


3 RTxCB 


RxDA C 


13 




28 


3 RTxCB 


TRxCA ^ 


14 


27 


3 RxDB 


TRxCA L 


14 




27 


3 RxDB 


TxDA C 


11 




3 TRxCB 


TxDA C 


15 




26 


3 TRxCB 


DTR.'REQA £ 


16 


25 


3 TxDB 


DTRIHEQA ^ 


16 




as 


3 TxDB 


RTSA £ 


17 


24 


3 DTRJREQB 


RTSA £ 


17 




24 


3 DTRfREOB 


CTSA £ 


1B 


23 


3 RTSB 


CTSA C 


18 




23 


3 RTSB 


DC DA C 


19 


22 


3 CTSB 


DCDA C 


19 




22 


3 CTSB 


PCLK C 


20 


21 


3 DCDB 


PCLK C 


20 




21 


3 DCDB 



Figure 2a. DIP Pin Assignments. Z8530 



Figure 2b. DIP Pin Assignments. Z8030 



<>"■ o* <y> o N <y> <p o*- o" < 





/- 


IEO 


7 


IEI 


8 


INTACK 


9 


+ 5V 


10 


W/REQA 


11 


SYNCA 


12 


RTxCA 


13 


RxDA 


u 


TRxCA 


15 


TxDA 


16 


NC 


17 



44 43 42 41 



18 19 20 21 22 23 24 25 26 27 28 



\ 




39 


A/B 


38 


CE 


37 


d/c 


36 


NC 


35 


GND 


34 


W/REQB 


33 


SYNCB 


32 


RTxCB 


31 


RxDB 


30 


TRxCB 


29 


TxDB 


/ 





+ 5V 
W'HEQA 
SYNCA 
RTxCA 
RxDA 
TRxCA 
TxDA 
NC 




18 19 20 21 22 23 24 25 26 27 28 



Figure 2c. Chip Carrier Pin Assignments, Z8530 



Figure 2d. Chip Carrier Pin Assignments, Z8030 



254 



Pin The following section describes the pin 

Description functions common to the Z8530 and the Z8030. 

Figures 1 and 2 detail the respective pin func- 
tions and pin assignments. 

CTSA. CTSB. Clear To Send (inputs, active 
Low). If these pins are programmed as Auto 
Enables, a Low on the inputs enables the 
respective transmitters. If not programmed as 
Auto Enables, they may be used as general- 
purpose inputs. Both inputs are Schmitt-trigger 
buffered to accommodate slow rise-time inputs. 
The SCC detects pulses on these inputs and can 
interrupt the CPU on both logic level 
transitions. 

DCDA. DCDB. Data Carrier Defec/ (inputs/outputs. 

active Low). These pins function as receiver 
enables if they are programmed for Auto 
Enables; otherwise they may be used as 
general-purpose input pins. Both pins are 
Schmitt-trigger buffered to accomodate slow 
rise-time signals. The SCC detects pulses on 
these pins and can interrupt the CPU on both 
logic level transitions. 

DTR/REQA, DTR/REQB. Data Terminal 
Ready/Request (outputs, active Low). These 
outputs follow the state programmed into the 
DTR bit. They can also be used as general- 
purpose outputs or as Request lines for a DMA 
controller. 

IEI. Interrupt Enable In (input, active High). 
IEI is used with IEO to form an interrupt daisy 
chain when there is more than one inter- 
ruptdriven device. A High IEI indicates that no 
other higher priority device has an interrupt 
under service or is requesting an interrupt. 

IEO. Interrupt Enable Our (output, active 
High). IEO is High only if IEI is High and the 
CPU is not servicing an SCC interrupt or the 
SCC is not requesting an interrupt (Interrupt 
Acknowledge cycle only) . IEO is connected to 
the next lower priority device's IEI input and 
thus inhibits interrupts from lower priority 
devices. 

INT. Interrupt Request (output, open-drain, 
active Low) . This signal is activated when the 
SCC requests an interrupt. 

INTACK. Interrupt Acknowledge (input, active 
Low). This signal indicates an active Interrupt 
Acknowledge cycle. During this cycle, t he 
SCC interrupt daisy chain settles. When RD 
or DS becomes active, the SCC places an inter- 
rupt vect or on the data bus (if IEI is High). 
INTACK is latched by the rising edge 
of PCLK. 

PCLK. Clock (input). This is the master SCC 
clock used to synchronize internal signals. 
PCLK is a TTL level signal. PCLK is not 
required to have any phase relationship with 
the master system clock. 



RxDA, RxDB. Receive Data (inputs, active 
High). These input signals receive serial data at 
standard TTL levels. 

RTxCA RTxCB. Receive/Transmit Clocks 
(inputs, active Low). These pins can be pro- 
grammed in several di fferent modes of opera- 
tion. In each channel, RTxC may supply the 
receive clock, the transmit clock, the clock for 
the baud rate generator, or the clock for the 
Digital Phase-Locked Loop. These pins can 
also be programmed for use with the respec- 
tive SYNC pins as a crystal oscillator. The 
receive clock may be 1, 16, 32, or 64 times 
the data rate in Asynchronous modes. 

RTSA, RTSB. Request To Send (outputs, 

active Low). When the Request To Send (RTS) 

bit in Write Register 5 (Figure 1 1) is set, the RTS 
signal goes Low. When the RTS bit is reset in 
the Asynchronous mode and Auto Enable is on, 
the signal goes High after the transmitter is 
empty. In Synchronous mode or in Asynchron- 
ous mode with Auto Enable off, the RTS pin 
strictly follows the state of the RTS bit. Both pins 
can be used as general-purpose outputs. 

SYNCA, SYNCB. Synchronization (inputs or 
outputs, active Low). These pins can act either 
as inputs, outputs, or part of the crystal 
oscillator circuit. In the Asynchronous Receive 
mode (crystal oscillator option not s elect ed), 
these pins are inputs similar to CTS and DCD. 
In this mode, transitions on these lines affect the 
state of the Synchronous/Hunt status bits in 
Read Register (Figure 10) but have no other 
function. 

In External Synchronization mode with the 
crystal oscillator not select ed, the se lines also 
act as inputs. In this mode, SYNC must be 
driven Low two receive clock cycles after the 
last bit in the synchronous character is 
received. Character assembly begins on the 
rising edge of the receive c lock im mediately 
preceding the activation of SYNC. 

In the Internal Synchronization mode 
(Monosync and Bisync) with the crystal 
oscillator not selected, these pins act as out- 
puts and are active only during the part of the 
receive clock cycle in which synchronous 
characters are recognized. The synchronous 
condition is not latched, so these outputs are 
active each time a synchronization pattern is 
recognized (regardless of character bound- 
aries). In SDLC mode, these pins act as 
outputs and are valid on receipt of a flag. 

TxDA, TxDB. Transmit Data (outputs, active 
High). These output signals transmit serial data 
at standard TTL levels. 



255 



TRxCA, TRxCB. Transmit/Receive Clocks 
(inputs or outputs, active Low). These pins can 
be programmed in several different modes of 
operation. TRxC may supply the receive clock 
or the transmit clock in the input mode or sup- 
ply the output of the Digital Phase-Locked 
Loop, the crystal oscillator, the baud rate gener- 
ator, or the transmit clock in the output mode. 

W/REQA, W/REQB. Wait/Request (outputs, 
open-drain when programmed for a Wait func- 
tion, driven High or Low when programmed for 
a Request function). These dual-purpose outputs 
may be programmed as Request lines for a DMA 
controller or as Wait lines to synchronize the 
CPU to the SCC data rate. The reset state is 
Wait. 

Z8530 

A/B. Channel A/Channel B Select (input). 
This signal selects the channel in which the 
read or write operation occurs. 

CE. Chip Enable (input, active Low). 

This signal selects the SCC for a read or write 

operation. 

D0-D7 Data Bus (bidirectional, 3-state). These 
lines carry data and commands to and from 
the SCC. 

D/C. Data/Control Select (input). This signal 
defines the type of information transferred to or 
from the SCC. A High means data is transfer- 
red; a Low indicates a command. 

RD. Bead (input, active Low). This signal indi- 
cates a read operation and when the SCC is 
selected, enables the SCC's bus drivers. During 



the Interrupt Acknowledge cycle, this signal 
gates the interrupt vector onto the bus 
if the SCC is the highest priority device 
requesting an interrupt. 

WR. Write (input, active Low). When the SCC 

is selected, this signal indicates a write 

operation. The coincidence of RD and WR is 
interpreted as a reset. 

Z8030 

AD0-AD7. Address/Data Bus (bidirectional, 
active High, 3-state). These multiplexed lines 
carry register addresses to the SCC as well as 
data or control information. 

AS. Address Strobe (input, active Low). 
Addresses on AD0-AD7 are latched by the rising 
edge of this signal. 

CS(j. Chip Select (input, active Low). This 
signal is latched concurrently with the 
addresses on AD0-AD7 and must be active for 
the intended bus transaction to occur. 

CSi. Chip Select 1 (input, active High). This 
second select signal must also be active before 
the intended bus transaction can occur. CSi 
must remain active throughout the transaction. 

DS. Data Strobe (input, active Low). This 
signal provides timing for the transfer of data 
into and out of the SCC. If AS and DS coincide, 
this is interpreted as a reset. 

R/W. Read/Write (input). This signal specifies 
whether the operation to be performed is a read 
or a write. 



Functional The functional capabilities of the SCC 

Description can be described from two different points 
of view: as a data communications device, 
it transmits and receives data in a wide 
variety of data communications protocols; as 
a microprocessor peripheral, the SCC offers 
valuable features such as vectored interrupts, 
polling, and simple handshake capability. 



Data Communications Capabilities. The 

SCC provides two independent full-duplex 
channels programmable for use in any com- 
mon Asynchronous or Synchronous data- 
communication protocol. Figure 3 and the 
following description briefly detail these 
protocols. 



MARKING LINE 



START I STOP 

J h 



ASYNCHRONOUS 



SYNC DATA 



SYNC SYNC DATA 



ATA I CRC ' 



MONOSVNC 



DATA CRC, 



SIGNAL 



DATA CRC, 



I ADDRESS I 



EXTERNAL SYNC 



INFORMATION 



SDLCfHDLCJX.25 



] 



I CRC, I CRC; I FLAG | 



Figure 3. Some SCC Protocols 



256 



Functional Asynchronous Modes. Transmission and 
Description reception can be accomplished independently 
(Continued) on each channel with five to eight bits per 
character, plus optional even or odd parity. 
The transmitters can supply one, one-and-a- 
half, or two stop bits per character and can 
provide a break output at any time. The 
receiver break-detection logic interrupts the 
CPU both at the start and at the end of a 
received break. Reception is protected from 
spikes by a transient spike-rejection 
mechanism that checks the signal one-half a 
bit time after a Low level is detected on the 
receive data input (RxDA or RxDB in 
Figure 1 ) . If the Low does not persist (as in the 
case of a transient), the character assembly 
process does not start. 

Framing errors and overrun errors are 
detected and buffered together with the partial 
character on which they occur. Vectored inter- 
rupts allow fast servicing or error conditions 
using dedicated routines. Furthermore, a 
built-in checking process avoids the interpreta- 
tion of a framing error as a new start bit: a 
framing error results in the addition of one-half 
a bit time to the point at which the search for 
the next start bit begins. 

The SCC does not reguire symmetric 
transmit and receive clock signals — a feature 
allowing use of the wide variety of clock 
sources. The transmitter and receiver can 
handle data at a rate of 1, 1/16, 1/32, or 1/64 
of the clock rate supplied to the receive and 
tra nsmit c lock inputs. In Asynchronous modes, 
the SYNC pin may be programmed as an input 
used for functions such as monitoring a ring 
indicator. 

Synchronous Modes. The SCC supports both 
byte-oriented and bit-oriented synchronous 
communication. Synchronous byte-oriented 
protocols can be handled in several modes, 
allowing character synchronization with a 6-bit 
or 8-bit synchronous character (Monosync), 
any 12-bit synchronization pattern (Bisync), or 
with an external synchronous signal. Leading 
sync characters can be removed without inter- 
rupting the CPU. 

Five- or 7-bit synchronous characters are 
detected with 8- or 16-bit patterns in the SCC 
by overlapping the larger pattern across multi- 
ple incoming synchronous characters as shown 
in Figure 4. 

CRC checking for Synchronous byte- 
oriented modes is delayed by one character 
time so that the CPU may disable CRC check- 
ing on specific characters. This permits the 
implementation of protocols such as 
IBM Bisync. 



Both CRC-16 (X16 + X15 + X2 + 1) and 
CCITT (X16 + X'2 + XS + 1) error checking 
polynomials are supported. Either polynomial 
may be selected in all Synchronous modes. 
Users may preset the CRC generator and 
checker to all Is or all Os. The SCC also pro- 
vides a feature that automatically transmits 
CRC data when no other data is -available for 
transmission. This allows for high speed 
transmissions under DMA control, with no 
need for CPU intervention at the end of a 
message. When there is no data or CRC to 
send in Synchronous modes, the transmitter 
inserts 6-, 8-, or 16-bit synchronous 
characters, regardless of the programmed 
character length. 

The SCC supports Synchronous bit-oriented 
protocols, such as SDLC and HDLC, by per- 
forming automatic flag sending, zero insertion, 
and CRC generation. A special command can 
be used to abort a frame in transmission. At 
the end of a message, the SCC automatically 
transmits the CRC and trailing flag when the 
transmitter underruns. The transmitter may 
also be programmed to send an idle line con- 
sisting of continuous flag characters or a 
steady marking condition. 

If a transmit underrun occurs in the middle 
of a message, an external/status interrupt 
warns the CPU of this status change so that an 
abort may be issued. The SCC may also be 
programmed to send an abort itself in case of 
an underrun, relieving the CPU of this task. 
One to eight bits per character can be sent, 
allowing reception of a message with no prior 
information about the character structure in 
the information field of a frame. 

The receiver automatically acquires syn- 
chronization on the leading flag of a frame in 
SDLC or HDLC a nd pro vides a synchroniza- 
tion signal on the SYNC pin (an interrupt can 
also be programmed). The receiver can be 
programmed to search for frames addressed by 
a single byte (or four bits within a byte) of a 
user-selected address or to a global broadcast 
address. In this mode, frames not matching 
either the user-selected or broadcast address 
are ignored. The number of address bytes can 
be extended under software control. For 
receiving data, an interrupt on the first 
received character, or an interrupt on every 
character, or on special condition only (end- 
of-frame) can be selected. The receiver 
automatically deletes all Os inserted by the 
transmitter during character assembly. CRC is 
also calculated and is automatically checked to 
validate frame transmission. At the end of 



T3 



Figure i. Detecting 5- or 7-Bit Synchronous Characters 



257 



Functional transmission, the status of a received frame is 
Description available in the status registers. In SDLC 
(Continued) mode, the SCC must be programmed to use 
the SDLC CRC polynomial, but the generator 
and checker may be preset to all Is or all Os. 
The CRC is inverted before transmission and 
the receiver checks against the bit pattern 
0001110100001111. 

NRZ, NRZI or FM coding may be used in any 
lx mode. The parity options available in Asyn- 
chronous modes are available in Synchronous 
modes. 

The SCC can be conveniently used under 
DMA control to provide high speed reception 
or transmission. In reception, for example, the 
SCC can interrupt the CPU when the first 
character of a message is received. The CPU 
then enables the DMA to transfer the message 
to memory. The SCC then issues an end-of- 
frame interrupt and the CPU can check the 
status of the received message. Thus, the CPU 
is freed for other service while the message is 
being received. The CPU may also enable the 
DMA first and have the SCC interrupt only on 
end-of-frame. This procedure allows all data to 
be transferred via the DMA. 

SDLC Loop Mode. The SCC supports SDLC 
Loop mode in addition to normal SDLC. In an 
SDLC Loop, there is a primary controller 
station that manages the message traffic flow 
on the loop and any number of secondary 
stations. In SDLC Loop mode, the SCC per- 
forms the functions of a secondary station 
while an SCC operating in regular SDLC 
mode can act as a controller (Figure 5). 

A secondary station in an SDLC Loop is 
always listening to the messages being sent 
around the loop, and in fact must pass these 
messages to the rest of the loop by retrans- 
mitting them with a one-bit-time delay. The 
secondary station can place its own message 
on the loop only at specific times. The con- 
troller signals that secondary stations may 
transmit messages by sending a special 
character, called an EOP (End Of Poll), 
around the loop. The EOP character is the bit 
pattern 11111110. Because of zero insertion 
during messages, this bit pattern is unigue and 
easily recognized. 




Figure 5. An SDLC Loop 



When a secondary station has a message to 
transmit and recognizes an EOP on the line, it 
changes the last binary 1 of the EOP to a 
before transmission. This has the effect of turn- 
ing the EOP into a flag seguence. The secon- 
dary station now places its message on the loop 
and terminates the message with an EOP. Any 
secondary stations further down the loop with 
messages to transmit can then append their 
messages to the message of the first secondary 
station by the same process. Any secondary 
stations without messages to send merely echo 
the incoming messages and are prohibited 
from placing messages on the loop (except 
upon recognizing an EOP). 

SDLC Loop mode is a programmable option 
in the SCC. NRZ, NRZI, and FM coding may 
all be used in SDLC Loop mode. 

Baud Rate Generator. Each channel in the 
SCC contains a programmable baud rate 
generator. Each generator consists of two 8-bit 
time constant registers that form a 16-bit time 
constant, a 16-bit down counter, and a flip-flop 
on the output producing a square wave. On 
startup, the flip-flop on the output is set in a 
High state, the value in the time constant 
register is loaded into the counter, and the 
counter starts counting down. The output of 
the baud rate generator toggles upon reaching 
0, the value in the time constant register is 
loaded into the counter, and the process is 
repeated. The time constant may be changed 
at any time, but the new value does not take 
effect until the next load of the counter. 

The output of the baud rate generator may 
be used as either the transmit clock, the 
receive clock, or both. It can also drive the 
Digital Phase- Locked Loop (see next section). 

If the receive clock or transmit clock is not 
programmed to come from the TRxC pin, the 
output of the baud rate generator may be 
echoed out via the TRxC pin. 

The following formula relates the time con- 
stant to the baud rate where PCLK or RTxC is 
the baud rate generator input frequency in Hz. 
The clock mode is 1, 16, 32, or 64 as selected in 
Write Register 4, bits D6 and D7. Synchronous 
operation modes should select 1 and 
Asynchronous should select 16, 32, or 64. 

_. _ PCLK or RTxC Frequency , 

lime constant = „ — „ , , — r-r-, — — i 
2 (Baud Rate) (Clock Mode) 

Digital Phase-Locked Loop. The SCC contains 
a Digital Phase-Locked-Loop (DPLL) to recover 
clock information from a data stream with NRZI 
or FM encoding. The DPLL is driven by a clock 
that is nominally 32 (NRZI) or 16 (FM) times the 
data rate. The DPLL uses this clock, along with 
the data stream, to construct a clock for the 
data. This clock may then be used as the SCC 
receive clock, the transmit clock, or both. 

For NRZI encoding, the DPLL counts the 32x 
clock to create nominal bit times. As the 32x 
clock is counted, the DPLL is searching the 



258 



next counting cyciej, producing a terminal 
count closer to the center of the bit cell. 

For FM encoding, the DPLL still counts from 
to 31, but with a cycle corresponding to two 
bit times. When the DPLL is locked, the clock 
edges in the data stream should occur between 
counts 15 and 16 and between counts 31 and 
0. The DPLL looks for edges only during a 
time centered on the 15 to 16 counting 
transition. 

The 32x clock for the DPLL can be pr o- 
grammed to come from either the RTxC input 
or the output of the baud rate generator. The 
DPLL output may be program med to be 
echoed out of the SCC via the TRxC pin (if 
this pin is not being used as an input). 

Data Encoding. The SCC may be pro- 
grammed to encode and decode the serial data 
in four different ways (Figure 6). In NRZ 
encoding, a 1 is represented by a High level 
and a is represented by a Low level. In NRZI 
encoding, a 1 is represented by no change in 
level and a is represented by a change in 
level. In FM1 (more properly, bi-phase mark), 
a transition occurs at the beginning of every 
bit cell. A 1 is represented by an additional 
transition at the center of the bit cell and a is 
represented by no additional transition at the 
center of the bit cell. In FMO (bi-phase space), 
a transition occurs at the beginning of every 
bit cell. A is represented by an additional 
transition at the center of the bit cell, and a 1 
is represented by no additional transition at 
the center of the bit cell. In addition to these 
four methods, the SCC can be used to decode 
Manchester (bi-phase level) data by using the 
DPLL in the FM mode and programming the 
receiver for NRZ data. Manchester encoding 
always produces a transition at the center of 
the bit cell. If the transition is to 1, the bit is 
a 0. If the transition is 1 to 0, the bit is a 1 . 



1 U11UUQ 



chronous and SDLC modes as well. In Auto 
Echo mode, TxD is RxD. Auto Echo mode can 
be used with NRZI or FM encoding with no 
additional delay, because the data stream is 
not decoded bef ore r etransmission. In Auto 
Echo mode, the CTS input is ignored as a 
transmitter enable (although transitions on this 
input can still cause interrupts if programmed 
to do so). In this mode, the transmitter is 
actually bypassed and the programmer is 
resp onsible for disabl ing transmitter interrupts 
and WAIT/REQUEST on transmit. 

The SCC is also capable of local loopback. 
In this mode TxD is RxD, just as in Auto Echo 
mode. However, in Local Loopback mode, the 
internal transmit data is tied to the internal 
receive data and RxD is i gnore d (e xcept to be 
echoed out via TxD). The CTS and DCD 
inputs are also ignored as transmit and receive 
enables. However, transitions on these inputs 
can still cause interrupts. Local Loopback 
works in Asynchronous, Synchronous and 
SDLC modes with NRZ, NRZI or FM coding of 
the data stream. 

I/O Interface Capabilities. The SCC offers 
the choice of Polling, Interrupt (vectored or 
nonvectored) , and Block Transfer modes to 
transfer data, status, and control information to 
and from the CPU. The Block Transfer mode 
can be implemented under CPU or DMA 
control. 

Polling. All interrupts are disabled. Three 
status registers in the SCC are automatically 
updated whenever any function is performed. 
For example, end-of -frame in SDLC mode 
sets a bit in one of these status registers. The 
idea behind polling is for the CPU to 
periodically read a status register until the 
register contents indicate the need for data to 
be transferred. Only one register needs to be 



DATA 1 



J V 



V 



f 




Figure 6. Data Encoding Method* 



2016-007 



259 



Functional read; depending on its contents, the CPU 
Description either writes data, reads data, or continues. 
(Continued) Two bits in the register indicate the need for 
data transfer. An alternative is a poll of the 
Interrupt Pending register to determine the 
source of an interrupt. The status for both 
channels resides in one register. 

Interrupts. When an SCC res ponds to a n 
Interrupt Acknowledge signal (INTACK) from 
the CPU, an interrupt vector may be placed on 
the data bus. This vector is written in WR2 and 
may be read in RR2A or RR2B (Figures 10 
and 11). 

To speed interrupt response time, the SCC 
can modify three bits in this vector to indicate 
status. If the vector is read in Channel A, 
status is never included; if it is read in 
Channel B, status is always included. 

Each of the six sources of interrupts in the 
SCC (Transmit, Receive, and External/Status 
interrupts in both channels) has three bits 
associated with the interrupt source: Interrupt 
Pending (IP), Interrupt Under Service (IUS), 
and Interrupt Enable (IE). Operation of the IE 
bit is straightforward. If the IE bit is set for a 
given interrupt source, then that source can 
reguest interrupts. The exception is when the 
MIE (Master Interrupt Enable) bit in WR9 is 
reset and no interrupts may be reguested. The 
IE bits are write only. 

The other two bits are related to the inter- 
rupt priority chain (Figure 7). As a 
microprocessor peripheral, the SCC may 
reguest an interrupt only when no higher 
priority device is requesting one, e.g., when 
IEI is High. If the device i n qu estion requests 
an interrupt, i t pulls do wn INT. The CPU then 
responds with INTACK, and the interrupting 
device places the vector on the data bus. 

In the SCC, the IP bit signals a need for 
interrupt servicing. When an IP bit is 1 and 
the IEI input is High, the INT output is pulled 
Low, requesting an interrupt. In the SCC, if 
the IE bit is not set by enabling interrupts, 
then the IP for that source can never be set. 
The IP bits are readable in RR3A. 

The IUS bits signal that an interrupt request 
is being serviced. If an IUS is set, all interrupt 
sources of lower priority in the SCC and 



external to the SCC are prevented from 
requesting interrupts. The internal interrupt 
sources are inhibited by the state of the inter- 
nal daisy chain, while lower priority devices 
are inhibited by the IEO output of the SCC 
being pulled Low and propagated to subse- 
quent peripherals. An IUS bit is set during an 
Interrupt Acknowledge cycle if there are no 
higher priority devices reguesting interrupts. 

There are three types of interrupts: 
Transmit, Receive, and External/Status. Each 
interrupt type is enabled under program con- 
trol with Channel A having higher priority 
than Channel B, and with Receiver, Transmit, 
and External/Status interrupts prioritized in 
that order within each channel. When the 
Transmit interrupt is enabled, the CPU is 
interrupted when the transmit buffer becomes 
empty. (This implies that the transmitter must 
have had a data character written into it so 
that it can become empty.) When enabled, the 
receiver can interrupt the CPU in one of three 
ways: 

■ Interrupt on First Receive Character or 
Special Receive Condition. 

■ Interrupt on All Receive Characters or 
Special Receive Condition. 

■ Interrupt on Special Receive Condition 
Only. 

Interrupt on First Character or Special Con- 
dition and Interrupt on Special Condition Only 
are typically used with the Block Transfer 
mode. A Special Receive Condition is one of 
the following: receiver overrun, framing error 
in Asynchronous mode, end-of-frame in SDLC 
mode and, optionally, a parity error. The 
Special Receive Condition interrupt is different 
from an ordinary receive character available 
interrupt only in the status placed in the vector 
during the Interrupt Acknowledge cycle. In 
Interrupt on First Receive Character, an inter- 
rupt can occur from Special Receive Condi- 
tions any time after the first receive character 
interrupt. 

The main function of the External/Status 
inte rrup t is to m onit or the signal transitions of 
the CTS, DCD, and SYNC pins; however, an 



IEI O0-D7 INT INTACK IEO 



rrrm 



PERIPHERAL 

IEI D -D? INT INTACK IEO 



PERIPHERAL 

IEI Oo-Dt INT INTACK 



J 1> I t i_T 



Figure 7. Interrupt Schedule 



260 



Functional External/Status interrupt is also caused by a 
Description Transmit Underrun condition, or a zero count 
(Continued) in the baud rate generator, or by the detection 
of a Break (Asynchronous mode), Abort (SDLC 
mode) or EOP (SDLC Loop mode) sequence in 
the data stream. The interrupt caused by the 
Abort or EOP has a special feature allowing 
the SCC to interrupt when the Abort or EOP 
sequence is detected or terminated. This 
feature facilitates the proper termination of the 
current message, correct initialization of the 
next message, and the accurate timing of the 
Abort condition in external logic in SDLC 
mode. In SDLC Loop mode, this feature allows 
secondary stations to recognize the wishes of 
the primary station to regain control of the 
loop during a poll sequence. 



CPU/DMA Block Transfer. The SCC provides 
a Block Transfer mode to accommodate CPU 
block transfer functions and DMA contro llers. 
The Block Transfer mode uses the WAIT/ 
REQUEST output in conjunctio n with the 
Wait/Requ est bits in WR1. The WAIT/ 
REQUEST output can b e defined under soft- 
ware control as a WAI T line in th e CPU Block 
Transfer mode or as a REQUEST line in the 

DMA Block Transfer mode. 

To a DMA controller, the SCC REQUEST 
output indicates that the SCC is ready to 
tra nsfer d ata to or from memory. To the CPU, 
the WAIT line indicates that the SCC is not 
ready to transfer data, thereby req uestin g that 
the CPU e xtend the I/O cycle. The DTR/ 
REQUEST line allows full-duplex operation 
under DMA control. 



Architecture The SCC internal structure includes two full- 
duplex channels, two baud rate generators, 
internal control and interrupt logic, and a bus 
interface to a nonmultiplexed bus. Associated 
with each channel are a number of read and 
write registers for mode control and status 
information, as well as logic necessary to inter- 
face to modems or other external devices 
(Figure 8). 

The logic for both channels provides 
formats, synchronization, and validation for 
data transferred to and from the channel inter- 
face. The modem control inputs are monitored 



by the control logic under program control. 
All of the modem control signals are general- 
purpose in nature and can optionally be used 
for functions other than modem control. 

The register set for each channel includes 
ten control (write) registers, two sync- 
character (write) registers, and four status 
(read) registers. In addition, each baud rate 
generator has two (read/write) registers for 
holding the time constant that determines the 
baud rate. Finally, associated with the inter- 
rupt logic is a write register for the interrupt 
vector accessible through either channel, a 



INTERNAL 
CONTROL 
LOGIC 



'Of 



St ft 



INTERNAL BUS 



INTERRUPT 
CONTROL 
LINES 



INTERRUPT 
CONTROL 
LOGIC 



ttt 

+ 5 V GNO PCLK 



^ CHANNEL A * m 



DISCRETE 
CONTROL 
STATUS 



DISCRETE 
CONTROL 
& STATUS 



} SERIAL DATA 
{CHANNEL CLOCKS 



■ SYNC 

- WAIT/REQUEST 



^> CHANNEL 8 * * 



SERIAL DATA 
CHANNEL CLOCKS 



Figure 8. Block Diagram of SCC Architecture 



261 



oi? 

§ i 



CPU I/O 

IL, 

I/O DATA BUFFER 



INTERNAL DATA BUS 



16-BIT DOWN | COUNTER 



RECEIVE 
ERROR 



HUNT MODE (BISYNC) 



31 

RECEIVE 
ERROR 
LOGIC 



RECEIVE 
- SHIFT REGISTER - 
(6 BITS) 



TT TTT 



CRC DELAY 
REGISTER 
(8 BITS) 



TRANSMIT DATA 



20BIT TRANSMIT | SHIFT REGISTER | 



CRC GENERATOR - 



> TO OTHER CHANNEL 



INTERNAL TxD 



2 



NRZI ENCODE 



NRZI DECODE 



CRC CHECKER 



- DPLL OUTPUT 



BR GENERATOR OUTPUT - 
DPLL OUTPUT - 



SYNC 
(OSCILLATOR) 



• RECEIVE CLOCK 

- TRANSMIT CLOCK 

- DPLL CLOCK 

- BR GENERATOR CLOCK 



Figure 9. Data Path 



Architecture write only Master Interrupt Control register 
(Continued) and three read registers: one containing the 

vector with status infomation (Channel B only), 
one containing the vector without status 
(Channel A only), and one containing the 
Interrupt Pending bits (Channel A only). 

The registers for each channel are 
designated as follows: 

WR0-WR15 — Write Registers through 15. 

RR0-RR3, RR10, RR12, RR13, RR15 — Read 
Registers through 3, 10, 12, 13, 15. 

Table 1 lists the functions assigned to each 
read or write register. The SCC contains only 
one WR2 and WR9, but they can be accessed 
by either channel. All other registers are 
paired (one for each channel). 

Data Path. The transmit and receive data path 
illustrated in Figure 9 is identical for both 
channels. The receiver has three 8-bit buffer 
registers in an FIFO arrangement, in addition 
to the 8-bit receive shift register. This scheme 
creates additional time for the CPU to service 
an interrupt at the beginning of a block of 
high speed data. Incoming data is routed 
through one of several paths (data or CRC) 
depending on the selected mode (the character 
length in Asynchronous modes also determines 
the data path). 

The transmitter has an 8-bit Transmit Data 
buffer register loaded from the internal data 
bus and a 20-bit Transmit Shift register that 
can be loaded either from the synchronous 
character registers or from the Transmit Data 
register. Depending on the operational mode, 
outgoing data is routed through one of four 
main paths before it is transmitted from the 
Transmit Data output (TxD) 



Read Register Functions 



RRO Transmit/Receive buffer status and External status 

RR1 Special Receive Condition status 

RR2 Modified interrupt vector (Channel B only) 

Unmodified interrupt vector (Channel A only) 

RR3 Interrupt Pending bits (Channel A only) 

RR8 Receive buffer 

RR10 Miscellaneous status 

RR12 Lower byte of baud rate generator time constant 

RR13 Upper byte of baud rate generator time constant 

RR15 External/Status interrupt information 



Write Register Functions 



WRO CRC initialize, initialization commands for the 
various modes. Register Pointers 

WR1 Transmit/Receive interrupt and data transfer mode 
definition 

WR2 Interrupt vector (accessed through either channel) 

WR3 Receive parameters and control 

WR4 Transmit/Receive miscellaneous parameters and 
modes 

WR5 Transmit parameters and controls 

WR6 Sync characters or SDLC address field 

WR7 Sync character or SDLC flag 

WR8 Transmit buffer 

WR9 Master interrupt control and reset (accessed 

through either channel) 

WR10 Miscellaneous transmitter/receiver control bits 

WR11 Clock mode control 

WR12 Lower byte of baud rate generator time constant 

WR13 Upper byte of baud rate generator time constant 

WR14 Miscellaneous control bits 

WR15 External/Status interrupt control 

Table 1 . Read and Write Register Functions 



Programming The SCC contains write registers in each 
channel that are programmed by the system 
separately to configure the functional per- 
sonality of the channels. 



Z8530 

In the SCC, register addressing is direct for 
the data registers only, which are selected by a 
High on the D/C pin. In all other cases (with the 
exception of WRO and RRO), programming the 
write registers requires two write operations and 
reading the read registers requires both a write 
and a read operation. The first write is to WRO 
and contains three bits that point to the selected 
register. The second write is the actual control 
word for the selected register, and if the second 
operation is read, the selected read register is 
accessed. All of the registers in the SCC, 
including the data registers, may be accessed in 
this fashion. The pointer bits are automatically 
cleared after the read or write operation so that 
WRO (or RRO) is addressed again. 



All SCC registers are directly addressable. 
How the SCC decodes the address placed on 
the address/data bus at the beginning of a Read 
or Write cycle is controlled by a command 
issued in WROB. In the Shift Right mode the 
channel select A/B is taken from ADo and the 
state of AD5 is ignored. In the Shift Left mode 
the channel select A/B is taken from AD5 and 
the state of ADo is ignored. AD7 and AD5 are 
always ignored as address bits and the register 
address itself occupies AD4-AD1 . 

Z8S30/Z8030 

The system program first issues a series of 
commands to initialize the basic mode of 
operation. This is followed by other commands 
to qualify conditions within the selected mode. 
For example, the Asynchronous mode, 
character length, clock rate, number of stop 
bits, even or odd parity might be set first. Then 
the interrupt mode would be set, and finally, 
receiver or transmitter enable. 



263 



Programming 

(Continued) 



Read Registers. The SCC contains eight read 
registers (actually nine, counting the receive 
buffer (RR8) in each channel). Four of these 
may be read to obtain status information (RRO, 
RR1 , RR10, and RR15). Two registers (RR12 and 
RR13) may be read to learn the baud rate 
generator time constant. RR2 contains either the 
unmodified interrupt vector (Channel A) or the 
vector modified by status information (Channel 

Read Register 

[ D, I D 5 | D s | Dj , | D; | D„ | 



Rx CHARACTER AVAILABLE 
ZERO COUNT 

- Tx BUFFER EMPTY 
" DCD 

- SYNC/HUNT 

- CTS 

" Tx UNOERRUN/EOM 

- BREAK/ ABORT 



B). RR3 contains the Interrupt Pending (IP) bits 
(Channel A). Figure 10 shows the formats for 
each read register. 

The status bits of RRO and RR1 are carefully 
grouped to simplify status monitoring; e.g., 
when the interrupt vector indicates a Special 
Receive Condition interrupt, all the appropriate 
error bits can be read from a single register 
(RR1). 



Read Register 10 

[ 0, [ D. | D s 1 D. | D 3 | D, | D, | D | 



- LOOP SENDING 



• TWO CLOCKS HISSING 



E CLOCK MISSING 



Read Register 1 

j p. r;. p. □, p J o. o, o 1 

L 



ALL SENT 
RESIDUE CODE 2 

- RESIDUE CODE 1 

- RESIDUE CODED 

- PARITY ERROR 

■ Rx OVERRUN ERROR 

- CROFHAMING ERROR 

■ END Of FRAME (SDLC) 



Read Register 12 

[d7V 



D, D, Dj D, O, D 



I Ltc °1 

I TC, 



■ TC, 

■ TC- 

■ TC, 

• TC« 

■ TC, 

■ TC, 



Read Register 2 

| D, 0, D, 0. D, D, 0. ; D | 

I u 

I V, 



► INTERRUPT VECTOR ' 



Read Register 13 



•MODIFIED IN B CHANNEL 



Read Register 3 



ID, I D, | D, D, Dj Dj 



CHANNEL 8 EXT/STAT IP* 
CHANNEL B Tx IP' 
CHANNEL B Rx IP* 
CHANNEL A EXT/STAT IP- 
CHANNEL A Tx IP* 
CHANNEL A Rx IP* 



■ALWAYS IN B CHANNEL 



Read Register IS 

| D, | D 6 j D 5 | D t j D } j ■ D, j D a | 

I L. 



■ ZERO COUNT IE 



- DCD IE 

■ SYNC/HUNT IE 

■ CTS IE 

■ Tx UNOERRUN/EOM IE 

■ BREAK/ABORT IE 



Figure 10. Read Register Bit Functions 



Write Registers. The SCC contains 13 write 
registers (14 counting WR8, the transmit buffer) 
in each channel. These write registers are 
programmed separately to configure the 
functional "personality" of the channels. In 
addition, there are two registers (WR2 and 



WR9) shared by the two channels that may be 
accessed through either of them. WR2 contains 
the interrupt vector for both channels, while 
WR9 contains the interrupt control bits. Figure 
1 1 shows the format of each write register. 



264 



Programming 

(Continued) 

Write Register (28530) 

| 0, | O, I D 5 | D, I D, I D, | D, | D,"] 



REGISTER 3 
REGISTER 4 
REGISTER S 
REGISTER B 
REGISTER 7 
REGISTER 8 
REGISTER 9 
REGISTER 10 
REGISTER 11 
REGISTER 12 
REGISTER 13 
14 












NULL CODE 








1 


POINT HIGH 





1 





RESET EXT/STAT INTERRUPTS 





1 


1 


SEND ABORT (SOLO 


1 








ENABLE INT ON NEXT Rx CHARACTER 


1 





1 


RESET TxINT PENDING 


1 


1 





ERROR RESET 


1 


1 


1 


RESET HIGHEST IUS 



NULL CODE 

RESET Rx CRC CHECKER 
RESET T« CRC GENERATOR 
RESET Tx UNDERRUN/EOM LATCH 



'WITH POINT HIGH COMMAND 

Write Register (Z8030) 

|D r |D 6 |D,i0,|0 J | D; |D,|D g | 



NULL CODE 
NULL CODE 

SELECT SHtFT LEFT MODE* 
SELECT SHIFT RIGHT MODE* 



NULL CODE 
NULL CODE 

RESET EXTfSTATUS INTERRUPTS 
SEND ABORT 

ENABLE INT ON NEXT Rx CHARACTER 
RESET Tx INT PENDING 
ERROR RESET 
RESET HIGHEST IUS 



NULL CODE 

RESET Rx CRC CHECKER 
RESET Tx CRC GENERATOR 
RESET Tx UNDERRUN/EOM LATCH 



■ B CHANNEL ONLY 



Write Register 1 

| D ; [ Dt, I > | 0* 1 D 3 | D, 1 P t j On | 



Li 



EXT INT ENABLE 
Tx INT ENABLE 

PARITY IS SPECIAL CONDITION 
Rx INT DISABLE 

Rx INT ON FIRST CHARACTER OR SPECIAL CONDITION 
INT ON ALL Rx CHARACTERS OR SPECIAL CONDITION 
Rx INT ON SPECIAL CONDITION ONLY 



Write Register 2 

| D 7 | D 6 | D s | 0, ; D 3 j D ; j Q, [ a | 



Lb 



> INTERRUPT VECTOR 



Write Register 3 

| D, : 6 P., ' D, ' D, D; D, j Dp | 



ENABLE 

SYNC CHARACTER LOAD INHIBIT 
ADDRESS SEARCH MODE (SDLC) 
Rx CRC ENABLE 
ENTER HUNT MODE 
AUTO ENABLES 



Rx 5 BITS/CHARACTER 
Rx 7 BITS/CHARACTER 
Rx 6 BITS/CHARACTER 
Rx 8 BITS/CHARACTER 



Write Register 4 



' — PARITY ENABLE 
I PARITY EVEN/ODD 

SYNC MODES ENABLE 

1 STOP 8ITICHARACTER 
in STOP BITS/CHARACTER 

2 STOP BITS/CHARACTER 



8 SIT SYNC CHARACTER 
16 BIT SYNC CHARACTER 
SDLC MODE (01111110 FLAG) 
EXTERNAL SYNC MODE 



XI CLOCK MODE 
X16 CLOCK MODE 
X32 CLOCK MODE 
X64 CLOCK MODE 



Write Register S 

| 0, | Ds | $ | O t | D 3 ] Dj j D, | D„ | 

L,. 



Lb 



CRC ENABLE 
RTS 

SDTC/CRC-16 
Tx ENABLE 
SEND BREAK 

Tx 5 BITS (OR LESSV C HARACTER 
Tx 7 BITS/CHARACTER 
Tx 6 BITS/CHARACTER 
Tx 8 BITS/CHARACTER 



■ DTR 



Write Register 6 

|D, |D t |D s |D < |Q i :D ? lD 1 'dT] 



r \ 



- WAITfDMA REQUEST ON RECEIVE/TRANSMIT 

■ WAITfDMA REQUEST FUNCTION 

■ WAIT/DMA REQUEST ENABLE 

Figure 11. Write 



SYNC? 


SYNCg 


SYNCs 


SYNCj 


SYNC3 


SYNCj 


SYNCi 


SYNCg 


SYNC, 


SYNCo 


SYNC5 


SYNC* 


SYNC3 


SYNC 2 


SYNC, 


SYNCo 


SYNCj 


SYNC 6 


SYNC5 


SYNC* 


SYNC3 


SYNCj 


SYNCi 


SYNCo 


SYNC3 


SYNCj 


SYNC, 


SYNCo 




1 


1 


1 


ADR; 


ADRe 


AOR5 


ADfl 4 


ADR 3 


AORi 


ADR, 


ADRo 


ADR, 


ADR G 


ADRs 


ADRfl 




X 







MONOSYNC. 8 BITS 
MONOSYNC. 6 BITS 
BISYNC. 16 BITS 
BISYNC. 12 BITS 
SDLC 

SDLC (ADDRESS RANGE) 



Register Bit Functions 



265 



Programming 

(Continued) 



SYNC? 
SYNC 5 
SYNC15 
SYNCn 



SYNCe 
SYNC4 
SYNCi* 
SYNCo 



Write Register 7 

I D ? [ D 6 j D s | Q 4 | Q 3 I D a I D, | Do | 



SYNCb 

SYNC3 

SYNC, 3 
SYNC9 
1 



r \ 



SYNC* 
SYNC 2 
SYNC,j 
SYNCb 



SYNC3 
SYNC» 
SYNC 1 1 
SYNC7 



SYNC 2 
SYNCo 
SYNC to 
SYNCb 



MONOSYNC, B BITS 
MONOSYNC. 6 BITS 
BISYNC. 16 BITS 
BISYNC, 12 BITS 
SOLC 



Write Register 9 



Id, D s ! D s O, l D, ! O, D, Do 



Li 



NV 
- DLC 

■ MIE 

■ STATUS HIGH/STATUSTOW 



NO RESET 
CHANNEL RESET B 
CHANNEL RESET A 
FORCE HARDWARE RESET 



Write Register 10 

|D, D/P,, D< P; D. D' 1 Dp I 



U: 



L e BITreUT SYNC 
LOOP MODE 
ABORT/FLAG ON UNDERRUN 



- MARKfFLAG IDLE 
■ GO ACTIVE ON POLL 



NRZ 
NAZI 

FM1 (TRANSITION = 1) 
FMD (TRANSITION = 0) 



- CRC PRESET I/O 



Write Register 11 



O] D] O, Dg 



TR*C OUT = XTAL OUTPUT 
TR"«C OUT = TRANSMIT CLOCK 
TRxC OUT = BR GENERATOR OUTPUT 
TR»C OUT = DPLL OUTPUT 
- TRxC O/i 



TRANSMIT CLOCK = RTiC PIN 

TRANSMIT CLOCK = TRxC PIN 

TRANSMIT CLOCK = BR GENERATOR OUTPUT 

TRANSMIT CLOCK = DPLL OUTPUT 



RECEIVE CLOCK = RTxC PIN 

RECEIVE CLOCK = ffftC PIN 

RECEIVE CLOCK = BR GENERATOR OUTPUT 

RECEIVE CLOCK = DPLL OUTPUT 

RTxC XTAUNO XTAL 



Write Register 12 

| O r ! 6 : D. ' D. ' D; ' D : , ' D, O3 I 



L 



Write Register 13 

L TC B 
- TC, 
. TC,o 



Lb; 



- TCi 
. TC,j 
. TC,. 

- TC, S 



Write Register 14 

| D, | D. | P, | P. ! D, j D, | D, P."] 

L 



BR GENERATOR ENABLE 
BR GENERATOR SOURCE 
DTRJREQUEST FUNCTION 
AUTO ECHO 
LOCAL LOOPBACK 



NULL COMMAND 
ENTER SEARCH MODE 
RESET MISSING CLOCK 
DISABLE DPLL 

SET SOURCE = BR GENERATOR 
SET SOURCE = RTxC 
SET FM MODE 
SET NRZI MODE 



Write Register 15 

| 0- D. D. 0, D-, D : D, P.. | 



- ZERO COUNT IE 

- 

- DCD IE 

- SYNC/HUNT IE 

- CTS IE 

- Tx UNDERRUNfEOM IE 

- BREAK/ABORT IE 



Figure 11. Write Register Bit Functions (Continued) 



266 



Z8530 Timing Th e SC C generates internal control signals 
from WR and RD that are related to PCLK. 
Since PCLK has no phase relationship with 
WR and RD, the circuitry generating these 
internal control signals must provide time for 
metastable conditions to disappear. This gives 
rise to a recovery time related to PCLK. The 
recovery time applies only between bus trans- 
actions involving the SCC. The recovery time 
required for proper operation is specified from 
the falling edge of WR or RD in the first 
transaction involving the SCC to the falling 



edge of WR or RD in the second transaction 
involving the SCC. This time must be at least 4 
PCLK regardless of which register or channel is 
being accessed. 

Read Cycle Timing. Figure 12 illustrates 
Read cycle timin g. Addre sses on A/B and D/C 
and the status on INTACK must remain stable 
throughout the cycle. If CE falls after RD falls or 
if it rises before RD rises, the effective RD is 
shortened. 



X 



ADDRESS VALID 



z 



DATA VALID 



Figure 12. Read Cycle Timing 



Write Cycle Timing. Figure 13 illustrates 
Write cycle timin g. Addre sses on A/B and D/C 
and the status on INTACK must remai n sta ble 
throughout the cycle. If CE falls after WR falls 



or if it rises before WR rises, the effective WR is 
shorten ed. D ata must be valid before the falling 
edge of WR. 



ADDRESS VALID 



3CZ 



JL 



WR 



f 



DATA VALID 



Figure 13. Write Cycle Timing 



Interrupt Acknowledge Cycle Timing. Figure 
14 illustrates Interrupt A cknowled ge cycle 
timing. Between the time INTACK goes Low 
and the falling edge of RD, the internal and 
external IEI/IEO daisy chains settle. If there is 
an interrupt pending in the SCC and IEI is High 



when RD falls, the Acknowledge cycle is 
intended for the SCC. In this case, the SCC 
may be programmed to respond to RD Low by 
placing its interrupt vector on D0-D7 and it then 
sets the appropriate Interrupt-UnderService 
latch internally. 



INTACK 



-fj- 
-ff- 



f 



f 



< ) f" VECTOR } - 



Figure U. Interrupt Acknowledge Cycle Timing 



267 



Z8030 Timing The SCC generates internal control signals 
from AS and DS that are related to PCLK. 
Since PCLK has no phase relationship with 
AS and DS, the circuitry generating these 
internal control signals must provide time for 
metastable conditions to disappear. This gives 
rise to a recovery time related to PCLK. The 
recovery time applies only between bus trans- 
actions involving the SCC. The recovery time 
required for proper operation is specified from 
the falling edge of DS in the first transaction 



involving the SCC to the falling edge of DS in 
the second transaction involving the SCC . 

Read Cycle Timing. Figure 15 illustrates 
Read cycle timing. The address o n AD0-AD7 
and the state of CSo and INTACK are latched 
by the rising edge of AS. Ft/W must be High to 
indicate a Read cycle. CSi must also be High 
for the Read cycle to occur. The data bus 
drivers in the SCC are then enabled while 
DS is Low. 



^ L 



7 ^ 



3 C 



X 



DATA VALID 



T 



R/W 



T 



f 



Figure 15. Road Cycle Timing 



Write Cycle Timing. Figure 16 illustrates 
Write cycle timing. The address o n AD0-AD7 
and the state of CSo and INTACK are latched 
by the rising edge of AS. R/W must be Low to 



indicate a Write cycle. CSi must be High for the 
Write cycle to occur. DS Low strobes the data 
into the SCC. 



cs 



^ n 

7 zz 

XEEDOC 

v 

/ 



3C 
£1 



f 



Figure 16. Write Cycle Tuning 



268 



Interrupt Acknowledge Cycle Timing. Figure 
17 illustrates Interrupt Acknowledge cycle 
timing. The address on AD0-AD7 and the state 
of CSo and INTACK are latched b y the rising 
edge of AS. However, if INTACK is Low, the 
address and CSo are ignored. The state of the 
R/W and CS\ are also ignored for the duration 
of the Interrupt A ckn owledge cycle. Between 
the rising edge of AS and the falling edge of 

v / /> — 



DS, the internal and external IEI/IEO daisy 
chains settle. If there is an interrupt pending in 
the SCC and IEI is High when DS falls, the 
Acknowledge cycle was intended for the SCC. 
In this case, the SCC may be programmed to 
respond to'RD Low by placing its interrupt 
vector on D0-D7 and it then internally sets the 
appropriate Interrupt-Under-Service latch. 



X L 



-ff- 
-fj- 



-fj- 
-tj- 



AO0-AD7 )( (IGWOBED) - ^ // { 

** — V 



Figure 17. Interrupt Acknowledge Cycle Timing 



Absolute Voltages on all pins with respect 

Maximum to GND - 0.3V to + 7.0V 

Ratings Operating Ambient 

Temperature See Ordering Information 

Storage Temperature -65 °C to + 1 50 °C 



Stresses greater than those listed under Absolute Maxi- 
mum Ratings may cause permanent damage to the device. 
This is a stress rating only; operation of the device at any 
condition above those indicated in the operational sections 
of these specifications is not implied. Exposure to absolute 
maximum rating conditions for extended periods may affect 
device reliability. 



Standard The DC characteristics and capacitance sec- 

Test tion below apply for the following standard test 

Conditions conditions, unless otherwise noted. All voltages 

are referenced to GND. Positive current flows 

into the referenced pin. 

Standard conditions are as follows: 



■ GND = V 

■ Ta as specified in Ordering Information 

All ac parameters assume a load capacitance 
of 50 pF max. 




3 V 

l 



Standard Test Load 



Open-Drain Test Load 



269 



DC 

Charac- 
teristics 


Symbol 


Parameter Min 


Max 


Unit 


Condition 


V,H 
V,L 
V H 

Vol 
la 

lOL 

Ice 


Input High Voltage 2.0 
Input Low Voltage -0.3 
Output High Voltage 2.4 
Output Low Voltage 
Input Leakage 
Output Leakage 
Vcc Supply Current 


Vcc + 0.3 
0.8 

0.4 
+ 10.0 
±10.0 
250 


V 
V 
V 
V 

mA 


Iqh = - 250 nA 
Iol= +2.0 mA 

(14 < V™ <: 4-9 AV 
\J.H — VJJJ — -t-Z.*4V 

0.4 s V OUT < +2.4V 




Vcc = S V ± 5% unless otherwise specified, over specified temper 


ature range. 






Capacitance 


Symbol 


Parameter Min 


Max 


Unit 


Test Condition 




CoUT 
C I/0 


Input Capacitance 
Output Capacitance 
Bidirectional Capacitance 


10 

1 R 

20 


pF 

pr 

nF 
pr 


Unmeasured Pins 
Returned to Ground 




f ■ 1 MHz, over specified temperature range. 
Unmeasured pins returned to ground. 








Miscellaneous 




Gate Count 


6000 







270 



Z8530 AC CHARACTERISTICS 









4 MHz 


6 MHz 


8 MHz 




Number 


Symbol 


Parameter 


Min 


Max 


Min 


Max 


Min 


Max 


Notes t 


1 


TwPCI 


PCLK Low Width 


105 


2000 


70 


1000 


50 


1000 




2 


TwPCh 


PCLK High Width 


105 


2000 


70 


1000 


50 


1000 




-3 


TfPC 


PCLK Fall Time 




20 




10 




10 




4 


TrPC 


PCLK Rise Time 




20 




10 




10 




5 


TcPC 


PCLK Cycle Time 


250 


4000 


165 


2000 


125 


2000 




6 


TsA(WR) 


Address to WR I Setup Time 


80 




80 




70 






7 


ThA(WR) 


Address to WR T Hold Time 



















8 


TsA(RD) 


Address to RD I Setup Time 


80 




80 




70 






9 


ThA(RD) 


Address to RD t Hold Time 



















10 


TslA(PC) 


INTACK to PCLK t Setup Time 


10 




10 




10 






11 


TslAi(WR) 


INTACK to WR i Setup Time 


200 




160 




145 




1 


12 


ThlA(WR) 


INTACK to WRT Hold Time 



















13 


TslAi(RD) 


INTACK to RD i Setup Time 


200 




160 




145 




1 


14 


ThlA(RD) 


INTACK to RDt Hold Time 



















15 


ThlA(PC) 


INTACK to PCLK t Hold Time 


100 




100 




85 






16 


TsCEI(WR) 


CE Low to WR 4 Setup Time 



















17 


ThCE(WR) 


CE to WR T Hold Time 



















18 


TsCEh(WR) 


CE High to WR 1 Setup Time 


100 




70 




60 






19 


TsCEI(RD) 


CE Low to RD I Setup Time 

















1 


20 


ThCE(RD) 


CE to RD t Hold Time 

















1 


21 


TsCEh(RD) 


CE High to RD i Setup Time 


100 




70 




60 




1 


22 


TwRDI 


RD Low Width 


240 




200 




150 




1 


23 


TdRD(DRA) 


RD i to Read Data Active Delay 



















24 


TdRDr(DR) 


RD t to Read Data Not Valid Delay 



















25 


TdRDf(DR) 


RD 1 to Read Data Valid Delay 




250 




180 




140 




26 


TdRD(DRz) 


RD t to Read Data Float Delay 




70 




45 




40 


2 



NOTES: 

1 . Parameter does not apply to Interrupt Acknowledge transactions. 

2. Float delay is defined as the time required for a ±0.5V change at the output with a maximum dc load and minimum ac load. 
tUnits in nanoseconds (ns). 



Reset 
Timing 

Z8530 



Cycle 
Timing 

Z8530 




f 



\ r 



-®- 



-fs- 



■v 



271 



Z8530 AC CHARACTERISTICS (Continued) 









4 MHz 


6 MHz 


8 MHz 




Number 


Symbol 


Parameter 


Min 


Max 


Min 


Max 


Min 


Max I 


Motes t 


27 


TdA(DR) 


Address Required Valid to Read Data 




















Valid Delay 




300 




280 




220 




28 


TwWRI 


WR Low Width 


240 




200 




150 






29 


TsDW(WR) 


Write Data to WR i Setup Time 


10 




10 




10 






30 


ThDW(WR) 


Write Data to WR t Hold Time 



















31 


TdWR(W) 


WR I to Wait Valid Delay 




240 




200 




170 


4 


32 


TdRD(W) 


RD I Wait Valid Delay 




240 




200 




170 


4 


33 


TdWRf(REQ) 


WR 1 to W/REQ Not Valid Delay 




240 




200 




170 




34 


TdRDf(REQ) 


RD I to W/REQ Not Valid Delay 




240 




200 




170 




35 


TdWRr(REQ) 


WR 1 DTR/REQ Not Valid Delay 




4TCPC 




4TcPC 




4TcPC 




36 


TdRDr(REQ) 


RD t to DTR/REQ Not Valid Delay 




4TcPC 




4TcPC 




4TcPC 




37 


TdPC(INT) 


PCLK I to FRT Valid Delay 




500 




500 




500 


4 


38 


TdlAi(RD) 


INTACK to RD 4 (Acknowledge) Delay 


250 




200 




150 




5 


39 


TwRDA 


RD (Acknowledge) Width 


250 




200 




150 






40 


THRDAmRl 


RH L I'ArknriwffvSn^ tn Ra^H Data 




















Valid Delay 




250 




180 




140 




41 


TslEI(RDA) 


IEI to RD I (Acknowledge) Setup 




















Time 


120 




100 




95 






42 


ThlEI(RDA) 


IEI to RD t (Acknowledge) Hold Time 



















43 


TdlEI(IEO) 


IEI to IEO Delay Time 




120 




100 




95 




44 


TdPC(IEO) 


PCLK t to IEO Delay 




250 




250 




200 




45 


TdRDA(INT) 


RD J. to INT Inactive Delay 




500 




500 




450 


4 


46 


TdRD(WRQ) 


RD t to WR i Delay for No Reset 


30 




15 




15 






47 


TdWRQ(RD) 


WR T to RD I Delay for No Reset 


30 




30 




20 






48 


TwRES 


WR and RD Coincident Low for Reset 


250 




200 




150 






49 


Trc 


Valid Access Recovery Time 


4TcPC 




4TcPC 




4TcPC 




3 



NOTES: 

3. Parameter applies only between transactions involving the SCC. 

4. Open-drain output, measured with open-drain test load. 

5. Parameter is system dependent. For any SCC in the daisy chain, TdlAi(RD) must be greater than the sum of TdPC(IEO) for the highest priority de- 
vice in the daisy chain, TslEI(RDA) for the SCC, and TdlElf(IEO) for each device separating them in the daisy chain. 

tUnits in nanoseconds (ns). 



272 




274 



Z8030 AC CHARACTERISTICS 









4 MHz 


6 MHz 


8 MHz 




Number 


Symbol 


Parameter 


Min 


Max 


Min 


Max 


Min Max 


Notes t 


1 


TwAS 


AS Low Width 


70 




50 




35 




2 


TdDS(AS) 


DS t to AS 1 Delay 


50 




25 




15 




3 


TsCSO(AS) 


CS to AS t Setup Time 















1 


4 


ThCSO(AS) 


CSo to AS t Hold Time 


60 




40 




30 


1 


5 


TsCS1(DS) 


CSi to DS i Setup Time 


100 




80 




65 


1 


6 


ThCS1(DS) 


CS-| to DSt Hold Time 


55 




40 




30 


1 


7 


TslA(AS) 


INTACK to AS t Setup Time 


10 




10 




10 




8 


ThlA(AS) 


INTACK to AST Hold Time 


250 




200 




150 




9 


TsRWR(DS) 


R/W (Read) to DS i Setup Time 


100 




80 




65 




10 


ThRW(DS) 


R/W to DS T Hold Time 


55 




40 




35 




11 


TsRWW(DS) 


RAW (Write) to DS I Setup Time 

















12 


TdAS(DS) 


AS t to DS i Delay 


60 




40 




30 




13 


TwDSI 


DS Low Width 


240 




200 




150 




14 


TrC 


Valid Access Recovery Time 


4TcPC 




4TcPC 




4TcPC 


2 


15 


TsA(AS) 


Address to AS T Setup Time 


30 




10 




10 


1 


16 


ThA(AS) 


Address to AS t Hold Time 


50 




30 




25 


1 


17 


TsDW(DS) 


Write Data to DS I Setup Time 


30 




20 




15 




18 


ThDW(DS) 


Write Data to DS 1 Hold Time 


30 




20 




20 




19 


TdDS(DA) 


DS i to Data Active Delay 

















20 


TdDSr(DR) 


DS t to Read Data Not Valid Delay 

















21 


TdDSf(DR) 


DS i to Read Data Valid Delay 




250 




180 


140 




22 


TdAS(DR) 


AS t to Read Data Valid Delay 




520 




300 


250 




NOTES: 



1 . Parameter does not apply to Interrupt Acknowledge transactions. 

2. Parameter applies only between transactions involving the SCC. 

tUnits in nanoseconds (ns). 



275 



Z8030 AC CHARACTERISTICS (Continued) 









4 MHz 


6 MHz 


8 MHz 




Number 


Symbol 


Parameter 


Min Max 


Min Max 


Min Max 


Notes t 


23 


TdDS(DRz) 


DS T to Read Data Float Delay 


70 


45 


40 


3 


24 


TdA(DR) 


Address Required Valid to Read Data 














Valid Delay 


570 


310 


260 




25 


TdDS(W) 


DS I to Wait Valid Delay 


240 


200 


170 


4 


26 


TdDSf(REQ) 


DS 1 to W/REQ Not Valid Delay 


240 


200 


170 




27 


TdDSr(REQ) 


DS 1 to DTR/REQ Not Valid Delay 


4TcPC 


4TcPC 


4TCPC 




28 


TdAS(INT) 


AS T to TNT Valid Delay 


500 


500 


500 


4 


29 


TdAS(DSA) 


AS T to DS i (Acknowledge) Delay 


250 


250 


250 


5 


30 


TwDSA 


DS (Acknowledge) Low Width 


390 


200 


150 




31 


TdDSA(DR) 


DS I (Acknowledge) to Read Data 














Valid Delay 


250 


180 


140 




32 


TslEI(DSA) 


IEI to DS I (Acknowledge) Setup Time 


120 


100 


80 




33 


ThlEI(DSA) 


IEI to DS T (Acknowledge) Hold Time 













34 


TdlEI(IEO) 


IEI to IEO Delay 


120 


100 


90 




35 


TdAS(IEO) 


AS t to IEO Delay 


250 


250 


200 


6 


36 


TdDSA(INT) 


DS i (Acknowledge) to TNT Inactive 














Delay 


500 


500 


450 


4 


37 


TdDS(ASQ) 


DS t to AS I Delay for No Reset 


30 


15 


15 




38 


TdASQ(DS) 


AS T to DS I Delay for No Reset 


30 


30 


20 




39 


TwRES 


AS and DS Coincident Low for Reset 


250 


200 


150 


7 


40 


TwPCI 


PCLK Low Width 


105 2000 


70 1000 


50 




41 


TwPCh 


PCLK High Width 


105 2000 


70 1000 


50 




42 


TcPC 


PCLK Cycle Time 


250 4000 


165 2000 


125 




43 


TrPC 


PCLK Rise Time 


20 


10 


10 




44 


TfPC 


PCLK Fall Time 


20 


10 


10 




NOTES: 














3. Float delay is defined as 


the time required for a + 0.5V change in the output with a maximum dc load and a minimum ac load. 





4. Open-drain output, measured with open-drain test load. 

5. Parameter is system dependent. For any Z-SCC in the daisy chain, TdAS(DSA) must be greater than the sum of TdAS(IEO) for the highest priority 
device in the daisy chain, TslEI(DSA) for the Z-SCC, and TdlElf(IEO) for each device separating them in the daisy chain. 

6. Parameter applies only to a Z-SCC pulling INT Low at the beginning of the Interrupt Acknowledge transaction. 

7. Internal circuitry allows for the reset provided by the Z8 to be recognized as a reset by the Z-SCC. 
All timing references assume 2.0V for a logic "1 " and 0.8V for a logic "0". 

tUnits in nanoseconds (ns). 



276 




277 



Z8030/Z8530 GENERAL TIMING AC CHARACTERISTICS 









4 MHz 


6 MHz 


8 MHz 




Number 


Symbol 


Parameter 


Min 


Max 


Min 


Max 


Min 


Max 


Notes t 


1 


TdPC(REQ) 


PCLK 1 to W/REQ Valid Delay 




250 




250 




250 




2 


TdPC(W) 


PCLK 1 to Wait Inactive Delay 




350 




350 




350 




3 


TsRXC(PC) 


RxC t to PCLK T Setup Time 




















(PCLK + 4 case only) 


80 


TwPCL 


70 


TwPCL 


60 


TwPCL 


1,4 


4 


TsRXD(RXCr) 


RxD to RxC T Setup Time (X1 Mode) 

















1 


5 


ThRXD(RXCr) RxD to RxC t Hold Time (X1 Mode) 


150 




150 




150 




1 


6 


TsRXD(RXCf) 


RxD to RxC I Setup Time (X1 Mode) 

















1,5 


7 


ThRXD(RXCf) RxD to RxC i Hold Time (X1 Mode) 


150 




150 




150 




1,5 


8 


TsSY(RXC) 


SYNC to RxC t Setup Time 


-200 




-200 




-200 




1 


9 


ThSY(RXC) 


SYNC to RxC t Hold Time 


3TcPC 




3TcPC 




3TcPC 












+ 400 




+ 320 




+ 250 




1 


10 


TsTXC(PC) 


TxC" I to PCLK T Setup Time 

















2,4 


11 


TdTXCffTXD) 


TxC I to TxD Delay (X1 Mode) 




300 




230 




200 


2 


12 


TdTxCrtTXD) 


TxC T to TxD Delay (X1 Mode) 




300 




230 




200 


2,5 


13 


TdTXDfTRX) 


TxD to TRxC Delay (Send Clock 




















Echo) 




200 




200 




200 




14 


TwRTXh 


RTxC High Width 


180 




180 




150 




6 


15 


TwRTXI 


RTxC Low Width 


180 




180 




150 




6 


16 


TcRTX 


RTxC Cycle Time (RxD, TxD) 


1000 




640 




500 




6,7 


17 


TcRTXX 


Crystal Oscillator Period 


250 


1000 


165 


1000 


125 


1000 


3 


18 


TwTRXh 


TRxC High Width 


180 




180 




150 




6 


19 


TwTRXI 


TRxC Low Width 


180 




180 




150 




6 


20 


TcTRX 


TRxC Cycle Time 


1000 




640 




500 




6,7 


21 


TwEXT 


DCD or CTS Pulse Width 


200 




200 




200 






22 


TwSY 


SYNC Pulse Width 


200 




200 




200 







NOTES: 

1. RxC is RTxC or TRxC , whichever is supplying the receive clock. 

2. TxC i s TRxC or RTxC, whichever is supplying the transmit clock. 

3. Both RTxC and SYNC have 30 pf capacitors to ground connected to them. 

4. Parameter applies only if the data rate is one-fourth the PCLK rate. In all other cases, no phase relationship between RxC and PCLK or TxC and 
PCLK is required. 

5. Parameter applies only to FM encoding/decoding. 

6. Parameter applies only for transmitter and receiver; DPLL and baud rate generator timing requirements are identical to case PCLK requirements. 

7. The maximum receive or transmit data is Va PCLK. 

tUnits in nanoseconds (ns). 



278 



RTxC, TRxC 

RECEIVE 



TRxC, RTkC 

TRANSMIT 



TRxC 

OUTPUT 



SYNC 

INPUT 



SYNC \r 

EXTERNAL /V 



/ 



®- 








CD - 

X 




— ©■ 


1 * 


•■ — 


H 



-©- 



-if- 
-tj- 



-<s>- 



-®- 



X 

-®- 



-®- 
-®- 



-®- 



-®- 



— ® ► 



— ® — /~ 

- — ® — A \- — ® — H 



X 



279 



Z8030/Z8530 SYSTEM TIMING AC CHARACTERISTICS 



4 MHz 6 MHz 8 MHz 



Number Symbol 


Parameter 


Min 


Max 


Min 


Max 


Min 


Max 


Notes f 


1 


TdRXC(REQ) 


RxC T to W/REQ Valid Delay 


8 


12 


8 


12 


8 


12 


2 


2 


TdRXC(W) 


RxC t to Wait Inactive Delay 


8 


14 


8 


14 


8 


14 


1,2 


3 


TdRXC(SY) 


RxC t to SYNC Valid Delay 


4 


7 


4 


7 


4 


7 


2 


ta. 




RxC T to INT Valid Delay 


10 


16 


10 


16 


10 


16 


1,2 


dh 

tu. 






8 


12 


8 


12 


8 


12 


1,2 








+ 2 


+ 3 


+ 2 


+ 3 


+ 2 


+ 3 


4 


5 


TdTXC(REQ) 


TxC" i to W/REQ Valid Delay 


5 


8 


5 


8 


5 


8 


3 


6 


TdTXC(W) 


TxC I to Wait Inactive Delay 


5 


11 


5 


11 


5 


11 


1,3 


7 


TdTXC(DRQ) 


TxC I DTR/REQ Valid Delay 


4 


7 


4 


7 


4 


7 


3 


8a 


TdTXC(INT), Z8530 


TxC I to InT Valid Delay 


6 


10 


6 


10 


6 


10 


1,3 


8b. 


TdTXC(INT), Z8030 




4 


6 


4 


6 


4 


6 


1,3 








+ 2 


+ 3 


+ 2 


+ 3 


+ 2 


+ 3 


4 


9a. 


TdSY(INT), Z8530 


SYNC Transition to INT Valid Delay 


2 


6 


2 


6 


2 


6 


1 


9b. 


TdSY(INT), Z8030 




2 


3 


2 


3 


2 


3 


1,4 


10a. 


TdEXT(INT), Z8530 


DCD or CTS Transition to INT Valid Delay 


2 


6 


2 


6 


2 


6 


1 


10b. 


TdEXT(INT), Z8030 




2 


3 


2 


3 


2 


3 


1,4 



NOTES: 

1 . Ope n- drain o ut put, m easured with open-drain test load. 

2. RxC is RTxC or TRxC , whichever is supplying the receive clock. 

3. TxC is TRxC or RTxC, whichever is supplying the transmit clock. 

4. Units equal to AS". 



tUnits equal to TcPC. 



280 



System 
Timing 



BTxC, TRxC 

RECEIVE 



WIRED 

WAIT 



INT 



\ / — \ / V 



-(Eh 



> 



J 



-©- 



RTxC, TRxC 

TRANSMIT 



W/REQ 

REQUEST 



/ \ / \ r 



-®- 



-®- 



-®- 



CD.RI 








SYNC 

INPUT 






h — ® — ► 


< 


INT 


s 

- — ■ — - 





281 



Zilog 



Product Specification 



Z8036 Z8000® Z-CIO 
Counter/Timer and 
Parallel I/O Unit 



October 1988 



Features 



Two independent 8-bit, double-buffered, 
bidirectional I/O ports plus a 4-bit 
special-purpose I/O port. I/O ports 
feature programmable polarity, 
programmable direction (Bit mode), "pulse 
catchers," and programmable open- 
drain outputs. 

Four handshake modes, including 3- Wire 
(like the IEEE-488). 



REQUEST/WAIT signal for high-speed data 
transfer. 



Flexible pattern-recognition logic, program- 
mable as a 16- vector interrupt controller. 

Three independent 16-bit counter/timers 
with up to four external access lines per 
counter/timer (count input, output, gate, 
and trigger), and three output duty cycles 
(pulsed, one-shot, and square-wave), 
programmable as retriggerable or 
nonretriggerable . 

Easy to use since all registers are read/write 
and directly addressable. 



General The Z8036 Z-CIO Counter/Timer and 

Description Parallel I/O element is a general-purpose 
peripheral circuit, satisfying most 
counter/timer and parallel I/O needs 
encountered in system designs. This versatile 
device contains three I/O ports and three 
counter/timers. Many programmable options 
tailor its configuration to specific applications. 



The use of the device is simplified by making 
all internal registers (command, status, and 
data) readable and (except for status bits) 
writable. In addition, each register is given its 
own unique address so that it can be 
accessed directly — no special sequential 
operations are required. The Z-CIO is directly 
Z-Bus compatible. 



AD, 


PA, 






AOg 






»D S 


PA, 




AO, 


m, 




AD, 


PA, 




AD2 


PA, 






AD, 


PA, 




AD„ 


PA,; 




AS 


PC, 




65 Z«03» 


PC; 




PJW Z-CIO 


PC, 




CSo 


pc„ 




cs. 


PB, 




INT 


PB„ 




INTACK 


PB, 




IEI 


PB, 




IEO 


PB, 






PB, 










PB, 










PB„ 









TT 



PCLK +5 V GND 



Figure 1. Pin Functions 



AO.C 




W 


40 


3 AD, 


AD S C 






3S 


3 AD, 


AD.C 


* 




38 


] AD, 


AD,C 






37 


] Aft, 


BSC 






36 


JcS 




• 






]cs, 


gndC 






- 


3*5 


PBoL 


s 




33 


]PAo 


PB,C 


• 




33 


]PA, 


PB,C 


10 


Z8030 
Z-CIO 


31 


3 PA, 


PB.C 


11 


30 


3 PA, 


pb«e 


12 




29 


Jp-v, 


pb s L 


13 




31 


]PA S 


ps.L 


14 




27 


] PA. 


PB,C 


15 




& 


] PA, 


pclkC 


16 




25 


3 INTACK 


mQ 


17 




2t 


3 fNT 


IE0C 


18 




23 


3 +5V 


pcL 


19 




32 


3 PC, 


pc,C 


20 




2, 


3 pc. 



Figure 2a. 40-pin Dual-ln-Line Package (Drp). 
Pin Assignments 



282 



2014-001.002 



Pin AD0-AD7. Z-Bus Address/Data lines 

Description (bidirectional/3-state). These multiplexed 

Address/Data lines are used lor transfers 

between the CPU and Z-CIO. 

AS*. Addr ess Strobe (input, active Low). 
Addr esses , 1NTACK, and CSrj are sampled 
while AS is Low. 

CS U and CSi. Chip Select 0. (input, active 
Low ) and Chip Select 1 (input, active High). 
CSo ar >d CS) must be Low and Higjh^ respec- 
tively, in order to select a device. CSo > s 
latched by AS. 

DS*. Data Strobe (input, active Low). DS pro- 
vides timing for the transfer of data into or out 
of the Z-CIO. 

IEI. Interrupt Enable In (input, active High). 
IEI is used with IEO to form an interrupt daisy 
chain when there is more than one interrupt- 
driven device. A High IEI indicates that no 
other higher priority device has an interrupt 
under service or is requesting an interrupt. 

IEO. Interrupt Enable Out (output, active 
High). IEO is High only if IEI is High and the 
CPU is not servicing an interrupt from the 
requesting Z-CIO or is not requesting an inter- 
rupt (Interrupt Acknowledge cycle only). IEO 
is connected to the next lower priority device's 
IEI input and thus inhibits interrupts from 
lower priority devices. 

'When AS and DS are delected Low at the same time (normally 
an illegal condition), the Z-CIO is reset. 



INT. Interrupt Request (output, open-drain, 
active Low). This signal is pulled Low when 
the Z-CIO requests an interrupt. 



INTACK. Interrupt Acknowledge (input, active 
Low). This signal indicates to the Z-CIO that 
an Interr upt Acknowledge cycle is in progress. 
INTACK is sampled while AS is Low. 

PA0-PA7. Port A I/O lines (bidirectional, 
3-state, or open-drain). These eight I/O lines 
transfer information between the Z-CIO's Port 
A and external devices. 

PB0-PB7. Port B I/O lines (bidirectional, 
3-state, or open-drain). These eight I/O lines 
transfer information between the Z-CIO's Port 
B and external devices. May also be used to 
provide external access to Counter/Timers 
1 and 2. 

PC0-PC3. Port C I/O lines (bidirectional, 
3-state, or open-drain). These f our I/O lines 
are used to provide handshake, WAIT, and 
REQUEST lines for Ports A and B or to provide 
external access to Counter/Timer 3 or access 
to the Z-CIO's Port C. 

PCLK. (input, TTL- compatible). This is a 
peripheral clock that may be, but is not 
necessarily, the CPU clock. It is used with 
timers and REQUEST/WAIT logic. 

R/W. Head/Write (input). R/W indicates that 
the CPU is reading from (High) or writing to 
(Low) the Z-CIO. 




Figure 2b. 44-pin Chip Carrier, 
Pin Assignments 



283 



Architecture 



The Z8036 Z-CIO Counter/Timer and 
Parallel I/O element (Figure 3) consists of a 



Z-Bus interface, three I/O ports (two general- 
purpose 8-bit ports and one special-purpose 



' INTERRUPT ' 



INTERRUPT 
CONTROL 
LOGIC 



CONTROL ' 



INTERNAL 
CONTROL 
LOGIC 



■\ COUNTER' / \ 

/ TIMER 3 ^ ^ 



■\ COUNTER* \ 
./ TIMER 2 V 



N PORT A r 



2, 



i port c y 



< * — i — s 

N PORT B ' 



Figure 3. Z-CIO Block Diagram 



284 



Architecture 4-bit port), three 16-bit counter/timers, an 
(Continued) interrupt control logic block, and the internal 
control logic block. An extensive number of 
programmable options allow the user to tailor 
the configuration to best suit the specific 
application. 

The two general-purpose 8-bit I/O ports 
(Figure 4) are identical, except that Port B can 
be specified to provide external access to 
Counter/Timers 1 and 2. Either port can be 
programmed to be a handshake-driven, 
double-buffered port (input, output, or bidirec- 
tional) or a control-type port with the direction 
of each bit individually programmable. Each 
port includes pattern-recognition logic, allow- 
ing interrupt generation when a specific pat- 
tern is detected. The pattern-recognition logic 
can be programmed so the port functions like 
a priority- interrupt controller. Ports A and B 
can also be linked to form a 16-bit I/O port. 

To control these capabilities, both ports con- 
tain 12 registers. Three of these registers, the 



Input, Output, and Buffer registers, comprise 
the data path registers. Two registers, the 
Mode Specification and Handshake Specifica- 
tion registers, are used to define the mode of 
the port and to specify which handshake, if 
any, is to be used. The reference pattern for 
the pattern-recognition logic is defined via 
three registers: the Pattern Polarity, Pattern 
Transition, and Pattern Mask registers. The 
detailed characteristics of each bit path (for 
example, the direction of data flow or whether 
a path is inverting or noninverting) are pro- 
grammed using the Data Path Polarity, Data 
Direction, and Special I/O Control registers. 

The primary control and status bits are 
grouped in a single register, the Command 
and Status register, so that after the port is ini- 
tially configured, only this register must be 
accessed frequently. To facilitate initialization, 
the port logic is designed so that registers 
associated with an unrequired capability are 
ignored and do not have to be programmed. 



OUTPUT 

DATA 
REGISTER 



PATTERN 
RECOGNITION 
LOGIC 



TO COUNTER/TIMERS 1 AND 2 
(PORT 6 ONLY) 



X DATA A 

\ MULTIPLEXER / 



JI 



PORT 
CONTROL 
LOGIC 



INPUT 
BUFFER/ 
INVERTERS 
AND 



OUTPUT 
BUFFER/ 
INVERTERS 



TO PORT C 

Figure 4. Ports A and B Block Diagram 



285 



Architecture The function of the special-purpose 4-bit 
(Continued) port, Port C (Figure 5), depends upon the 
roles of Ports A and B. Port C provides the 
required handshake lines. Any bits of Port C 
not used as handshake lines can be used as 
I/O lines or to provide external access for the 
third counter/timer. 

Since Port C's function is defined primarily 
by Ports A and B, only three registers (besides 
the Data Input and Output registers) are 
needed. These registers specify the details of 
each bit path: the Data Path Polarity, Data 
Direction, and Special I/O Control registers. 

The three counter/timers (Figure 6) are all 
identical. Each is comprised of a 16-bit down- 
counter, a 16-bit Time Constant register 
(which holds the value loaded into the down- 
counter), a 16-bit Current Counter register 
(used to read the contents of the down- 
counter), and two 8-bit registers for control 
and status (the Mode Specification and the 
Command and Status registers). 

The capabilities of the counter/timer are 



numerous. Up to four port I/O lines can be 
dedicated as external access lines for each 
counter/timer: counter input, gate input, trig- 
ger input, and counter/timer output. Three dif- 
ferent counter/timer output duty cycles are 
available: pulse, one-shot, or square-wave. 
The operation of the counter/timer can be pro- 
grammed as either retriggerable or nonretrig- 
gerable. With these and other options, most 
counter/timer applications are covered. 

The interrupt control logic provides standard 
Z-Bus interrupt capabilities. There are five 
registers (Master Interrupt Control register, 
three Interrupt Vector registers, and the Cur- 
rent Vector register) associated with the inter- 
rupt logic. In addition, the ports' Command 
and Status registers and the counter/timers' 
Command and Status registers include bits 
associated with the interrupt logic. Each of 
these registers contains three bits for interrupt 
control and status: Interrupt Pending (IP), 
Interrupt Under Service (IUS), and Interrupt 
Enable (IE). 



TO PORT TO PORT 



HANDSHAKE 

AND 

REQUEST/WAIT 



OUTPUT 

DATA 
REGISTER 



1~L 



INPUT 
DATA 
REGISTER 



INPUT 

buffer; 
inverters 

AND 



7*V 



PORT 
CONTROL 
LOGIC 



/ J\m 

\ l C ° 



OUTPUT 
BUFFER/ 
INVERTERS 



Figuro 5. Port C Block Diagram 



286 



Architecture 

(Continued) 



TIME 
CONSTANT 
REGISTER 
(MSB's) 



TtME 
CONSTANT 
REGISTER 
(LSB'.) 



16-BIT 
DOWN 
COUNTER 



CURRENT 
COUNT 

REGISTER 
(MSB'S) 



5 



CURRENT 

COUNT 
REGISTER 



COUNTER/ 
TIMER 

CONTROL 
LOGIC 



3 



COUNTER 
CONTROL 
LINES 



Figure 6. Counter/Timer Block Diagram 



Functional The following describes the functions 
Description of the ports, pattern-recognition logic, 
counter/timers, and interrupt logic. 

I/O Port Operations. Of the Z-CIO's three 
I/O ports, two (Ports A and B) are general- 
purpose, and the third (Port C) is a special- 
purpose 4-bit port. Ports A and B can be con- 
figured as input, output, or bidirectional ports 
with handshake. (Four different handshakes 
are available.) They can also be linked to form 
a single 16-bit port. If they are not used as 
ports with handshake, they provide 16 input or 
output bits with the data direction pro- 
grammable on a bit-by-bit basis. Port B also 
provides access for Counter/Timers 1 and 2. In 
all configurations, Ports A and B can be pro- 
grammed to recognize specific data patterns 
and to generate interrupts when the pattern is 
encountered. 

The four bits of Port C provide the hand- 
shake lines f or Port s A and B when required. 
A REQUEST/WAIT line can also be provided 
so that Z-CIO transfers can be synchronized 
with DMAs or CPUs. Any P ort C b its not used 
for handshake or REQUEST/WAIT can be used 
as input or output bits (individually data direc- 
tion programmable) or external access lines for 
Counter/Timer 3. Port C does not contain any 
pattern-recognition logic. It is, however, 
capable of bit-addressable writes. With this 
feature, any combination of bits can be set 
and/or cleared while the other bits 
remain undisturbed without first reading the 
register. 

Bit Port Operations. In bit port operations, the 



port's Data Direction register specifies the 
direction of data flow for each bit. A 1 
specifies an input bit, and a specifies an out- 
put bit. If bits are used as I/O bits for a 
counter/timer, they should be set as input or 
output, as required. 

The Data Path Polarity register provides the 
capability of inverting the data path. A 1 
specifies inverting, and a specifies non- 
inverting. All discussions of the port opera- 
tions assume that the path is noninverting. 

The value returned when reading an input 
bit reflects the state of the input just prior to 
the read. A l's catcher can be inserted into the 
input data path by programming a 1 to the 
corresponding bit position of the port's Special 
I/O Control register. When a 1 is detected at 
the l's catcher input, its output is set to a 1 
until it is cleared. The l's catcher is cleared 
by writing a to the bit. In all other cases, 
attempted writes to input bits are ignored. 

When Ports A and B include output bits, 
reading the Data register returns the value 
being output. Reads of Port C return the state 
of the pin. Outputs can be specified as open- 
drain by writing a 1 to the corresponding bit of 
the port's Special I/O Control register. Port C 
has the additional feature of bit-addressable 
writes. When writing to Port C, the four most 
significant bits are used as a write protect 
mask for the least significant bits (0-4, 1-5, 
2-6, and 3-7). If the write protect bit is written 
with a 1 , the state of the corresponding output 
bit is not changed. 



287 



Functional Ports with Handshake Operation. Ports A and 
Description B can be specified as 8-bit input, output, or 
(Continued) bidirectional ports with handshake. The Z-CIO 
provides four different handshakes for its 
ports: Interlocked, Strobed, Pulsed, and 
3-Wire. When specified as a port with hand- 
shake, the transfer of data into and out of the 
port and interrupt generation is under control 
of the handshake logic. Port C provides the 
handshake lines as shown in Table 1 . Any Port 
C lines not used for handshake can be used as 
simple I/O lines or as access lines for Counter/ 
Timer 3. 

When Ports A and B are configured as ports 
with handshake, they are double-buffered. 
This allows for more relaxed interrupt service 
routine response time. A second byte can be 
input to or output from the port before the 
interrupt for the first byte is serviced. Nor- 
mally, the Interrupt Pending (IP) bit is set and 
an interrupt is generated when data is shifted 
into the Input register (input port) or out of the 
Output register (output port). For input and 
output ports, the IP is automatically cleared 
when the data is read or written. In bidirec- 
tional ports, IP is cleared only by command. 
When the Interrupt on Two Bytes (ITB) control 
bit is set to 1 , interrupts are generated only 
when two bytes of data are available to be read 
or written. This allows a minimum of 16 bits of 
information to be transferred on each inter- 
rupt. With ITB set, the IP is not automatically 
cleared until the second byte of data is read or 
written. 

When the Single Buffer (SB) bit is set to 1 , 
the port acts as if it is only single-buffered. 
This is useful if the handshake line must be 
stopped on a byte-by-byte basis. 

Ports A and B can be linked to form a 16-bit 
port by programming a 1 in the Port Link Con- 
trol (PLC) bit. In this mode, only Port A's 
Handshake Specification and Command and 
Status registers are used. Port B must be 
specified as a bit port. When linked, only Port 



A has pattern-match capability. Port B's 
pattern-match capability must be disabled. 
Also, when the ports are linked, Port B's Data 
register must be read or written before 
Port A's. 

When a port is specified as a port with hand- 
shake, the type of port it is (input, output, or 
bidirectional) determines the direction of data 
flow. The data direction for the bidirectional 
port is determined by a bit in Port C (Table 1). 
In all cases, the contents of the Data Direction 
register are ignored. The contents of the 
Special I/O Control register apply only to out- 
put bits (3-state or open-drain). Inputs may not 
have l's catchers; therefore, those bits in the 
Special I/O Control register are ignored. Port 
C lines used for handshake should be pro- 
grammed as inputs. The handshake specifica- 
tion overrides Port C's Data Direction register 
for bits that must be outputs. The contents of 
Port C's Data Path Polarity register still apply. 

Interlocked Handshake. In the Interlocked 
Handshake mode, the action of the Z-CIO must 
be acknowledged by the external device 
before the next action can take place. Figure 7 
shows timing for Interlocked Handshake. An 
output port does not indicate that new data is 
available until the external device indicates it 
is ready for the data. Similarly, an input port 
does not indicate that it is ready for new data 
until the data source indicates that the pre- 
vious byte of the data is no longer available, 
thereby acknowledging the input port's accep- 
tance of the last byte. This allows the Z-CIO to 
interface directly to the port of a Z8 microcom- 
puter, a UPC, an FIO, an FIFO, or to another 
Z-CIO port with no external logic. 

A 4-bit deske w time r can be inserted in the 
Data Available (DAV) output for output ports. 
As data is transferred to the Buffer register, 
the deskew timer is triggered. After the 
number of PCLK cycles specified by t he 
deskew timer time constant plus one, DAV is 



Port A/B Configuration PC3 PC2 PC] PCo 



Ports A and B: Bit Ports 


Bit I/O 


Bit I/O 


Bit I/O 


Bit I/O 


Port A: Input or Output Port 
(Interlocked, Strobed, or Pulsed 
Handshake) * 


RFD or DAV 


ACKIN 


REQUEST/WAIT 
or Bit I/O 


Bit I/O 


Port B: Input or Output Port 
(Interlocked, Strobed, or Pulsed 
Handshake)' 


REQUEST/WATT 
or Bit I/O 


Bit I/O 


RFD or DAV 


ACKIN 


Port A or B: Input Port (3- Wire 
Handshake) 


RFD (Output) 


DAV (Input) 


REQUEST/WAIT 
or Bit I/O 


DAC (Output) 


Port A or B: Output Port (3- Wire 
Handshake) 


DAV (Output) 


DAC (Input) 


REQUEST/WAIT 
or Bit I/O 


RFD (Input) 


Port A or B: Bidirectional Port 
(Interlocked or Strobed Handshake) 


RFD or DAV 


ACKIN 


REQUEST/WAIT 
or Bit I/O 


IN/OUT 



'Both Ports A an d B ca n be specified input or output with Interlocked, Strobed, or Pulsed Handshake at the same time if neither 
uses REQUEST/WAIT. 



Table 1. Port C Bit Utilization 



288 



Functional allowed to go Low. The deskew timer therefore 
Description guarantees that the output data is valid fo r a 
(Continued) specified minimum amount of time before DAV 
goes Low. Deskew timers are available for out- 
put ports independent of the type of handshake 
employed. 

Strobed Handshake. In the Strobed Hand- 
shake mode, data is "strobed" into or out of 
the port by the external log ic. The falling edge 
of the Acknowledge Input (ACKIN) strobes 
data into or out of the port. Figure 7 shows 
timing for the Strobed Handshake. In contrast 
to the Interlocked Handshake, the signal 
indicating the port is ready for another data 
transfer operates independently of the ACKIN 
input. It is up to the external logic to ensure 
that data overflows or underflows do not occur. 

3-Wire Handshake. The 3-Wire Handshake is 
designed for the situation in which one output 
port is communicating with many input ports 
simultaneously. It is essentially the same as the 
Interlocked Handshake, except that two signals 
are used to indicate if an input port is ready 
for new data or if it has accepted the present 
data. In the 3-Wire Handshake (Figure 8), the 
rising edge of one status line indicates that the 
port is ready for data, and the rising edge of 
another status line indicates that the data has 
been accepted. With the 3-Wire Handshake, 
the output lines of many input ports can be 
bussed together with open-drain drivers; the 



output port knows when all the ports have 
accepted the data and are ready. This is the 
same handshake as is used on the IEEE-488 
bus. Because this handshake reguires three 
lines, only one port (either A or B) can be a 
3-Wire Handshake port at a time. The 3-Wire 
Handshake is not available in the bidirectional 
mode. Because the port's direction can be 
changed under software control, however, 
bidirectional IEEE-488-type transfers can be 
performed. 

Pulsed Handshake. The Pulsed Handshake 
(Figure 9) is designed to interface to 
mechanical-type devices that reguire data to 
be held for long periods of time and need 
relatively wide pulses to gate the data into or 
out of the device. The logic is the same as the 
Interlocked Handshake mode, except that an 
internal counter/timer is linked to the hand- 
shake logic. If the port is specifie d in the input 
mode, the ti mer is in serted in the ACKIN path. 
The external ACKIN input triggers the timer 
and its output is used as the Interlocked Hand- 
shake's normal acknowledge input. If the port 
is an output por t, the timer is placed in the 
Data Available (DAV) output path. The timer is 
trigge red w hen the normal Interlocked Hand- 
shake DAV output goes Low a nd the timer out- 
put is used as the actual DAV output. The 
counter/timer maintains all of its normal 
capabilities. This handshake is not available to 
bidirectional ports. 



INPUT HANDSHAKE 



OUTPUT HANDSHAKE 



y 



DATA LATCHED 




A 



„ DESKEW fc | 
TIME ' 

STROBED 
HANDSHAKE 

NEXT BYTE 
SHIFTED FROM 
OUTPUT REGISTER TO 



Figure 7. Interlocked and Strobed 1 




Figure 8. 3-Wire Handshake 



Functional REQUEST/WAIT Line Operation. Port C can 
Description be programmed to provide a status signal out- 
(Continued) put in addition to the normal handshake lines 
for either Port A or B when used as a port with 
handshake. T he add itional signal is either a 
REQUEST or WAIT signal. The REQUEST 
signal indicates when a port is ready to per- 
form a data transfer via the Z-Bus. It is 
intend ed for use with a DMA-type device. The 
WAIT signal provides synchronization for 
transfers with a CPU. Three bits in the Port 
Handshake Specificati on regi ster provide con- 
trols for the REQUEST/WAIT logic. Because 
the extra Port C line is used, only one port can 
be specifie d as a port with a handshake and a 
REQUEST/WAIT line. The other port must be 
a bit port. 

Operation of the REQUEST line is modified 
by the state of the port's Interrupt on Two 
Bytes (ITB) control bit. When ITB is 0, the 
REQUEST line goes active as soon as the 
Z-CIO is ready for a data transfer. If ITB is 1, 
REQUEST does not go active until two bytes 
can be transferred. REQUEST stays active as 
long as a byte is available to be read or 
written. 

The SPECIAL REQUEST function is reserved 
for use with bidirectional ports only. In this 
case, the REQUEST line indicates the status of 
the register not bei ng us ed in the data path at 
that time. If the IN/OUT line is High, the 
REQUEST line is High when the Output 
register is empty. If IN/OUT is Low, the 
REQUEST line is High when the Input register 
is full. 

Pattern-Recognition Logic Operation. Both 
Ports A and B can be programmed to generate 
interrupts when a specific pattern is recog- 
nized at the port. The pattern-recognition logic 
is independent of the port application, thereby 
allowing the port to recognize patterns in all of 
its configurations. The pattern can be 
independently specified for each bit as 1 , 0, 
rising edge, falling edge, or any transition. 
Individual bits may be masked off. A pattern- 
match is defined as the simultaneous satisfac- 
tion of all nonmasked bit specifications in the 
AND mode or the satisfaction of any non- 
masked bit specifications in either of the OR or 
OR-Priority Encoded Vector modes. 



OUTPUT PORT 



Figure 9. Pulsed Handshake 



The pattern specified in the Pattern Defini- 
tion register assumes that the data path is pro- 
grammed to be noninverting. If an input bit in 
the data path is programmed to be inverting, 
the pattern detected is the opposite of the one 
specified. Output bits used in the pattern- 
match logic are internally sampled before the 
invert/noninvert logic. 

Bit Port Pattern-Recognition Operations. Dur- 
ing bit port operations, pattern- recognition 
may be performed on all bits, including those 
used as I/O for the counter/timers. The input 
to the pattern- recognition logic follows the 
value at the pins (through the invert/noninvert 
logic) in all cases except for simple inputs with 
l's catchers. In this case, the output of the l's 
catcher is used. When operating in the AND 
or OR mode, it is the transition from a no- 
match to a match state that causes the inter- 
rupt. In the "OR" mode, if a second match 
occurs before the first match goes away, it 
does not cause an interrupt. Since a match 
condition only lasts a short time when edges 
are specified, care must be taken to avoid 
losing a match condition. Bit ports specified in 
the OR-Priority Encoded Vector mode generate 
interrupts as long as any match state exists. A 
transition from a no-match to a match state is 
not required. 

The pattern-recognition logic of bit ports 
operates in two basic modes: Transparent and 
Latched. When the Latch on Pattern Match 
(LPM) bit is set to (Transparent mode), the 
interrupt indicates that a specified pattern has 
occurred, but a read of the Data register does 
not necessarily indicate the state of the port at 
the time the interrupt was generated. In the 
Latched mode (LPM= 1), the state of all the 
port inputs at the time the interrupt was gener- 
ated is latched in the input register and held 
until IP is cleared. In all cases, the PMF indi- 
cates the state of the port at the time it is read. 

If a match occurs while IP is already set, an 
error condition exists. If the Interrupt On Error 
bit (IOE) is 0, the match is ignored. However, 
if IOE is 1, after the first IP is cleared, it is 
automatically set to 1 along with the Interrupt 
Error (ERR) flag. Matches occurring while ERR 
is set are ignored. ERR is cleared when the 
corresponding IP is cleared. 

When a pattern- match is present in the 
OR-Priority Encoded Vector mode, IP is set to 
1 . The IP cannot be cleared until a match is no 
longer present. If the interrupt vector is 
allowed to include status, the vector returned 
during Interrupt Acknowledge indicates the 
highest priority bit matching its specification at 
the time of the Acknowledge cycle. Bit 7 is the 
highest priority and bit is the lowest. The bit 
initially causing the interrupt may not be the 
one indicated by the vector if a higher priority 
bit matches before the Acknowledge. Once the 
Acknowledge cycle is initiated, the vector is 



290 



Functional frozen until the corresponding IP is cleared. 
Description Where inputs that cause interrupts might 
(Continued) change before the interrupt is serviced, the l's 
catcher can be used to hold the value. 
Because a no-match to match transition is not 
required, the source of the interrupt must be 
cleared before IP is cleared or else a second 
interrupt is generated. No error detection is 
performed in this mode and the Interrupt On 
Error bit should be set to 0. 

Ports with Handshake Pattern-Recognition 
Operation. In this mode, the handshake logic 
normally controls the setting of IP and, 
therefore, the generation of interrupt requests. 
The pattern-match logic controls the Pattern 
Match Flag (PMF). The data is compared with 
the match pattern when it is shifted from the 
Buffer register to the Input register (input port) 
or when it is shifted from the Output register to 
the Buffer register (output port). The pattern- 
match logic can override the handshake logic 
in certain situations. If the port is programmed 
to interrupt when two bytes of data are 
available to be read or written, but the first 
byte matches the specified pattern, the 
pattern-recognition logic sets IP and generates 
an interrupt. While PMF is set, IP cannot be 
cleared by reading or writing the data 
registers. IP must be cleared by command. 
The input register is not emptied while IP is 
set, nor is the output register filled until IP is 
cleared. 

If the Interrupt on Match Only (IMO) bit is 
set, IP is set only when the data matches the 
pattern. This is useful in DMA- type applica- 
tions when interrupts are required only after a 
block of data is transferred. 

Counter/Timer Operation. The three 
independent 16-bit counter/timers consist of a 
presettable 16-bit down counter, a 16-bit Time 
Constant register, a 16-bit Current Counter 
register, an 8-bit Mode Specification register, 
an 8-bit Command and Status register, and the 
associated control logic that links these 
registers. 



Function 


C/Ti 


C/T 2 


C/T 3 


Counter/Timer Output 


PB 4 


PB 


PC 


Counter Input 


PB 5 


PB 1 


PC 1 


Trigger Input 


PB 6 


PB 2 


PC 2 


Gate Input 


PB 7 


PB 3 


PC 3 



Table 2. Counter/Timer External Access 

The flexibility of the counter/timers is 
enhanced by the provision of up to four lines 
per counter/timer (counter input, gate input, 
trigger input, and counter/timer output) for 
direct external control and status. Counter/ 
Timer l's external I/O lines are provided by 
the four most significant bits of Port B. 
Counter/Timer 2's are provided by the four 
least significant bits of Port B. Counter/Timer 
3's external I/O lines are provided by the four 
bits of Port C. The utilization of these lines 
(Table 2) is programmable on a bit-by-bit basis 
via the Counter/Timer Mode Specification 
registers. 

When external counter/timer I/O lines are to 
be used, the associated port lines must be 
vacant and programmed in the proper data 
direction. Lines used for counter/timer I/O 
have the same characteristics as simple input 
lines. They can be specified as inverting or 
noninverting; they can be read and used with 
the pattern-recognition logic. They can also 
include the l's catcher input. 

Counter/Timers 1 and 2 can be linked inter- 
nally in three different ways. Counter/Timer 
l's output (inverted) can be used as Counter/ 
Timer 2's trigger, gate, or counter input. 
When linked, the counter/timers have the 
same capabilities as when used separately. The 
only restriction is that when Counter/Timer 1 
drives Counter/Timer 2's count input, 
Counter/Timer 2 must be programmed with 
its external count input disabled. 

There are three duty cycles available for the 
timer/counter output: pulse, one-shot, and 
square-wave. Figure 10 shows the counter/ 



TC TC-1 TC-1 TC-2 



PULSE OUTPUT 



I OR 



J — L 



WAVE 
OUTPUT 

FIRST HALF - 



SQUARE WAVE 
OUTPUT 

SECOND HALF 



Figure 10. Counter/Timer Waveforms 



291 



Functional timer waveforms. When the Pulse mode is 
Description specified, the output goes High for one clock 
(Continued) cycle, beginning when the down-counter 

leaves the count of 1. In the One-Shot mode, 
the output goes High when the counter/timer is 
triggered and goes Low when the down- 
counter reaches 0. When the square-wave out- 
put duty cycle is specified, the counter/timer 
goes through two full sequences for each 
cycle. The initial trigger causes the down- 
counter to be loaded and the normal count- 
down sequence to begin. If a 1 count is 
detected on the down-counter's clocking edge, 
the output goes High and the time constant 
value is reloaded. On the clocking edge, when 
both the down-counter and the output are l's, 
the output is pulle d back Low. 

The Continuous/Single Cycle (C/SC) bit in 
the Mode Specification register controls opera- 
tion of the down-counter when it reaches ter- 
minal count. If C/SC is when a terminal 
count is reached, the countdown sequence 
stops. If the C/SC bit is 1 each time the count- 
down counter reaches 1 , the next cycle causes 
the time constant value to be reloaded. The 
time constant value may be changed by the 
CPU, and on reload, the new time constant 
value is loaded. 

Counter/timer operations require loading the 
time constant value in the Time Constant 
register and initiating the countdown sequence 
by loading the down-counter with the time 
constant value. The Time Constant register is 
accessed as two 8-bit registers. The registers 
are readable as well as writable, and the 
access order is irrelevant. A in the Time 
Constant register specifies a time constant of 
65,536. The down-counter is loaded in one of 
three ways: by writing a 1 to the Trigger 
Command Bit (TCB) of the Command and 
Status register, on the rising edge of the exter- 
nal trigger input, or, for Counter/Timer 2 only, 
on the rising edge of Counter/Timer l's inter- 
nal output if the counters are linked via the 
trigger input. The TCB is write-only, and read 
always returns 0. 

Once the down-counter is loaded, the count- 
down sequence continues toward terminal 
count as long as all the counter/timers' hard- 
ware and software gate inputs are High. If any 
of the gate inputs goes Low (0), the countdown 
halts. It resumes when all gate inputs are 1 
again. 

The reaction to triggers occurring during a 
countdown sequence is determined by the state 
of the Retrigger Enable Bit (REB) in the Mode 
Specification register. If REB is 0, retriggers 
are ignored and the countdown continues nor- 
mally. If REB is 1, each trigger causes the 
down-counter to be reloaded and the count- 
down sequence starts over again. If the output 



is programmed in the Square-Wave mode, 
retrigger causes the sequence to start over 
from the initial load of the time constant. 

The rate at which the down-counter counts is 
determined by the mode of the counter/timer. 
In the Timer mode (the External Count Enable 
[ECE] bit is 0), the down-counter is clocked 
internally by a signal that is half the frequency 
of the PCLK input to the chip. In the Counter 
mode (ECE is 1), the down-counter is 
decremented on the rising edge of the counter/ 
timer's counter input. 

Each time the counter reaches terminal 
count, its Interrupt Pending (IP) bit is set to 1, 
and if interrupts are enabled (IE = 1), an inter- 
rupt is generated. If a terminal count occurs 
while IP is already set, an internal error flag is 
set. As soon as IP is cleared, it is forced to a 1 
along with the Interrupt Error (ERR) flag. 
Errors that occur after the internal flag is set 
are ignored. 

The state of the down-counter can be deter- 
mined in two ways: by reading the contents of 
the down-counter via the Current Count 
register or by testing the Count In Progress 
(CIP) status bit in the Command and Status 
register. The CIP status bit is set when the 
down-counter is loaded; it is reset when the 
down-counter reaches 0. The Current Count 
register is a 16-bit register, accessible as two 
8-bit registers, which mirrors the contents of 
the down-counter. This register can be read 
anytime. However, reading the register is 
asynchronous to the counter's counting, and 
the value returned is valid only if the counter 
is stopped. The down-counter can be reliably 
read "on the fly" by the first writing of a 1 to 
the Read Counter Control (RCC) bit in the 
counter/timer's Command and Status register. 
This freezes the value in the Current Count 
register until a read of the least significant 
byte is performed. 

Interrupt Logic Operation. The interrupts 
generated by the Z-CIO follow the Z-Bus 
operation as described more fully in the Zilog 
Z-Bus Summary. The Z-CIO has five potential 
sources of interrupts: the three counter/timers 
and Ports A and B. The priorities of these 
sources are fixed in the following order: 
Counter/Timer 3, Port A, Counter/Timer 2, 
Port B, and Counter/Timer 1. Since the 
counter/timers all have equal capabilities and 
Ports A and B have equal capabilities, there is 
no adverse impact from the relative priorities. 

The Z-CIO interrupt priority, relative to 
other components within the system, is deter- 
mined by an interrupt daisy chain. Two pins, 
Interrupt Enable In (IEI) and Interrupt Enable 
Out (IEO), provide the input and output 
necessary to implement the daisy chain. When 
IEI is pulled Low by a higher priority device, 



Functional the Z-CIO cannot request an interrupt of the 
Description CPU. The following discussion assumes that 
(Continued) the IEI line is High. 

Each source of interrupt in the Z-CIO con- 
tains three bits for the control and status of the 
interrupt logic: an Interrupt Pending (IP) 
status bit, an Interrupt Under Service (IUS) 
status bit, and an Interrupt Enable (IE) control 
bit. IP is set when an event requiring CPU 
intervention occurs. T he s etting of IP results in 
forcing the Interrupt (INT) output Low, if the 
associated IE is 1 . 

The IUS status bit is set as a result of the 
Interrupt Acknowledge cycle by the CPU and 
is set only if its IP is of highest priority at the 
time the Interrupt Acknowledge commences. It 
can also be set directly by the CPU. Its 
primary function is to control the interrupt 
daisy chain. When set, it disables lower prior- 
ity sources in the daisy chain, so that lower 
priority interrupt sources do not request ser- 
vicing while higher priority devices are being 
serviced. 

The IE bit provides the CPU with a means of 
masking off individual sources of interrupts. 
When IE is set to 1 , an interrupt is generated 
normally. When IE is set to 0, the IP bit is set 
when an event occurs that wo uld normally 
require service; however, the INT output is not 
forced Low. 

The Master Interrupt Enable (MIE) bit allows 
all sources of interrupts within the Z-CIO to be 
disabled without having to individually set 
each IE to 0. If MIE is set to 0, all IPs are 
masked off and no interrupt can be requested 
or acknowledged. The Disable Lower Chain 



(DLC) bit is included to allow the CPU to 
modify the system daisy chain. When the DLC 
bit is set to 1, the Z-CIO's IEO is forced Low, 
independent of the state of the Z-CIO or its IEI 
input, and all lower priority devices' interrupts 
are disabled. 

As part of the Interrupt Acknowledge cycle, 
the Z-CIO is capable of responding with an 
8-bit interrupt vector that specifies the source 
of the interrupt. The Z-CIO contains three vec- 
tor registers: one for Port A, one for Port B, 
and one shared by the three counter/timers. 
The vector output is inhibited by setting the No 
Vector (NV) control bit to 1 . The vector output 
can be modified to include status information 
to pinpoint more precisely the cause of inter- 
rupt. Whether the vector includes status or not 
is controlled by a Vector Includes Status (VIS) 
control bit. Each base vector has its own VIS 
bit and is controlled independently. When 
MIE = 1 , reading the base vector register 
always includes status, independent of the 
state of the VIS bit. In this way, all the infor- 
mation obtained by the vector, including 
status, can be obtained with one additional 
instruction when VIS is set to 0. When 
MIE = 0, reading the vector register returns 
the unmodified base vector so that it can be 
verified. Another register, the Current Vector 
register, allows use of the Z-CIO in a polled 
environment. When read, the data returned is 
the same as the interrupt vector that would be 
output in an acknowledge, based on the 
highest priority IP set. If no unmasked IPs are 
set, the value FFh is returned. The Current 
Vector register is read-only. 



Programming Programming the Z-CIO entails loading con- 
trol registers with bits to implement the desired 
operation. Individual enable bits are provided 
for the various major blocks so that erroneous 
operations do not occur while the part is being 
initialized. Before the ports ar e enab led, IPs 
cannot be set, REQUEST and WAIT cannot be 
asserted, and all outputs remain high-impe- 
dance. The handshake lines are ignored until 
Port C is enabled. The counter/timers cannot 
be triggered until their enable bits are set. 

The Z-CIO is reset by forcing AS and DS 
Low simultaneously or by writing a 1 to the 
Reset bit. Once reset, the only thing that can 
be done is to read and write the Reset bit. 
Writes to all other bits are ignored and all 
reads return 0s. In this state, all control bits 
are forced to 0. Only after clearing the Reset 



bit (by writing to it) can the other command 
bits be programmed. 

Register Addressing. The Z-CIO allows two 
schemes for register addressing. Both schemes 
use only six of the eight bits of the address/ 
data bus. The scheme used is determined by 
the Right Justify Address (RJA) bit in the 
Master Interrupt Control register. When RJA 
equals 0, address bus bits and 7 are ignored, 
and bits 1 through 6 are decoded for the 
register address (Ao from ADj). When RJA 
equals 1 , bits through 5 are decoded for the 
register address (Ao from ADo). In the follow- 
ing register descriptions, only six bits are 
shown for addresses and represent address/ 
data bus bits through 5 or 1 through 6, 
depending on the state of the RJA bit. 



293 



Registers 



Master Interrupt Control Register 

Address: 000000 
(Read/Write) 

[qT["p.|i>,|d.|p,|d,|p, I p 1 



J 



DISABLE LOWER CHAIN (DLC) 
NO VECTOR (NV) ■ 



PORT A VECTOR INCLUDES ■ 
STATUS {PA VIS) 



L. 



Configuration Control Register 

Address: 000001 
(Read/Write) 

|b,|d.|d,|d.|d,|d,|»,|d71 



r.J 



COUNTER/TIMER 1 - 
ENABLE (CT1E) 



- RIGHT JUSTIFIED ADDRESSES 

- SHIFT LEFT (Ao from AOJ 

1 - RIGHT JUSTIFY (Ao from A Do) 

- COUNTER/TIMERS VECTOR 
INCLUDES STATUS <CT VIS) 

- PORT B VECTOR INCLUDES PORT C AND COUNTER/ ■ 
STATUS (PB VIS) TIMER 3 ENABLE 

(PCE AND CT3E) 



COUNTER/TIMER LINK 
CONTROLS (LC) 
LCI LC0 

COUNTER/TIMERS INDEPENDENT 

i arri output gates c/t 2 

1 err r» output triggers c/t 2 
1 1 crrn output is err 2-. 

COUNT INPUT 
■ PORT A ENABLE (PAE) 
PORT LINK CONTROL (PLC| 



Figure 11. Master Control Registers 



Port Mode Specification Registers 

Addresses: 100000 Port A 
101000 Port B 
(Read/Write) 



Port Handshake Specification Registers 

Addresses: 100001 Port A 
101001 Port B 
(Read/Write) 



I D, I D. I D, I 0. 1 D, j D, I D, 1 0.1 



SELECTS (PTS) 
PTS1 PTS0. 
BIT PORT 

1 INPUT PORT 

1 OUTPUT PORT 

1 1 BIDIRECTIONAL 



INTERRUPT ON TWO 
BYTES (ITB) 

SINGLE SUFFERED 



L 



j D 7 I D 6 I D, j D, j D, j D, j D, | D | 



LATCH ON PATTERN MATCH (LPM) 
(BIT MODE) 

DESKEW TIMER ENABLE (DTE) 
(HANDSHAKE MODES) 

- PATTERN MODE SPECIFICATION 
BITS (PMS) 
PMS1 PMSC 

DISABLE PATTERN MATCH 

1 "AND-MODE 



HANDSHAKE TYPE SPECIFICATION - 
BITS (HST) 

HST1 HSTO 
INTERLOCKED HANDSHAKE 

1 STROBED HANDSHAKE 

1 PULSED HANDSHAKE 

1 1 THREE-WIRE HANDSHAKE 



1 



1 



■ INTERRUPT ON MATCH ONLY (IMO) 



SPECIFICATION BITS 

(RWS) 

RWS2 RWS1 RWSO FUNCTION 

HEQUESTfWAIT DISABLED 

1 OUTPU T WA IT 

1 1 INPUT WAIT 



■ DESKEW TIME SPECIFICATION 
BITS 

SPECIFIES THE MSB's OF 
DESKEW TIMER TIME CONSTANT. 
LSB IS FORCED 1. 



Port Command and Status Registers 

Addresses: 001000 Port A 
001001 Port B 
(Read/Partial Write) 



3 



INTERRUPT UNDER 
SERVICE (IUS) 
INTERRUPT ENABLE (IE) 

INTERRUPT PENDING (IP) 



NULL CODE 
CLEAR IP & IUS 
SET IUS 
CLEAR IUS 
SET IP 
CLEAR IP 
SET IE 
CLEAR IE 



J 



• INTERRUPT ON ERROR (IOE) 



INPUT REGISTER FULL (IRF) 



Figure 12. Port Specification Registers 



294 



Registers 

(Continued) 



Data Path Polarity Registers 

Addresses: 100010 Port A 
101010 Port B 
000101 Port C (4 LSBs only) 
(Read/Write) 



|0,|0,|0.|D.|P,|P,[P,|P.| 



Data Direction Registers 

Addresses: 100011 Port A 
101011 Port B 
000110 Port C (4 LSBs only) 
(Read/Write) 

| o, | p« | p, | p. | p, | p, [ p, 1 dTl 



DATA PATH POLARITY (DPP) 

= NON-INVERTING 

1 = INVERTING 



DATA DIRECTION (DDI 



Special I/O Control Registers 

Addresses: 100100 Port A 
101100 Port B 
000111 Port C (4 LSBs only) 
(Read/Write) 

| D T | 0. | P, | D. | P, | P, j D, i P, | 



SPECIAL INPUTIOUTPUT |SIO| 

= NORMAL INPUT OR OUTPUT 

1 = OUTPUT WITH OPEN DRAIN OR 

INPUT WITH V» CATCHER 



Figure 13. Bit Path Definition Registers 



Port Data Registers 

Addresses: 001101 Port A 
001 1 10 Port B 
(Read/Write) 

|d,|d,|d,|o.|q,1d,|d,|"o7| 



Port C Data Register 

Address: 001111 
(Read/Write) 

1 p T | p. | p, | p. j n, | n a | p, | p7| 



J 



(READ RETURNS I) 



Figure 14. Port Data Registers 



Pattern Polarity Registers (PP) 

Addresses: 100101 Port A 
101101 PortB 
(Read/Write) 



Pattern Transition Registers (PT) 

Addresses: 100110 Port A 
101110 Port B 
(Read/Write) 



Pattern Mask Registers (PM) 

Addresses: 100111 Port A 
101111 PortB 
(Read/Write) 



| D, ] D, | 5 | D. | P, | D, | D, 1 D, | 



|0. D, D, P. D, D. D, D. | 
I 



PM PT PP P ATTERN SPECIFICA TION 

X BIT MASKED OFF 

1 X ANY TRANSITION 

1 ZERO 
1 1 ONE 

1 1 ONE TO-ZERO TRANSITION 0) 

1 1 1 ZERO -TO- ONE TRANSITION V) 



Figure 15. Pattern Definition Registers 



295 



Registers 

(Continued) 



Counter/Timer Command and Status Registers 

Addresses: 001010 Counter/Timer 1 
001011 Counter/Timer 2 
001 100 Counter/Timer 3 
(Read/Partial Write) 

| D, | D. | D 5 ! 0. | 0, | D, | D, | P. 1 



INTERRUPT UNDER SERVICE (IUSI 



J 



INTERRUPT ENABLE (IE) - 



NULL CODE 
CLEAR IP 4 IUS 
SET IUS 
CLEAR IUS 
SET IP 
CLEAR IP 
SET IE 
CLEAR IE 

INTERRUPT ERROR (ERR) 
(READ ONLY) 



L 



COUNT IN PROGRESS (CIP) 
(READ ONLY) 

■ TRIGGER COMMAND BIT (TCB) 
(WRITE ONLY - READ RETURNS 0) 



- READ COUNTER CONTROL (RCC) 
(READ'S ET ONLY - 

— -3CCRLSBI 



Counter/Timer Mode Specification Registers 

Addresses: 01 1 100 Counter/Timer 1 
011101 Counter/Timer 2 
011110 Counter/Timer 3 
(Read/Write) 

|d,|o,|d,|o,|o,|q,[d,|d<,| 



J 



EXTERNAL TRIGGER - 
ENABLE (ETE) 



PULSE OUTPUT 

I ONE-SHOT OUTPUT 

1 SQUARE-WAVE OUTPUT 
1 1 DO NOT SPECIFY 

RETRIGGER ENABLE BIT (REB) 

- EXTERNAL GATE ENABLE (EGEt 



Counter/Timer Current Count Registers 

Addresses: 010000 Counter/Timer l's MSB 
010001 Counter/Timer l's LSB 

010010 Counter/Timer 2's MSB 

010011 Counter/Timer 2's LSB 

010100 Counter/Timer 3's MSB 

010101 Counter/Timer 3's LSB 
(Read Only) 

| D, [ D. | D, |P, [D, [D; I 0, |P,|0, I P. [ P 5 I P. |0,jO,|D, 1"d7| 
OST ^ I — LE 



Counter/Timer Time Constant Registers 

Addresses: 010110 Counter/Timer l's MSB 
010111 Counter/Timer l's LSB 

01 1000 Counter/Timer 2's MSB 

011001 Counter/Timer 2's LSB 

011010 Counter/Timer 3's MSB 

011011 Counter/Timer 3's LSB 
(Read/Write) 

|D,|D,|D, |D, |D,|D,)D, |D,|D,|D,|D, [D, |D,|0, |D, [oTI 



Figure 16. Conter/Timer Registers 



296 



Registers 

(Continued) 



Interrupt Vector Register 

Addresses: 000010 Port A 
000011 Port B 
000100 Counter/Timers 
(Read/Write) 

| o 7 1 o. [ p, | o. [ p 3 1 p, j p, f571 
I 



Current Vector Register 

Address: 011111 
(Read Only) 

| o, | p« | a, | o. | p, [ o a | o, | oT] 

1 — INTI 



(PT VECTOR BASED 



ON HIGHEST PRIORITY 



POHT VECTOR STATUS 

PRIORITY ENCODED VECTOR MODE: 
Dj Dj 0, 

xxx NUMBER OF HIGHEST PRIORITY BIT 
WITH A MATCH 

ALL OTHER MODES: 
D3 D2 Di 



COUNTERfTIMER STATUS 



C/T 3 
CTT2 

cm 



Figure 17. Interrupt Vector Registers 



Register 
Address 



Main Control Registers 

Address* Register Name 

000000 Master Interrupt Control 

000001 Master Configuration Control 

000010 Port A's Interrupt Vector 

000011 Port B's Interrupt Vector 

000100 Counter/Timer's Interrupt Vector 

000101 Port C's Data Path Polarity 

0001 10 Port C's Data Direction 

0001 1 1 Port C's Special I/O Control 

Most Often Accessed Registers 

Address* Register Name 

001000 Port A's Command and Status 

001001 Port B's Command and Status 

001010 Counter/Timer l's Command and Status 

00101 1 Counter/Timer 2's Command and Status 

001100 Counter/Timer 3's Command and Status 

001101 Port A's Data 

001110 Port B's Data 

001111 Port C's Data 



Address* 

010000 
010001 
010010 
010011 
010100 
010101 
010110 
010111 
011000 
011001 
011010 
011011 
011100 
011101 
011110 
011111 



Counter/Timer Related Registers 

Register Name 

Counter/Timer l's Current Count-MSBs 
Counter/Timer l's Current Count-LSBs 
Counter/Timer 2's Current Count-MSBs 
Counter/Timer 2's Current Count-LSBs 
Counter/Timer 3's Current Count-MSBs 
Counter/Timer 3's Current Count-LSBs 
Counter/Timer l's Time Constant-MSBs 
Counter/Timer l's Time Constant-LSBs 
Counter/Timer 2's Time Constant-MSBs 
Counter/Timer 2's Time Constant-LSBs 
Counter/Timer 3's Time Constant-MSBs 
Counter/Timer 3's Time Constant-LSBs 
Counter/Timer l's Mode Specification 
Counter/Timer 2's Mode Specification 
Counter/Timer 3's Mode Specification 
Current Vector 



Port A Specification Registers 

Address* Register Name 

100000 Port A's Mode Specification 

100001 Port A's Handshake Specification 

100010 Port A's Data Path Polarity 

10001 1 Port A's Data Direction 

100100 Port A's Special I/O Control 

100101 Port A's Pattern Polarity 

1001 10 Port A's Pattern Transition 

1001 1 1 Port A's Pattern Mask 

Port B Specification Registers 

Address* Register Name 

101000 Port B's Mode Specification 

101001 Port B's Handshake Specification 

101010 Port B's Data Path Polarity 

101011 Port B's Data Direction 

101 100 Port B's Special I/O Control 

101 101 Port B's Pattern Polarity 

101110 Port B's Pattern Transition 

101111 Port B's Pattern Mask 



•When RIA = 0. An Irom ADj : when RJA = 1. An from ADrj 



297 



Timing Read Cycle. The CPU places an address on 

the address/data bus. The more significant bits 
and status information are combined and 
decoded by external logic to provide two Chip 
Selects (CSo and CSi). Six bits of the least 
significant byte of the address are latched 
within the Z-CIO and used to specify a Z-CIO 
register. The data from the register specified is 
strobed onto the address/d ata bus when the 
CPU issues a Data Strobe (DS). If the register 
indicated by the address does not exist, the 
Z-CIO remains high-impedance. 




S 



Figure 18. Read Cycle Timing 



Write Cycle. The CPU places an address on 
the address/data bus. The more significant bits 
and status information are combined and 
decoded by external logic to provide two Chip 
Selects (CSo and CSj). Six bits of the least 
significant byte of the address are latched 
within the Z-CIO and used to specify a Z-CIO 
register. The CPU places the data on the 
address/data bus and strobes it into the Z-CIO 
register by issuing a Data Strobe (DS). 



C«1 



y 



J- 



V ADDRESS V~ 
A MUD A 



3d 



Figure 19. Write Cycle Timing 



Interrupt Acknowledge Cycle. When one of 
the IP bits in the Z-CIO goes High an d int er- 
rupts are enabled, the Z-CIO pulls its INT 
output line Low, requesting an interrupt. The 
CPU respond s with an Interrupt Acknowledge 
cycle. When INTACK goes Low with IP set, the 
Z-CIO pulls its Interrupt Enable Out (IEO) 



Low, disabling all lower priority devices on the 
daisy chain. The CPU reads the Z-CIO inter- 
rupt vector by issuing a Low DS, thereby 
strobing the interrupt vector onto the address/ 
data bus. The IUS that corresponds to the IP is 
also set, which causes IEO to remain Low. 



y 



a r 



'INTACK is decoded from Z8000 status. 
Figure 20. Interrupt Acknowledge Timing 



298 



Absolute Voltages on all pins with respect 

Maximum to GND - 0.3V to + 7.0V 

Ratings Operating Ambient 

Temperature See Ordering Information 

Storage Temperature - 65 °C to + 150 °C 



Stresses greater than those listed under Absolute Maxi- 
mum Ratings may cause permanent damage to the device. 
This is a stress rating only; operation of the device at any 
condition above those indicated in the operational sections 
of these specifications is not implied. Exposure to absolute 
maximum rating conditions for extended periods may affect 
device reliability. 



Standard The DC characteristics and capacitance sec- 

Test tions below apply for the following standard test 

Conditions conditions, unless otherwise noted. All voltages 

are referenced to GND. Positive current flows 

into the referenced pin. 

Standard conditions are as follows: 



+ 4.75 V < V r 



+ 5.25 V 




■ GND = V 

■ Ta as specified in Ordering Information 

All ac parameters assume a load capacitance 
of 50 pf max. 

The Ordering Information section lists temper- 
ature ranges and product numbers. Package 
drawings are in the Package Information section 
in this book. Refer to the Literature List for addi- 
tional documentation. 



4 

fin nf 



Figuro 21. Standard Test Load 



Figure 22. Open-Drain Test Load 



DC 


Symbol 


Parameter 


Min Max 


Unit 


Condition 


Charac- 












teristics 


V,H 


Input High Voltage 


2.0 + 0.3 


V 






V,L 


Input Low Voltage 


-0.3 0.8 


V 






V OH 


Output High Voltage 


2.4 


V 


I OH = -250/tA 




Vol 


Output Low Voltage 


0.4 


V 


Io L = +2.0 mA 








0.5 


V 


Iql = + 3.2 mA 




% 


Input Leakage 


±10.0 


MA 


0.4 < V IN s +2.4 V 




|pL 


Output Leakage 


±10.0 


fh 


0.4 <= V OUT s +2.4 V 




'cc 


V cc Supply Current 


200 


mA 






Vqq = 5 V ± 5% unless otherwise specified, over specified temperature range. 






Capacitance 


Symbol 


Parameter 


Min Max 


Unit 


Test Condition 




C IN 


Input Capacitance 


10 


pf 






C OUT 


Output Capacitance 


IS 


Pf 






c i/o 


Bidirectional Capacitance 


20 


pf 





f = 1 MHz, over specified temperature range. 

Unmeasured pins returned to ground. 



299 



CPU 

Interlace 
Timing 









© 

> 










/ 




















i 












® — 



—I® 



- — ® — - 

®- —lh— r® 

V ADDRESS V~ ' 

4 v;i:i ° jv. 

— ® 



JRt 



CIO 

READ 



zzy. 



/ 



-®- 



DATA VALID 



® 



-ff- 



:c:: 



Interrupt 
Timing 



HATCH 
INPUT(t) 

BIT POUT 



3: 



PATTERN MATCHES 



-®- 



-®- 



-®- 



-®- 



iSt 



Interrupt 

Acknowledge 

Timing 



~ ^UNDEFINED^ - 



INTAOK 



X 



■*®» 



® r*- 




<8> 



31 



3IT\ 



300 



No. Symbol Parameter 



4 MHz 

Min Max 



6 MHz 

Min Max Notes*! 



1 TwAS AS Low Width 70 2000 50 2000 

2 TsA(AS) Address to AS I Setup Time 30 10 1 

3 ThA(AS) Address to AS I Hold Time 50 30 1 
4 — TsA(DS) Address toDS I Setup Time 180 110 1- 

5 TsCSO(AS) CSo to AS t Setup Time 5 5 1 

6 ThCSO(AS) CSo to AS t Hold Time 60 50 1 

7 TdAS(DS) AS 1 to DS I Delay 150 100 1 

8 — TsCSl(DS) CS) toDS 1 Setup Time 100 100 

9 TsRWR(DS) R/W (Read) to DS I Setup Time 100 80 

10 TsRWW(DS) R/W (Write) to DS I Setup Time 100 80 

11 TwDS DS Low Width 500 320 

12 — TsDW(DSf) Write Data toDS I Setup Time 50 45 

13 TdDS(DRV) DS (Read) 1 to Address Data Bus Driven 

14 TdDSf(DR) DS 1 to Read Data Valid Delay 460 280 

15 ThDW(DS) Write Data to DS 1 Hold Time 200 115 

16 — TdDSr(DR) DS t to Read Data Not Valid Delay 

17 TdDS(DRz) DS t to Read Data Float Delay 70 45 2 

18 ThRW(DS) R/W to DS 1 Hold Time 150 80 

19 ThCSKDS) CSj to DS I Hold Time 150 60 

20 — TdDS(AS) DS I to AS I Delay 50 25 

21 Trc Valid Access Recovery Time 1000 650 3 



22 TdPM(INT) 

23 TdACK(lNT) 
24 — TdCl(INT) — 

25 TdPC(INT) 

26 TdAS(INT) 



Pattern Match to INT Delay (Bit Port) 



ACKIN to INT Delay (Port with Handshake) 
- Counter Input to INT Delay (Counter Mode)- 
PCLK to INT Delay (Timer Mode) 
AS to INT Delay 



1+800 
4 + 600 
-1 +700- 
1 + 700 
300 



1 + 800 
4 + 600 
-1 + 700- 
1+700 



6 

4,6 
-6- 

6 



27 

28 

29 

30- 

31 

32 

33- 

34 

35 

36 



TslA(AS) 
ThlA(AS) 
TsAS(DSA) 

-TdDSA(DR)— 
TwDSA 
TdAS(IEO) 

-TdlEl(IEO) — 
TsIEKDSA) 
ThIEKDSA) 
TdDSA(lNT) 



1NTACK to AS t Setup Time 

INTACK to AS t Hold Time 250 140 

AS t to DS (Acknowledge) I Setup Time 900 580 

-DS (Acknowledge) 1 to Read Data Valid Delay 710 440- 

D§ (Acknowledge) Low Width 750 480 

AS I to IEO 1 Delay (INTACK Cycle) 430 300 

-IEI to IEO Delay 180 160- 



IEO to DS (Acknowledge) I Setup Time 
IEI to DS~(Acknowledge) t Hold Time 
DS (Acknowledge) I to INT 1 Delay 



100 
100 



70 
70 



1280 



840 



NOTES: 

1 . Parameter does not apply to Interrupt Acknowledge Iran 

factions. 

2. Float delay 15 measured to the time when the output has 
change- 0.5 V trorr, steady state with minimum ac load and 
maximum dc loac 

3. This is the delay Irom DS t o! one CIO access to DS I ol 
another CIO access. 

A. The aeiay is irom DAV i lor 3 Wire Input Handshake. The 
delay is from DAC t tor 3 Wire Output Handshake One 
oadit.cnal AS cycle is required lor ports in the Single But 
terec moq*-. 



5. The parameters lor the devices in any particular daisy 
chain mus] meet the following constraint: the delay Irom 
A3 I to DS I must be greater than the sum o! TdAS(IEO) 
lor the highest priority peripheral, T'sIEIiDSA) for the 
lowest priority peripheral, and TdlEI'IEOl for each 
peripheral separating them in the chain. 

6. Units equal to A3 cycle + ns. 

' Timings ere preliminary and subtect to change. 
T Units in nanoseconds(ns). eicept as noted 

7. The A3 (unctions as the dock to the 8036 H A3 strobe 
stops, then data does not get docked through the 
device. A3 cycle functions similar to a dock cycle, 
following AS timing specifications. Refer to 7-1 ol the 
Technical Manual. 



301 



4 MHz 6 MHz 

No. Symbol Parameter Min Max Min Max Notes't 



1 TsDI(ACK) Data Input to ACKIN i Setup Time 

2 ThDI(ACK) Data Input to ACKIN I Hold Time - Strobed 500 330 

Handshake 



3 TdACKf(RFD) ACKIN I to RFD 1 Delay 
4 TwACKl ACKIN Low Width - Strobed Handshake 250 165- 



14 TdDAVr(ACK) DAV 1 to ACKIN 1 (RFD t ) - Interlocked and 
3-Wire Handshake 



5 TwACKh ACKIN High Width - Strobed Handshake 250 165 



6 TdRFDr(ACK) RFD 1 to ACKIN 1 Delay 

7 TsDO(DAV) Data Out to DAV 1 Setup Time 25 20 1 

8 TdDAVf(ACK) DAV I to ACKIN I Delay 

9 ThDO(ACK) Data Out to ACKIN 1 Hold Time 1 1 2- 



10 TdACK(DAV) ACKIN 1 to DAV I Delay 1 1 2 

1 1 ThDI(RFD) Data Input to RFD I Hold Time - Interlocked 

Handshake 



12 TdRFDf(ACK) RFD 1 to ACKIN 1 Delay - Interlocked Handshake 

13 — TdACKr(RFD) — ACKIN I (DAV I ) to RFD t Delay - Interlocked' — - 

and 3-Wire Handshake 



15 TdACK(DAV) ACKIN t (RFD t )to DAV I Delay - Interlocked and 
3-Wire Handshake 

16 TdDAVIf(DAC)— DAV 1 to DAC I Delay - Input 3-Wire Handshake 

17 ThDI(DAC) Data Input to DAC t Hold Time - 3-Wire 

Handshake 

18 TdDACOr(DAV) DAC t to DAV t Delay - Input 3-Wire Handshake 

19 TdDAVIr(DAC) DAV t to DAC 1 Delay - Input 3-Wire Handshake 

20 TdDAVOf(DAC)-DAV 1 to DAC I Delay - Output 3-Wire Handshake 

21 ThDO(DAC) Data Output to DAC 1 Hold Time - 3-Wire 1 1 2 

Handshake 

22 TdDACIr(DAV) DAC 1 to DAV t Delay - Output 3-Wire Handshake 1 1 2 

23 TdDAVOr(DAC) DAV t to DAC 1 Delay - Output 3-Wire Handshake 

NOTES: 

1 . This time can be extended through the use of the deskew * Timings are preliminary and subject to change. All timing 

timers. references assume 2.0 V for a logic "1" and 0.8 V for a logic "0" 

2 Units equal to AS cycle. t Units in nanoseconds (ns). except as noted. 



303 




No. Symbol 



Parameter 



4 MHz 

Min Max 



6 MHz 
Min Max 



Notes*t 



1 
2 
3 
4 
5 

6- 

7 

8 

9 
10 
11- 



TcPC 

TwPCh 

TwPCl 

TfPC 

TrPC 

-TcCI 

TCIh 

TwCIl 

TfCI 

TrCI 
-TsTI(PC)- 



12 TsTI(CI) 

13 TwTI 

14 — TsGI(PC)- 

15 TsGI(CI) 

16 ThGI(PC) 

17 — ThGI(CI) — 

18 TdPC(CO) 

19 TdCI(CO) 



PCLK Cycle'Time 

PCLK High Width 

PCLK Low Width 

PCLK Fall Time 

PCLK Rise Time 

-Counter Input Cycle Time 

Counter Input High Width 

Counter Input Low Width 

Counter Input Fall Time 

Counter Input Rise Time 

-Trigger Input to PCLK I Setup Time 

(Timer Mode) 

Trigger Input to Counter Input 1 Setup 
Time (Counter Mode) 

Trigger Input Pulse Width (High or Low) 

-Gate Input to PCLK 1 Setup Time 

(Timer Mode) 

Gate Input to Counter Input 1 Setup 
Time (Counter Mode) 

Gate Input to PCLK 1 Hold Time (Timer 
Mode) 

-Gate Input to Counter Input I Hold 

Time (Counter Mode) 

PCLK to Counter Output Delay (Timer 
Mode) 

Counter Input to Counter Output Delay 
(Counter Mode) 



250 4000 
140 2000 
105 2000 
10 
10 

-500 

230 
230 

20 
20 



-150 • 

150 

200 
-100 

100 

100 

-100 



475 
475 



165 4000 
75 2000 
70 2000 
10 
15 

-330 

150 
150 

15 
15 



-120- 

100 

130 
-100- 

80 

70 

-70- 



320 
420 



NOTES: 

1. PCLK is only used with the counte r/time rs (in Timer mode), the 
deskew timers, and the REQUEST/WAIT logic. II these func- 
tions are not used, the PCLK input can be held low. 

2. These parameters must be met to guarantee that trigger or gate 



are valid lor the next counter/timer cycle. 
* Timings are preliminary and subject to change. All timing refer- 
ences assume 2.0 V for a logic "I" and 0.8 V lor a logic "0". 
t Units in nanoseconds (ns). 



304 




No. 


Symbol 


Parameter 


4 MHz 

Min Max 


6 MHz 
Min Max 


Notes't 


1 


TdDS(REQ) 


DS~I to REQ 1 Delay 


500 


450 




2 


TdDS(WAIT) 


DS~I to WAIT 1 Delay 


500 


450 




3 


TdPC(REQ) 


PCLK 1 to REQ 1 Delay 


300 


320 




4 


TdPC(WAIT) 


PCLK 1 to WAIT 1 Delay 


300 


300 




5 


TdACK(REQ) 


ACKIN 1 to REQ I Delay 


3 + 2 


3 + 2 










+ 1000 


+ 9000 


1.2 


6 


TdACK(WAIT) 


ACKIN 1 to WAIT 1 Delay 


10 + 600 


10 + 500 


3 



NOTES: 3. Unils equal to PCLK cycles + ns. 

J The Delay u lrom DAV I for the 3- Wire Input Handshake. The * Timings are preliminary and subiect to change. All timing reier- 

de.ay is lrom DAC t for the 3-Wire Output Handshake. ences assume 2.0 V lor a logic "1" and 0.8 V (or a logic "0". 

2. Un:ts equa. to AS cycles + PCLK cycles ■% ns. T Units m nanoseconds (ns), except as noted 



Reset 
Timing 




No. 


Symbol 


Parameter 


4 MHz 

Min Max 


6 MHz 
Min Max 


Notes*t 


1 


TdDSQ(AS) 


Delay lrom DS t to AS I for No Reset 


40 


15 




2 


TdASQ(DS) 


Delay from AS 1 to DS 1 for No Reset 


50 


30 




3 


TwRES 


Minimum Width of AS and DS both Low for Reset 


250 


170 


1 



NOTES: * Timings are preliminary and subiect to chanoe. All timing refer- 

1. Interna) circutry allows for the reset provided by the Z8 (DS ences assume 2.0 V lor a logic "1" and 0.8 V ior a logic "0". 

held Low wh.ie A~S pulses) to be suliicient. 1 Units in nanoseconds (ns). 



305 



Miscellaneous 

Port 

Timing 



1'« CATCHER 
INPUT 



y_ 



X 





4 






PATTERN MATCHES 


< 


©- 




\* (<> ► 






t I 


< 









4 MHz 


6 MHz 




No. 


Symbol 


Parameter 


Min Max 


Min 


Max 


Notes*t 


1 


TrI 


Any Input Rise Time 


100 




100 




2 


Tfl 


Any Input Fall Time 


100 




100 




3 


Twl's 


l's Catcher High Width 


250 


170 




1 


4 


TwPM 


Pattern Match Input Valid (Bit Port) 


750 


500 






5 


TsPMD 


Data Latched on Pattern Match Setup Time (Bit Port) 












6 


ThPMD 


Data Latched on Pattern Match Hold Time (Bit Port) 


1000 


650 







NOTES: 

1 . Ii the input is programmed inverting, a Low-going pulse of the 
same width will be detected. 



* Timings are preliminary and subject to change. All timing refer- 
ences assume 2.0 V for a logic "1" and 0.8 V for a logic "0", 
T Units in nanoseconds (ns). 



Bidirectional 

Port 

Timing 



J 



7 



-©- 



-CD- 

















/ 


1 \ 

— © 4 




"* — © — * 





No. 


Symbol 


Parameter 


4 MHz 

Min Max 


6 MHz 
Min Max 


Notes*t 


1 


TdlOr(DAV) 


I/O I to RFD/DAV High Delay 


500 


500 




2 


TdlOr(DRZ) 


I/O t to Data Float Delay 


500 


500 




3 


TdlOr(ACK) 


I/O t to ACKIN 1 Delay 






2 


4 


TdlOf(RFD) 


I/O 1 to RFD/DAV High Delay 


500 


500 V 




5 


TdlOf(DAV) 


I/O 1 to RFD/DAV 1 Delay 


3 


3 


1 


6 


TdDO(IO) 


I/O 1 to Data Bus Driven 


2 


2 


1 



NOTES: _ 

1, Units equal to AS cycles^ 

2. Minimum delay is four AS cycles or one AS cycle alter the cor- 
responding IP is cleared, whichever is lonqer. 



Timings are preliminary and subject to change. All timing 
relerences assume 2.0 V tor a logic "1" and 8 V lor a logic "0". 
T Units m nanoseconds (ns). 



306 



Zilog 



Z8536 CIO 
Counter/Timer and 
Parallel I/O Unit 



October 1988 



Features ■ Two independent 8-bit, double-buffered, 

bidirectional I/O ports plus a 4-bit 
special-purpose I/O port. I/O ports 
feature programmable polarity, 
programmable direction (Bit mode), "pulse 
catchers," and programmable open- 
drain outputs. 

■ Four handshake modes, including 3- Wire 
(like the IEEE-488). 



REQUEST/WAIT signal for high-speed data 
transfer. 



Flexible pattern-recognition logic, program- 
mable as a 16-vector interrupt controller. 

Three independent 16-bit counter/timers 
with up to four external access lines per 
counter/timer (count input, output, gate, 
and trigger), and three output duty cycles 
(pulsed, one-shot, and square-wave), 
programmable as retriggerable or 
nonretriggerable . 

Easy to use since all registers are 
read/write. 



(II 
W 

o 



General The Z8536 CIO Counter/Timer and 

Description Parallel I/O element is a general-purpose 
peripheral circuit, satisfying most counter/ 
timer and parallel I/O needs encountered in 
system designs. This versatile device contains 
three I/O ports and three counter/timers. Many 
programmable options tailor its configuration 
to specific applications. The use of the device 
is simplified by making all internal registers 



(command, status, and data) readable and 
(except for status bits) writable. In addition, 
each register is given its own unique internal 
address, so that any register can be accessed 
in two operations. All data registers can be 
directly accessed in a single operation. The 
CIO is easily interfaced to all popular 
microprocessors. 



INTERRUPT 



0, 


PA. 


D« 


PA, 


D| 


PA S 


Da 


PA., 


Ol 


PA, 


»2 


PA, 


Ol 


PA, 


Do 


PA., 


WR 


PC, 


no 2853a 


PC, 


A, CIO 


PC, 


Ao 


PC, 


CE 


PB, 


INT 


ps, 


INTACK 


P3 S 


IEI 


PS, 


IE0 


PB, 




P8, 
PB, 

p B 



t 1 1 



PCLK + 5V GND 

Figure 1. Pin Functions 









« 


3°. 


">L 


2 




JS 


3* 


°.C 


,* 




3H 


J°1 


°>C 






37 


J DO 


SBC 






» 


]CE 


mQ 


« 




35 


]A, 








34 


]». 


PBoE 


• 




33 


]PA„ 


PB, £ 


9 




12 


] PA, 


PBjC 
PB,C 


1D 
11 


Z6S36 
CIO 


31 
30 


2 PA! 
J PA, 


PB.C 


12 




2S 


DPA. 


PB S C 


'» 




28 


J PA, 


PB.C 


14 




27 


]PA« 


PB,C 


* 




26 


]PA, 


PCLKfJ 


1. 




25 


] INTACK 


mC 


» 




2a 


INT 




18 




23 


] +5 V 


PC.C 


15 




22 




pc,C 


20 




21 


JPCj 



Figure 2a. 40-pin Dual-In-Line Package (DIP). 
Pin Assignments 



307 



<^ ^ o A <f° & O h <>"> O a O*- 0° 1 



NC 
GND 
PB 
PBi 
PB 2 
PB 3 
PB„ 
PBs 
PB 6 
PB 7 



6 5 4 3 2 1 44 43 42 41 40 



Z8S36 
CIO 



18 19 20 21 22 23 24 25 26 27 21 



\ 




39 


A, 


33 


AO 


37 


PA,, 


36 


PA, 


35 


PA, 


34 


PA 3 


33 


PA, 


32 


PA'. 


31 


PA 6 


30 


PA, 


29 


NC 


/ 





Figure 2b. 44-pin Chip Carrier, 
Pin Assignments 



Pin Ao-A]. Address Lines (input). These two lines 

Description are used to select the register involved in the 
CPU transaction: Port A's Data register, Port 
B's Data register, Port C's Data register, or a 
control register. 

CE. Chip Enable (input, active Low). A Low 
level on this input enables the CIO to be read 
from or written to. 

D0-D7. Data Bus (bidirectional 3-state). These 
eight data lines are used for transfers between 
the CPU and the CIO. 

IEI. Interrupt Enable In (input, active High). 
IEI is used with IEO to form an interrupt daisy 
chain when there is more than one interrupt- 
driven device. A High IEI indicates that no 
other higher priority device has an interrupt 
under service or is reguesting an interrupt. 

IEO. Interrupt Enable Out (output, active 
High). IEO is High only if IEI is High and the 
CPU is not servicing an interrupt from the 
reguesting CIO or is not requesting an inter- 
rupt (Interrupt Acknowledge cycle only). IEO 
is connected to the next lower priority device's 
IEI input and thus inhibits interrupts from 
lower priority devices. 

INT. Interrupt Request (output, open-drain, 
active Low). This signal is pulled Low when 
the CIO requests an interrupt. 



INTACK. Interrupt Acknowledge (input, active 
Low). This input indicates to the CIO that an 
Interrupt Acknowledge cycle is in progress. 
INTACK must be synchronized to PCLK, and 



it must be stable throughout the Interrupt 
Acknowledge cycle. 

PA0-PA7. Port A I/O lines (bidirectional, 
3-state, or open-drain). These eight I/O lines 
transfer information between the CIO's Port A 
and external devices. 

PB0-PB7. Port B I/O lines (bidirectional, 
3-state, or open-drain). These eight I/O lines 
transfer information between the CIO's Port B 
and external devices. May also be used to 
provide external access to Counter/Timers 
1 and 2. 

PC0-PC3. Port C I/O lines (bidirectional, 
3-state, or open-drain). These f our I/O lines 
are used to provide handshake, WAIT, and 
REQUEST lines for Ports A and B or to provide 
external access to Counter/Timer 3 or access 
to the CIO's Port C. 

PCLK. Peripheral Clock (input, TTL- 
compatible). This is the clock used by the 
internal control logic and the counter/timers 
in timer mode. It does not have to be the 
CPU clock. 

HD*. Read (input, active Low). This signal 
indicates that a CPU is reading from the CIO. 
During an Interrupt Acknowledge cycle, this 
signal gates the interrupt vector onto the data 
bus if the CIO is the highest priority device 
requesting an interrupt. 

WH*. Write (input, active Low). This signal 
indicates a CPU write to the CIO. 

"When RD and WR are detected Low at the same time {normally 
an illegal condition), the CIO is reset. 



308 



Architecture The CIO Counter/Timer and Parallel I/O 

element (Figure 3) consists of a CPU interface, 
three I/O ports (two general-purpose 8-bit 
ports and one special-purpose 4-bit port), 
three 16-bit counter/timers, an interrupt- 



control logic block, and the internal-control 
logic block. An extensive number of program- 
mable options allow the user to tailor the con- 
figuration to best suit the specific application. 



1 INTERRUPT v 



INTERRUPT 
CONTROL 
LOGIC 



INTERNAL BUS 



i UAIA BUb . 



INTERNAL 
CONTROL 
LOGIC 



\ COUNTER* / \ 

y> TIMER 3 ^ ^ 



~\ COUNTER/ \ 

__/ TIMER 2 J 

~~\ COUNTER/ \ 

) TIMER 1 J 



C=E^> 

' PORT A r 



1 PORT C ' 



N PORT B ' 



FIgur* 



3. CIO Block Diagram 



Architecture 

(Continued) 



TO COUNTER/TIMERS 1 AND 2 
(PORT S ONLY) 



OUTPUT 
DATA 
REGISTER 



PATTERN 
RECOGNITION 
LOGIC 



INPUT 
DATA 
REGISTER 



\f DATA A 

\ MULTIPLEXER / 



POUT 
CONTROL 
LOGIC A HANDSHAKE CONTROL 



INPUT 
BUFFER/ 
INVERTERS 
AND 



OUTPUT 
BUFFER/ 
INVERTERS 



Figure 4. Porta A and B Block Diagram 



The two general-purpose 8-bit I/O ports 
(Figure 4) are identical, except that Port B can 
be specified to provide external access to 
Counter/Timers 1 and 2. Either port can be 
programmed to be a handshake-driven, 
double-buffered port (input, output, or bidirec- 
tional) or a control-type port with the direction 
of each bit individually programmable. Each 
port includes pattern-recognition logic, allow- 
ing interrupt generation when a specific pat- 
tern is detected. The pattern-recognition logic 
can be programmed so the port functions like 
a priority-interrupt controller. Ports A and B 
can also be linked to form a 16-bit I/O port. 

To control these capabilities, both ports con- 
tain 12 registers. Three of these registers, the 
Input, Output, and Buffer registers, comprise 
the data path registers. Two registers, the 
Mode Specification and Handshake Specifica- 
tion registers, are used to define the mode of 
the port and to specify which handshake, if 
any, is to be used. The reference pattern for 
the pattern-recognition logic is defined via 
three registers: the Pattern Polarity, Pattern 
Transition, and Pattern Mask registers. The 
detailed characteristics of each bit path (for 



example, the direction of data flow or whether 
a path is inverting or noninverting) are pro- 
grammed using the Data Path Polarity, Data 
Direction, and Special I/O Control registers. 

The primary control and status bits are 
grouped in a single register, the Command 
and Status register, so that after the port is ini- 
tially configured, only this register must be ac- 
cessed frequently. To facilitate initialization, 
the port logic is designed so that registers 
associated with an unrequired capability are 
ignored and do not have to be programmed. 

The function of the special-purpose 4-bit 
port, Port C (Figure 5), depends upon the 
roles of Ports A and B. Port C provides the 
required handshake lines. Any bits of Port C 
not used as handshake lines can be used as 
I/O lines or to provide external access for the 
third counter/timer. 

Since Port C's function is defined primarily 
by Ports A and B, only three registers (besides 
the Data Input and Output registers) are 
needed. These registers specify the details of 
each bit path: the Data Path Polarity, Data 
Direction, and Special I/O Control registers. 



310 



2014-005 



Architecture 

(Continued) 



A B 



OUTPUT 

DATA 
REGISTER 



HANDSHAKE 
AND 
REQUEST/WAIT 
LOGIC 




4 





INPUT 
DATA 
REGISTER 



INPUT 
BUFFER/ 
INVERTERS 
AND 



PORT 
CONTROL 
LOGIC 



/ J pNi 

\ l co 



OUTPUT 
BUFFER! 
INVERTERS 



Figure 5. Port C Block Diagram 



The three counter/timers (Figure 6) are all 
identical. Each is comprised of a 16-bit down- 
counter, a 16-bit Time Constant register 
(which holds the value loaded into the down- 
counter), a 16-bit Current Count register (used 
to read the contents of the down-counter), and 
two 8-bit registers for control and status (the 
Mode Specification and the Command and 
Status registers). 

The capabilities of the counter/timer are 
numerous. Up to four port I/O lines can be 
dedicated as external access lines for each 
counter/timer: counter input, gate input, trig- 
ger input, and counter/timer output. Three dif- 
ferent counter/timer output duty cycles are 
available: pulse, one-shot, or square-wave. 



The operation of the counter/timer can be pro- 
grammed as either retriggerable or nonretrig- 
gerable. With these and other options, most 
counter/timer applications are covered. 

There are five registers (Master Interrupt 
Control register, three Interrupt Vector 
registers, and the Current Vector register) 
associated with the interrupt logic. In addition, 
the ports' Command and Status registers and 
the counter/timers' Command and Status 
registers include bits associated with the inter- 
rupt logic. Each of these registers contains 
three bits for interrupt control and status: 
Interrupt Pending (IP), Interrupt Under Ser- 
vice (IUS), and Interrupt Enable (IE). 



2014-006 



311 



Architecture 

(Continued) 



TIME 
CONSTANT 
REGISTER 
(MSBs) 


=5 


16-BIT 


^> 


CURRENT 
COUNT 

REGISTER 
(MSBs) 






DOWN 
COUNTER 






TIME 








CURRENT 


CONSTANT 
REGISTER 


=> 




^> 


COUNT 
REGISTER 


(LSB») 








(LSBs) 



COUNTER/ 
TIMER 

CONTROL 
LOGIC 



— 1 C( 
I Ul 



Figure 6. Counter/Timer Block Diagram 



Functional The following describes the functions 

Description of the ports, pattern-recognition logic, 
counter/timers, and interrupt logic. 

I/O Port Operations. Of the CIO's three I/O 
ports, two (Ports A and B) are general- 
purpose, and the third (Port C) is a special- 
purpose 4-bit port. Ports A and B can be con- 
figured as input, output, or bidirectional ports 
with handshake. (Four different handshakes 
are available.) They can also be linked to form 
a single 16-bit port. If they are not used as 
ports with handshake, they provide 16 input or 
output bits with the data direction program- 
mable on a bit-by-bit basis. Port B also pro- 
vides access for Counter/Timers 1 and 2. In all 
configurations, Ports A and B can be pro- 
grammed to recognize specific data patterns 
and to generate interrupts when the pattern is 
encountered. 

The four bits of Port C provide the hand- 
shake lines f or Port s A and B when reguired. 
A REQUEST/WAIT line can also be provided 
so that CIO transfers can be synchronized with 
DMAs or CPUs. Any Por t C bit s not used for 
handshake or REQUEST/WAIT can be used as 
input or output bits (individually data-direction 
programmable) or external access lines for 
Counter/Timer 3. Port C does not contain any 
pattern-recognition logic. It is, however, 
capable of bit-addressable writes. With this 
feature, any combination of bits can be set 
and/or cleared while the other bits remain 
undisturbed without first reading the register. 

Bit Port Operations. In bit port operations, the 



port's Data Direction register specifies the 
direction of data flow for each bit. A 1 
specifies an input bit, and a specifies an out- 
put bit. If bits are used as I/O bits for a 
counter/timer, they should be set as input or 
output, as reguired. 

The Data Path Polarity register provides the 
capability of inverting the data path. A 1 
specifies inverting, and a specifies non- 
inverting. All discussions of the port opera- 
tions assume that the path is noninverting. 

The value returned when reading an input 
bit reflects the state of the input just prior to 
the read. A l's catcher can be inserted into the 
input data path by programming a 1 to the 
corresponding bit position of the port's Special 
I/O Control register. When a 1 is detected at 
the l's catcher input, its output is set to 1 until 
it is cleared. The l's catcher is cleared 
by writing a to the bit. In all other cases, 
attempted writes to input bits are ignored. 

When Ports A and B include output bits, 
reading the Data register returns the value 
being output. Reads of Port C return the state 
of the pin. Outputs can be specified as open- 
drain by writing a 1 to the corresponding bit of 
the port's Special I/O Control register. Port C 
has the additional feature of bit-addressable 
writes. When writing to Port C, the four most 
significant bits are used as a write protect 
mask for the least significant bits (0-4, 1-5, 
2-6, and 3-7). If the write protect bit is written 
with a 1 , the state of the corresponding output 
bit is not changed. 



312 



2014-007 



Functional Ports with Handshake Operation. Ports A and 
Description B can be specified as 8-bit input, output, or 
(Continued) bidirectional ports with handshake. The CIO 
provides four different handshakes for its 
ports: Interlocked, Strobed, Pulsed, and 
3- Wire. When specified as a port with hand- 
shake, the transfer of data into and out of the 
port and interrupt generation is under control 
of the handshake logic. Port C provides the 
handshake lines as shown in Table 1 . Any Port 
C lines not used for handshake can be used as 
simple I/O lines or as access lines for 
Counter/Timer 3. 

When Ports A and B are configured as ports 
with handshake, they are double-buffered. 
This allows for more relaxed interrupt service 
routine response time. A second byte can be 
input to or output from the port before the 
interrupt for the first byte is serviced. Nor- 
mally, the Interrupt Pending (IP) bit is set and 
an interrupt is generated when data is shifted 
into the Input register (input port) or out of the 
Output register (output port). For input and 
output ports, the IP is automatically cleared 
when the data is read or written. In bidirec- 
tional ports, IP is cleared only by command. 
When the Interrupt on Two Bytes (ITB) control 
bit is set to 1 , interrupts are generated only 
when two bytes of data are available to be read 
or written. This allows a minimum of 16 bits of 
information to be transferred on each inter- 
rupt. With ITB set, the IP is not automatically 
cleared until the second byte of datais read 
or written. 

When the Single Buffer (SB) bit is set to 1, 
the port acts as if it is only single-buffered. 
This is useful if the handshake line must be 
stopped on a byte-by-byte basis. 

Ports A and B can be linked to form a 16-bit 
port by programming a 1 in the Port Link Con- 
trol (PLC) bit. In this mode, only Port A's 
Handshake Specification and Command and 
Status registers are used. Port B must be 
specified as a bit port. When linked, only Port 
A has pattern-match capability. Port B's 



pattern-match capability must be disabled. 
Also, when the ports are linked, Port B's Data 
register must be read or written before 
Port A's. 

When a port is specified as a port with hand- 
shake, the type of port it is (input, output, or 
bidirectional) determines the direction of data 
flow. The data direction for the bidirectional 
port is determined by a bit in Port C (Table 1). 
In all cases, the contents of the Data Direction 
register are ignored. The contents of the 
Special I/O Control register apply only to out- 
put bits (3-state or open-drain). Inputs may not 
have l's catchers; therefore, those bits in the 
Special I/O Control register are ignored. Port 
C lines used for handshake should be pro- 
grammed as inputs. The handshake specifica- 
tion overrides Port C's Data Direction register ^ 
for bits that must be outputs. The contents of 00 
Port C's Data Path Polarity register still apply. 

Interlocked Handshake. In the Interlocked 0) 
Handshake mode, the action of the CIO must O 
be acknowledged by the external device Q 
before the next action can take place. Figure 7 
shows timing for Interlocked Handshake. An 
output port does not indicate that new data is 
available until the external device indicates it 
is ready for the data. Similarly, an input port 
does not indicate that it is ready for new data 
until the data source indicates that the 
previous byte of the data is no longer 
available, thereby acknowledging the input 
port's acceptance of the last byte. This allows 
the CIO to interface directly to the port of a Z8 
microcomputer, a UPC, an FIO, an FIFO, or 
to another CIO port with no external logic. 

A 4-bit deske w time r can be inserted in the 
Data Available (DAV) output for output ports. 
As data is transferred to the Buffer register, 
the deskew timer is triggered. After the 
number of PCLK cycles specified by the 
deskew timer time constant plus one, DAV is 
allowed to go Low. The deskew timer therefore 
guarantees that the output data is valid for a 
specified minimum amount of time before DAV 



Port A/B Configuration PC 3 PCj PC] PCrj 



Ports A and B: Bit Ports 


Bit I/O 


Bit I/O 


Bit I/O 


Bit I/O 


Port A: Input or Output Port 
(Interlocked, Strobed, or Pulsed 
Handshake)' 


RFD or DAV 


ACKIN 


REQUEST/WAIT 
or Bit I/O 


Bit I/O 


Port B: Input or Output Port 
(Interlocked, Strobed, or Pulsed 
Handshake)" 


REQUEST/WAIT 
or Bit I/O 


Bit I/O 


RFD or DAV 


ACKIN 


Port A or B: Input Port (3- Wire 
Handshake) 


RFD (Output) 


DAV (Input) 


REQUEST/WAIT 
or Bit I/O 


DAC (Output) 


Port A or B: Output Port (3-Wire 
Handshake) 


DAV (Output) 


DAC (Input) 


REQUEST/WAIT 
or Bit I/O 


RFD (Input) 


Port A or B: Bidirectional Port 
(Interlocked or Strobed Handshake) 


RFD or DAV 


ACKIN 


REQUEST/WAIT 
or Bit I/O 


IN/OUT 



'Both Ports A and B can be specified input or output with Interlocked, Strobed, or Pulsed Handshake at the same time if neither uses 
REQUEST/WAIT. 

Table I. Port C Bit Utilization 



313 



Functional goes Low. Deskew timers are available for out- 
Description put ports independent of the type of handshake 
(Continued) employed. 

Strobed Handshake. In the Strobed Hand- 
shake mode, data is "strobed" into or out of 
the port by the external log ic. The falling edge 
of the Acknowledge Input (ACKIN) strobes 
■ data into or out of the port. Figure 7 shows 
timing for the Strobed Handshake. In contrast 
to the Interlocked handshake, the signal 
indicating the port is ready for another data 
transfer operates independently of the ACKIN 
input. It is up to the external logic to ensure 
that data overflows or underflows do not occur. 

3-Wire Handshake. The 3- Wire Handshake is 
designed for the situation in which one output 
port is communicating with many input ports 
simultaneously. It is essentially the same as the 
Interlocked Handshake, except that two signals 
are used to indicate if an input port is ready 
for new data or if it has accepted the present 
data. In the 3-Wire Handshake (Figure 8), the 
rising edge of one status line indicates that the 
port is ready for data, and the rising edge of 
another status line indicates that the data has 
been accepted. With the 3-Wire Handshake, 
the output lines of many input ports can be 
bussed together with open-drain drivers; the 
output port knows when all the ports have 
accepted the data and are ready. This is the 



same handshake as is used on the IEEE-488 
bus. Because this handshake reguires three 
lines, only one port (either A or B) can be a 
3-Wire Handshake port at a time. The 3-Wire 
. Handshake is not available in the bidirectional 
mode. Because the port's direction can be 
changed under software control, however, 
bidirectional IEEE-488-type transfers can be 
performed. 

Pulsed Handshake. The Pulsed Handshake 
(Figure 9) is designed to interface to 
mechanical-type devices that require data to 
be held for long periods of time and need 
relatively wide pulses to gate the data into or 
out of the device. The logic is the same as the 
Interlocked Handshake mode, except that an 
internal counter/timer is linked to the hand- 
shake logic. If the port is specifie d in the input 
mode, the ti mer is in serted in the ACKIN path. 
The external ACKIN input triggers the timer 
and its output is used as the Interlocked Hand- 
shake's normal acknowledge input. If the port 
is an output por t, the timer is placed in the 
Data Available (DAV) output path. The timer is 
trigge red w hen the normal Interlocked Hand- 
shake DAV output goes Low a nd the timer out- 
put is used as the actual DAV output. The 
counter/timer maintains all of its normal 
capabilities. This handshake is not available to 
bidirectional ports. 



INPUT HANDSHAKE 



OUTPUT HANDSHAKE 





\ \ 

/ 

STROBED 
HANDSHAKE 
NEXT BYTE 
SHIFTED FROM 
OUTPUT REGISTER TO 
BUFFER REGISTER 



Figure 7. Interlocked and Strobed Handshakes 



INPUT HANDSHAKE 



OUTPUT HANDSHAKE 




DATA ) 


^ NEXT BYTE 


„ D LASTONE^y 

INPUT J 
LAST ONE 


^~ 


INPUT ^\ \ 


( LAST 

\ ONE *Kf 




DESKEW L- \ 
TIME r*y 


DAV L/ 

OUTPUT l / 


X 



NEXT BYTE 
SHIFTED FROM 
OUTPUT REGISTER TO 
BUFFER REGISTER 



Figure 8. 3-Wire Handshake 



314 



2014-008,009 



Functional REQUEST/WAIT Line Operation. Port C can 
Description be programmed to provide a status signal out- 
continued) put in addition to the normal handshake lines 
for either Port A or B when used as a port with 
handshake. T he add itional signal is either a 
REQUEST or WAIT signal. The REQUEST 
signal indicates when a port is ready to per- 
form a data transfer via the CPU interface. It is 
intend ed for use with a DMA-type device. The 
WAIT signal provides synchronization for 
transfers with a CPU. Three bits in the Port 
Handshake Specificati on regi ster provide con- 
trols for the REQUEST/WAIT logic. Because 
the extra Port C line is used, only one port can 
be specifie d as a port with a handshake and a 
REQUEST/WAIT line. The other port must be 
a bit port. 

Operation of the REQUEST line is modified 
by the state of the port's Interrupt on Two 
Bytes (ITB) control bit. When ITB is 0, the 
REQUEST line goes active as soon as the CIO 
is ready for a data transfer. If ITB is 1 , 
REQUEST does not go active until two bytes 
can be transferred. REQUEST stays active as 
long as a byte is available to be read or 
written. 

The SPECIAL REQUEST function is reserved 
for use with bidirectional ports only. In this 
case, the REQUEST line indicates the status of 
the register not bei ng us ed in the data path at 
that time. If the IN/OUT line is High, the 
REQUEST line is High when the Output 
register is empty. If IN/OUT is Low, the 
REQUEST line is High when the Input register 
is full. 

Pattern-Becogniiion Logic Operation. Both 
Ports A and B can be programmed to generate 
interrupts when a specific pattern is recog- 
nized at the port. The pattern-recognition logic 
is independent of the port application, thereby 
allowing the port to recognize patterns in all of 
its configurations. The pattern can be indepen- 
dently specified for each bit as 1 , 0, rising 
edge, falling edge, or any transition. Indi- 
vidual bits may be masked off. A pattern- 
match is defined as the simultaneous satisfac- 
tion of all nonmasked bit specifications in the 
AND mode or the satisfaction of any non- 
masked bit specifications in either of the OR or 
OR-Priority Encoded Vector modes. 



'□-t>^ 



OUTPUT PORT 



Figure 9. Pulsed Handshake 



The pattern specified in the Pattern Defini- 
tion register assumes that the data path is pro- 
grammed to be noninverting. If an input bit in 
the data path is programmed to be inverting, 
the pattern detected is the opposite of the one 
specified. Output bits used in the pattern- 
match logic are internally sampled before the 
invert/noninvert logic. 

Bit Port Pattern-Recognition Operations. Dur- 
ing bit port operations, pattern- recognition 
may be performed on all bits, including those 
used as I/O for the counter/timers. The input 
to the pattern-recognition logic follows the 
value at the pins (through the invert/noninvert 
logic) in all cases except for simple inputs with 
I'm catchers. In this case, the output of the l's 
catcher is used. When operating in the AND 
or OR mode, it is the transition from a no- 
match to a match state that causes the inter- 
rupt. In the "OR" mode, if a second match 
occurs before the first match goes away, it 
does not cause an interrupt. Since a match 
condition only lasts a short time when edges 
are specified, care must be taken to avoid 
losing a match condition. Bit ports specified in 
the OR-Priority Encoded Vector mode generate 
interrupts as long as any match state exists. A 
transition from a no-match to a match state is 
not required. 

The pattern-recognition logic of bit ports 
operates in two basic modes: transparent and 
latched. When the Latch on Pattern Match 
(LPM) bit is set to (Transparent mode), the 
interrupt indicates that a specified pattern has 
occurred, but a read of the Data register does 
not necessarily indicate the state of the port at 
the time the interrupt was generated. In the 
Latched mode (LPM= 1), the state of all the 
port inputs at the time the interrupt was 
generated is latched in the input register and 
held until IP is cleared. In all cases, the PMF 
indicates the state of the port at the time it is 
read. 

If a match occurs while IP is already set, an 
error condition exists. If the Interrupt On Error 
bit (IOE) is 0, the match is ignored. However, 
if IOE is 1 after the first IP is cleared, it is 
automatically set to 1 along with the Interrupt 
Error (ERR) flag. Matches occurring while ERR 
is set are ignored. ERR is cleared when the 
corresponding IP is cleared. 

When a pattern-match is present in the OR- 
Priority Encoded Vector mode, IP is set to 1. 
The IP cannot be cleared until a match is no 
longer present. If the interrupt vector is allow- 
ed to include status, the vector returned dur- 
ing Interrupt Acknowledge indicates the 
highest priority bit matching its specification at 
the time of the Acknowledge cycle. Bit 7 is the 
highest priority and bit is the lowest. The bit 
initially causing the interrupt may not be the 
one indicated by the vector if a higher priority 
bit matches before the Acknowledge. Once the 



N 
W 

(H 

w 
0> 
o 



2014-010 



315 



Functional Acknowledge cycle is initiated, the vector is 
Description frozen until the corresponding IP is cleared. 
(Continued) Where inputs that cause interrupts might 

change before the interrupt is serviced, the l's 
catcher can be used to hold the value. 
Because a no-match to match transition is not 
required, the source of the interrupt must be 
cleared before IP is cleared or else a second 
interrupt is generated. No error detection is 
performed in this mode, and the Interrupt On 
Error bit should be set to 0. 

Ports with Handshake Pattern-Recognition 
Operation. In this mode, the handshake logic 
normally controls the setting of IP and, 
therefore, the generation of interrupt requests. 
The pattern-match logic controls the Pattern- 
Match Flag (PMF). The data is compared with 
the match pattern when it is shifted from the 
Buffer register to the Input register (input port) 
or when it is shifted from the Output register to 
the Buffer register (output port). The pattern 
match logic can override the handshake logic 
in certain situations. If the port is programmed 
to interrupt when two bytes of data are 
available to be read or written, but the first 
byte matches the specified pattern, the 
pattern-recognition logic sets IP and generates 
an interrupt. While PMF is set, IP cannot be 
cleared by reading or writing the data 
registers. IP must be cleared by command. 
The input register is not emptied while IP is 
set, nor is the output register filled until IP is 
cleared. 

If the Interrupt on Match Only (IMO) bit is 
set, IP is set only when the data matches the 
pattern. This is useful in DMA-type application 
when interrupts are required only after a block 
of data is transferred. 

Counter/Timer Operation. The three 
independent 16-bit counter/timers consist of a 
presettable 16-bit down counter, a 16-bit Time 
Constant register, a 16-bit Current Counter 
register, an 8-bit Mode Specification register, 
an 8-bit Command and Status register, and the 
associated control logic that links these registers. 



Function 


C/T, 


C/Tj 


C/T 3 


Counter/Timer Output 


PB4 


PBO 


PCO 


Counter Input 


PB 5 


PB 1 


PC 1 


Trigger Input 


PB6 


PB 2 


PC 2 


Gate Input 


PB 7 


PB 3 


PC 3 



Table 2. Counter/Timer External Access 

The flexibility of the counter/timers is 
enhanced by the provision of up to four lines 
per counter/timer (counter input, gate input, 
trigger input, and counter/timer output) for 
direct external control and status. Counter/ 
Timer l's external I/O lines are provided by 
the four most significant bits of Port B. 
Counter/Timer 2's are provided by the four 
least significant bits of Port B. Counter/Timer 
3's external I/O lines are provided by the four 
bits of Port C. The utilization of these lines 
(Table 2) is programmable on a bit-by-bit basis 
via the Counter/Timer Mode Specification 
registers. 

When external counter/timer I/O lines are 
to be used, the associated port lines must be 
vacant and programmed in the proper data 
direction. Lines used for counter/timer I/O 
have the same characteristics as simple input 
lines. They can be specified as inverting or 
noninverting; they can be read and used with 
the pattern-recognition logic. They can also 
include the l's catcher input. 

Counter/Timers 1 and 2 can be linked inter- 
nally in three different ways. Counter/Timer 
l's output (inverted) can be used as Counter/ 
Timer 2's trigger, gate, or counter input. 
When linked, the counter/timers have the 
same capabilities as when used separately. The 
only restriction is that when Counter/Timer 1 
drives Counter/Timer 2's count input, 
Counter/Timer 2 must be programmed with 
its external count input disabled. 

There are three duty cycles available for the 
timer/counter output: pulse, one-shot, and 
square-wave. Figure 10 shows the counter/ 
timer waveforms. When the Pulse mode 



:_n_riTiJi_ri/l_ri_ri_r 



TC TC-1 TC-1 TC-a 



J — L 



SQUARE WAVE 



SECOND HALF 



Figure 10. Counter/Timer Waveforms 



316 



Functional is specified, the output goes High for one 
Description clock cycle, beginning when the down-counter 
(Continued) leaves the count of 1. In the One-Shot mode, 

the output goes High when the counter/timer is 
triggered and goes Low when the down- 
counter reaches 0. When the square-wave out- 
put duty cycle is specified, the counter/timer 
goes through two full sequences for each 
cycle. The initial trigger causes the down- 
counter to be loaded and the normal count- 
down sequence to begin. If a 1 count is 
detected on the down-counter's clocking edge, 
the output goes High and the time constant 
value is reloaded. On the clocking edge, when 
both the down-counter and the output are l's, 
the output is pulle d back Low. 

The Continuous/Single Cycle (C/SC) bit in 
the Mode Specification register controls opera- 
tion of the down-counter when it reaches ter- 
minal count. If C/SC is when a terminal 
count is reached, the countdown sequence 
stops. If the C/SC bit is 1 each time the count- 
down counter reaches 1, the next cycle causes 
the time constant value to be reloaded. The 
time constant value may be changed by the 
CPU, and on reload, the new time constant 
value is loaded. 

Counter/timer operations require loading the 
time constant value in the Time Constant 
register and initiating the countdown sequence 
by loading the down-counter with the time 
constant value. The Time Constant register is 
accessed as two 8-bit registers. The registers 
are readable as well as writable, and the 
access order is irrelevant. A in the Time 
Constant register specifies a time constant of 
65,536. The down-counter is loaded in one of 
three ways: by writing a 1 to the Trigger Com- 
mand Bit (TCB) of the Command and Status 
register, on the rising edge of the external 
trigger input, or, for Counter/Timer 2 only, on 
the rising edge of Counter/Timer l's internal 
output if the counters are linked via the trigger 
input. The TCB is write-only, and read always 
returns 0. 

Once the down-counter is loaded, the count- 
down sequence continues toward terminal 
count as long as all the counter/timers' hard- 
ware and software gate inputs are High. If any 
of the gate inputs goes Low (0), the countdown 
halts. It resumes when all gate inputs are 1 
again. 

The reaction to triggers occurring during a 
countdown sequence is determined by the state 
of the Retrigger Enable Bit (REB) in the Mode 
Specification register. If REB is 0, retriggers 
are ignored and the countdown continues nor- 
mally. If REB is 1, each trigger causes the 
down-counter to be reloaded and the count- 
down sequence starts over again. If the output 
is programmed in the Square-Wave mode, 
retrigger causes the sequence to start over 
from the initial load of the time constant. 



The rate at which the down-counter counts is 
determined by the mode of the counter/timer. 
In the Timer mode (the External Count Enable 
[ECE] bit is 0), the down-counter is clocked 
internally by a signal that is half the frequency 
of the PCLK input to the chip. In the Counter 
mode (ECE is 1), the down-counter is decre- 
mented on the rising edge of the counter/ 
timer's counter input. 

Each time the counter reaches terminal 
count, its Interrupt Pending (IP) bit is set to 1, 
and if interrupts are enabled (IE = 1), an inter- 
rupt is generated. If a terminal count occurs 
while IP is already set, an internal error flag is 
set. As soon as IP is cleared, it is forced to 1 
along with the Interrupt Error (ERR) flag. 
Errors that occur after the internal flag is set 
are ignored. 

The state of the down-counter can be deter- 
mined in two ways: by reading the contents of 
the down-counter via the Current Count 
register or by testing the Count In Progress 
(CIP) status bit in the Command and Status 
register. The CIP status bit is set when the 
down-counter is loaded; it is reset when the 
down-counter reaches 0. The Current Count 
register is a 16-bit register, accessible as two 
8-bit registers, which mirrors the contents of 
the down-counter. This register can be read 
anytime. However, reading the register is 
asynchronous to the counter's counting, and 
the value returned is valid only if the counter 
is stopped. The down-counter can be reliably 
read "on the fly" by the first writing of a 1 to 
the Read Counter Control (RCC) bit in the 
counter/timer's Command and Status register. 
This freezes the value in the Current Count 
register until a read of the least significant 
byte is performed. 

Interrupt Logic Operation. The CIO has five 
potential sources of interrupts: the three 
counter/timers and Ports A and B. The 
priorities of these sources are fixed in the 
following order: Counter/Timer 3, Port A, 
Counter/Timer 2, Port B, and Counter/Timer 
1. Since the counter/timers all have equal 
capabilities and Ports A and B have equal 
capabilities, there is no adverse impact from 
the relative priorities. 

The CIO interrupt priority, relative to other 
components within the system, is determined 
by an interrupt daisy chain. Two pins, Inter- 
rupt Enable In (IEI) and Interrupt Enable Out 
(IEO), provide the input and output necessary 
to implement the daisy chain. When IEI is 
pulled Low by a higher priority device, the 
CIO cannot request an interrupt of the CPU. 
The following discussion assumes that the IEI 
line is High. 

Each source of interrupt in the CIO contains 
three bits for the control and status of the 
interrupt logic: an Interrupt Pending (IP) 
status bit, an Interrupt Under Service (IUS) 



MI 
W 

Q 



317 



Functional status bit, and an Interrupt Enable (IE) control 
Description bit. IP is set when an event requiring CPU 
(Continued) intervention occurs. T he s etting of IP results in 
forcing the Interrupt (INT) output Low, if the 
associated IE is 1 . 

The IUS status bit is set as a result of the 
Interrupt Acknowledge cycle by the CPU and 
is set only if its IP is of highest priority at the 
time the Interrupt Acknowledge commences. 
It can also be set directly by the CPU. Its 
primary function is to control the interrupt 
daisy chain. When set, it disables lower prior- 
ity sources in the daisy chain, so that lower 
priority interrupt sources do not request ser- 
vicing while higher priority devices are being 
serviced. 

The IE bit provides the CPU with a means of 
masking off individual sources of interrupts. 
When IE is set to 1 , interrupt is generated nor- 
mally. When IE is set to 0, the IP bit is set 
when an event occurs that wo uld n ormally 
require service; however, the INT output is not 
forced Low. 

The Master Interrupt Enable (MIE) bit allows 
all sources of interrupts within the CIO to be 
disabled without having to individually set 
each IE to 0. If MIE is set to 0, all IPs are 
masked off and no interrupt can be requested 
or acknowledged. The Disable Lower Chain 
(DLC) bit is included to allow the CPU to 
modify the system daisy chain. When the DLC 
bit is set to 1, the CIO's IEO is forced Low, 
independent of the state of the CIO or its IEI 



input, and all lower priority devices' interrupts 
are disabled. 

As part of the Interrupt Acknowledge cycle, 
the CIO is capable of responding with an 8-bit 
interrupt vector that specifies the source of the 
interrupt. The CIO contains three vector 
registers: one for Port A, one for Port B, and 
one shared by the three counter/timers. The 
vector output is inhibited by setting the No 
Vector (NV) control bit to 1 . The vector output 
can be modified to include status information 
to pinpoint more precisely the cause of inter- 
rupt. Whether the vector includes status or not 
is controlled by a Vector Includes Status (VIS) 
control bit. Each base vector has its own VIS 
bit and is controlled independently. When 
MIE = 1 , reading the base vector register 
always includes status, independent of the 
state of the VIS bit. In this way, all the infor- 
mation obtained by the vector, including 
status, can be obtained with one additional 
instruction when VIS is set to 0. When 
MIE = 0, reading the vector register returns 
the unmodified base vector so that it can be 
verified. Another register, the Current Vector 
register, allows use of the CIO in a polled en- 
vironment. When read, the data returned is 
the same as the interrupt vector that would be 
output in an acknowledge, based on the 
highest priority IP set. If no unmasked IPs are 
set, the value FFh is returned. The Current 
Vector register is read-only. 



Programming The data registers within the CIO are 

directly accessed by address lines Ag and A; 
(Table 3). All other internal registers are 
accessed by the following two-step sequence, 
with the address lines specifying a control 
operation. First, write the address of the target 
register to an internal 6-bit Pointer Register; 
then read from or write to the target register. 
The Data registers can also be accessed by 
this method. 

An internal state machine determines if 
accesses with An and Ai equalling 1 are to the 
Pointer Register or to an internal control 
register (Figure 11). Following any control 
read operation, the state machine is in State 
(the next control access is to the Pointer 
Register). This can be used to force the state 
machine into a known state. Control reads in 
State return the contents of the last register 





*o 


Register 








Port C's Data Register 





l 


Port B's Data Register 


1 





Port A's Data Register 


I 


1 


Control Registers 



pointed to. Therefore, a register can be read 
continuously without writing to the Pointer. 
While the CIO is in State 1 (next control 
access is to the register pointed to), many 
internal operations are suspended — no IPs are 
set and internal status is frozen. Therefore, to 
minimize interrupt latency and to allow con- 
tinuous status updates, the CIO should not be 
left in State 1 . 

The CIO is reset by forcing RD and WR Low 
simultaneously (normally an illegal condition) 
or by writing a 1 to the Reset bit. Reset 
disables all functions except a read from or 
write to the Reset bit; writes to all other bits 
are ignored, and all reads return 01h. In this 
state, all control bits are forced to and may 
be programmed only after clearing the Reset 
bit (by writing a to it). 



RD OR 

WR (BIT 0=1) 




{BIT = 1) 

NOTE: State changes occur only when An = Aj = 1. No other 
i have effect. 



Table 3. Register Selection 



Figure 11. State Machine Operation 



318 



Registers 



Interrupt Control 

Address: 000000 
(Read/Write) 

|D,|0.|O i [0,|D,|D a |0,|P.| 



LOWER CHAIN (OLC) 
NO VECTOR (NV) 



- RIGHT JUSTIFIED ADDRESSES 

= SHIFT LEFT (A Irom AD,) 

1 = RIGHT JUSTIFY (A Irom AD | 

- COUNTER/TIMERS VECTOR 
INCLUDES STATUS (CT VIS) 



Master Configuration Control Register 

Address: 000001 
(Read/Write) 



COUNTER/TIMER 1 - 
ENABLE ICTIE) 



PORT C AND COUNTER) - 



COUNTER/TIMER LINK 
CONTROLS (LC) 
LCI LC0 

COUNT ER/TIME RS INDEPENDENT 

1 CJT 1'b OUTPUT GATES CIT 2 

1 C/T 1'b OUTPUT TRIGGERS C/T 2 
1 1 C/T 1'b OUTPUT IS C/T 2's 

COUNT INPUT 
PORT A ENABLE (PAE) 
PORT LINK CONTROL (PLC) 



Figure 12. Master Control Registers 



Port Mode Specification Registers 

Addresses: 100000 Port A 
101000 Port B 
(Read/Write) 

pi,|D.|D,|P.|D,|D,|a,|0.| 



Port Handshake Specification Registers 

Addresses: 100001 Port A 
101001 Port B 
(Read/Write) 



POHT TYPE - 
SELECTS <PTS> 
PTS1 PTSQ 
8 IT PORT 

t INPUT POHT 

1 OUTPUT PORT 

1 1 BIDIRECTIONAL 
PORT 



L 



LATCH ON PATTERN MATCH (LPM) 
(BIT MODE) 

DESKEW TIMER ENABLE (DTE) 
(HANDSHAKE MODES) 



PMS1 PMSO 
DISABLE PATTERN MATCH 

1 -AND'MODE 

1 "OR ' MODE 

1 1 "OR-PRIORITY ENCODED 
VECTOR" MODE 

INTERRUPT ON MATCH ONLY (IMO) 



HANDSHAKE TYPE SPECIFICATION 
BITS (HTS) 

HTS1 HTS0 

INTERLOCKED HANDSHAKE 

1 STROBED HANDSHAKE 

1 PULSED HANDSHAKE 

1 1 THREE-WIRE HANDSHAKE 

REQUEST/WAIT SPECIFICATION BITS 

(RWS) 

RWS2 RWS1 RWSO FUNCTION 



OUTPUT WAIT 



| D ? [ 0, | D 5 j 0, | D 3 | D, | D, [ D u | 

ZT" 



DESKEW TIME SPECIFICATION 
BITS 

SPECIFIES THE MSB's OF 
DESKEW TIMER TIME CONSTANT. 
LSB IS FORCED 1. 



Port Command and Status Registers 

Addresses: 001000 Port A 
001001 Port B 
(Read/Partial Write) 

| D, | D, | 0, | D. | D, | D, | D, | D, | 



J 



SERVICE (IUS) 
INTERRUPT ENABLE (IE) 

INTERRUPT PENDING (IP) 



NULL CODE 
CLEAR IP & IUS 
SET IUS 
CLEAR IUS 
SET IP 
CLEAR IP 
SET IE 
CLEAR IE 



L 



INTERRUPT ON ERROR (IOE) 



- OUTPUT REGISTER EMPTY (ORE) 
(READ ONLY) 



Figure 13. Port Specifications Registers 



2014-012, 013 



319 



Registers 

(Continued) 



Data Path Polarity Registers 

Addresses: 100010 Port A 
101010 Port B 

000101 Port C (4 LSBs only) 
(Read/Write) 

|0,|D,|D,]P.]0,|D i |D l |P J | 



Data Direction Registers 

Addresses: 100011 Port A 
101011 PortB 

000110 Port C (4 LSBs only) 
(Read/Write) 

| 0, | D. | D« | D. | D 3 | P, | D. | P, | 



0AT« PATH POLARITY (DPP) 

■ NON-INVERTINO 

1 = INVERTING 



DATA DIRECTION |DD) 
= OUTPUT BIT 
1= INPUT BIT 



Special I/O Control Registers 

Addresses: 100100 Port A 
101100 PortB 

000111 PortC (4 LSBs only) 
(Read/Write) 

| P, | P. | P, | P. | D, | P a | P, | P„ | 



SPECIAL INPUT/OUTPUT (SIO) 

= NORMAL INPUT OR OUTPUT 

1 = OUTPUT WITH OPEN DRAIN OR 

INPUT WITH J'B CATCHER 



Figure 14. Bit Path Definition Registers 



Port Data Registers 

Addresses: 001101 Port A* 
001110 PortB* 
(Read/Write) 

|d,|d.|d,]d.|d,|d,|d,|d7| 



Port C Data Register 

Address: 001111* 
(Read/Write) 

| o, | p. j p, ] p. | p, [ p, | p. | p. | 



J 



'These registers can be 
addressed directly. 



Figure 15. Port Data 



Pattern Polarity Registers (PP) 

Addresses: 100101 Port A 
101101 PortB 
(Read/Write) 



|d,|d.|d,1o,[o,|d,]o,|d.| 
I 



Pattern Transition Registers (PT) 

Addresses: 100110 Port A 
101 110 PortB 
(Read/Write) 



Pattern Mask Registers (PM) 

Addresses: 100111 Port A 
101111 Port B 
(Read/Write) 



| D, | D. | O, | D. | D,|D,-r0T|0q 



| P, | P« | D> | P. | D, | P, | 0, | dT] 



PM PT PP PATTERN S 



BIT MASKED OFF 
ANY TRANSITION 
ZERO 
ONE 

ONE TO ZERO TRANSITION (.) 
ZERO-TO-ONE TRANSITION V) 



Figure 16. Pattern Definition Registers 



320 



2014-014.015,016 



Registers 

(Continued) 



Counter/Timer Command and Status Registers 

Addresses: 001010 Counter/Timer 1 
001011 Counter/Timer 2 
001100 Counter/Timer 3 
(Read/Partial Write) 

| D, | D. | D, 1 D. 1 P, | D, | P, | D. | 



INTERRUPT UNDER SERVICE (IUS> 
INTERRUPT ENABLE (IE) 
INTERRUPT PENDING (IP) 



J 



NULL CODE 
CLEAR IP & IUS 
SET IUS 
CLEAR IUS 
SET IP 
CLEAR IP 
SET IE 
CLEAR IE 



L 



COUNT IN PROGRESS (CtP) 
(READ ONLY) 



- GATE COMMAND BIT (QCB) 



- READ COUNTER CONTROL (RCC) 
(READ/SET ONLY- 
CLEARED BY READING CCR LSB) 



Counter/Timer Mode Specification Registers 

011100 Counter/Timer 1 

011101 Counter/Timer 2 
011110 Counter/Timer 3 
(Read/Write) 

| ; | D B | 5 | D, | D 3 | D; | D, | Dp | 



EXTERNAL OUTPUT - 
ENABLE (EOE) 



EXTERNAL COUNT - 
ENABLE (ECE) 



EXTERNAL TRIGGER - 
ENABLE <ETE) 



OUTPUT DUTY CYCLE 
SELECTS (DCS) 
DCS1 DCS O 
PULSE OUTPUT 

1 ONE-SHOT OUTPUT 

1 SQUARE-WAVE OUTPUT 
1 1 DO NOT SPECIFY 



RETRIOGER ENABLE BIT (REB) 
- EXTERNAL GATE ENABLE (EQE) 



Counter/Timer Current Count Registers 

Addresses: 010000 Counter/Timer l's MSB 
010001 Counter/Timer l's LSB 

010010 Counter/Timer 2's MSB 

010011 Counter/Timer 2's LSB 

010100 Counter/Timer 3"s MSB 

010101 Counter/Timer 3's LSB 
(Read Only) 

| D r | D. | D, 1 D« | D, | D, | D, 1 0„ | D, | O. | D, | D, | D, | D, ] D, | P. | 
OST — ^ I — LEI 



Counter/Timer Time Constant Registers 

Addresses : 1 1 1 Counter/Timer 1 's MSB 
010111 Counter/Timer l's LSB 

011000 Counter/Timer 2's MSB 

011001 Counter/Timer 2's LSB 

011010 Counter/Timer 3's MSB 

011011 Counter/Timer 3's LSB 
(Read/Write) 

| D, | D, | D, | D. | D, | D ; | D, | D, | D, | D. | D, | D. | D, | D, | D, | D, | 



Figure 17. Counter/Timer Registers 



2014-017 



321 



Registers 

(Continued) 



Interrupt Vector Register 

Addresses: 000010 Port A 
000011 Port B 
000100 Counter/Timers 
(Read/Write) 

|0,j0.|D s ;0.|D,|D,|0,|p7| 



Current Vector Registe 

Address: 011111 
(Read only) 

|d,[o.|o,|d.|d,|p,|d,|d 1 ~| 



INTERRUPT VECTOR 



INTERRUPT VECTOR BASED 
ON HIGHEST PRIORITY 
UNMASKED IP. 
IF NO INTERRUPT PENDING 
ALL Vm OUTPUT. 



PORT VEC TOR STATUS 

PRIORITY ENCODED VECTOR MODE; 
D S Dj Dj 



ALL OTHER MODES: 
D, Dj Di 



COUNT ER/ TIMER STATUS 



C/T 3 
C/T2 

err 1 

ERROR 



Figure 18. Interrupt Vector Registers 



Register 
Address 
Summary 





Main Control negisters 




Port A Specification Registers 


Address 


Register Name 


Address 


Register Name 


000000 


Master Interrupt Control 


100000 


Port A's Mode Specification 


000001 


Master Configuration Control 


100001 


Port A's Handshake Specification 


000010 


Port A's Interrupt Vector 


100010 


Port A's Data Path Polarity 


000011 


Port B's Interrupt Vector 


10001 1 


Port A's Data Direction 


000100 


Counter/Timer's Interrupt Vector 


100100 


Port A's Special I/O Control 


000101 


Port C's Data Path Polarity 


100101 


Port A's Pattern Polarity 


000110 


Port C's Data Direction 


100110 


Port A's Pattern Transition 


000111 


Port C's Special I/O Control 


100111 


Port A's Pattern Mask 




Most Often Accessed Registers 




Port B Specification Registers 


Address 


Register Name 


Address 


Register Name 


001000 


Port A's Command and Status 


101000 


Port B's Mode Specification 


001001 


Port B's Command and Status 


101001 


Port B's Handshake Specification 


001010 


Counter/Timer l's Command and Status 


101010 


Port B's Data Path Polarity 


001011 


Counter/Timer 2's Command and Status 


101011 


Port B's Data Direction 


001100 


Counter/Timer 3's Command and Status 


101100 


Port B's Special I/O Control 


001101 


Port A's Data (can be accessed directly) 


101101 


Port B's Pattern Polarity 


001110 


Port B's Data (can be accessed directly) 


101110 


Port B's Pattern Transition 


001111 


Port C's Data (can be accessed directly) 


101111 


Port B's Pattern Mask 




Counter/ Timer Related Registers 






Address 


Register Name 






010000 


Counter/Timer l's Current Count-MSBs 






010001 


Counter/Timer l's Current Count-LSBs 






010010 


Counter/Timer 2's Current Count-MSBs 






010011 


Counter/Timer 2's Current Count-LSBs 






010100 


Counter/Timer 3's Current Count-MSBs 






010101 


Counter/Timer 3's Current Count-LSBs 






010110 


Counter/Timer l's Time Constant-MSBs 






010111 


Counter/Timer l's Time Constant-LSBs 






011000 


Counter/Timer 2's Time Constant-MSBs 






011001 


Counter/Timer 2's Time Constant-LSBs 






011010 


Counter/Timer 3's Time Constant-MSBs 






011011 


Counter/Timer 3's Time Constant-LSBs 






011100 


Counter/Timer l's Mode Specification 






011101 


Counter/Timer 2's Mode Specification 






011110 


Counter/Timer 3's Mode Specification 






011111 


Current Vector 







322 



2014-018 



Read Cycle. At the beginning of a read cycle, 
the CPU places an address on the address bus. 
Bits Ao and Ai specify a CIO register; the 
remaining address bits and status information 
are combined and decoded to generate a Chip 
EnableJCE) signal that selects the CIO. When 
Read (RD) goes Low, data from the specified 
register is gated onto the data bus. 



Write Cycle. At the beginning of a write 
cycle, the CPU places an address on the data 
bus. Bits Ao and Ai specify a CIO register; the 
remaining address bits and status information 
are combined and decoded to generate a Chip 
Enable (CE) signal that selects the CIO. When 
WR goes Low, data placed on the bus by the 
CPU is strobed into the specified CIO register. 



A0-A1 



ADDRESS VALID 




READ DATA ^ - 



ADDRESS VALID 



WRITE DATA 



xz 



S 



Figure 19. Read Cycle Timing 



Figure 20. Write Cycle Timing 



01 



Interrupt Acknowledge. The CIO pulls its 
Interrupt Reguest (INT) line Low, reguesting 
interrupt service from the CPU, if an Interrupt 
Pending (IP) bit is set and interrupts are 
enabled. The CPU responds with an Interrupt 
Ackno wledge c ycle. When Interrupt Acknowl- 
edge (INTACK) goes true and the IP is set, the 



CIO forces Interrupt Enable Out (IEO) Low, 
disabling all lower priority devices in the inter- 
rupt daisy chain. If the CIO is the highest 
priority device reguesting service (IEI is 
High), it places its interrupt vector on the data 
bus and sets the Interrupt Under Service (IUS) 
bit when Read (RD) goes Low. 



-ff- 



S 



INTACK "\ ^ 



-ff- 
-ff 




Figure 21. Interrupt Acknowledge Timing 



2021-006.007.008 



323 



CPU 

Interface 
Timing 



-©- 



-®- 



zx 



\ 



<5>— 



-®- 



h — !® — ^_3C 



<§>- 



X 



-®— 
*<»>* 



-®— 



<\j' DATA ' 
* ""° f 



1 

®r«- 



-@- 



~®~ 



X 



N 
00 
tfl 

w 
o> 
o 



j or WR / 



f 



-®" 



y 



Interrupt 
Timing 



PATTERN MATCH 



COUNTER 
INPUT 



X 



PATTERN MATCHES 



-®- 



-®- 



Interrupt 

Acknowledge 

Timing 



INTACK 




324 




2014-025.026,027 3 25 



inajuiuuin rating conaiuons lor extended periods may attect 
device reliability. 



Standard The DC characteristics and capacitance sec- 

Test tions below apply for the following standard test 

Conditions conditions, unless otherwise noted. All voltages 

are referenced to GND. Positive current flows 

into the referenced pin. 

Standard conditions are as follows: 

■ +4.75 V < V cc < +5.25 V 

■ GND = V 

■ Ta as specified in Ordering Information 



The Ordering Information section lists temper- 
ature ranges and product numbers. Package 
drawings are in the Package Information section 
in this book. Refer to the Literature List for addi- 
tional documentation. 

All ac parameters assume a load capacitance 
of 50 pf max. 




+ 1V 

I 



Figure 22. Standard Test Load 



Figure 23. Open-Drain Test Load 



DC 

Charac- 
teristics 



Symbol 



Min 



Max 



Unit 



Condition 



Capacitance 





Input High Voltage 


2.0 V cc + 0.3 


V 




V,L 


Input Low Voltage 


-0.3 0.8 


V 




V OH 


Output High Voltage 


2.4 


V 


Io H = -250 iiA 


Vol 


Output Low Voltage 


0.4 


V 


Iql = + 2.0 mA 






0.5 


V 


Iq l = +3.2 mA 


% 


Input Leakage 


±10.0 


«* 


0.4 < V IN s +2.4 V 


>OL 


Output Leakage 


±10.0 


«* 


0.4 == V OUT < +2.4 V 


kx 


V cc Supply Current 


200 


mA 




v cc= 


5 V ± 5% unless otherwise specified, over 


specified temperature range. 






symoo 


1 Parameter 


Min Max 


Unit 


Test Condition 


C IN 


Input Capacitance 


10 


pf 




C OUT 


Output Capacitance 


15 


pf 




c i/o 


Bidirectional Capacitance 


20 


pf 





f = 1 MHz, over specified temperature range. 
Unmeasured pins returned to ground. 



326 



8085-0209. 0001 



No. Symbol Parameter 



4 MHz 6 MHz 

Min Max Min Max Notes*t 



1 


TcPC 


PCLK Cycle time 


250 


4000 


165 


4000 


2 


TwPCh 


PCLK Width (High) 


105 


2000 


70 


2000 


3 


TwPCl 


PCLK Width (Low) 


105 


2000 


70 


2000 


4 


TrPC 


PCLK Rise Time 




20 




10 


5 


— TfPC 


PCLK Fall Time 




20 




15 



TsIA(PC) 
ThlA(PC) 
TsIA(RD) 
ThlA(RD) 
TsIA(WR) - 
ThlA(WR) 
TsA(RD) 
ThA(RD) 
TsA(WR) 

15 — ThA(WR)- 

16 TsCEl(RD) 



INTACK to PCLK t Setup Time 



INTACK to PCLK I Hold Time 



INTACK to RD I Setup Time 
INTACK to RD I Hold Time 



■ INTACK to WR 1 Setup Time - 



INTACK to WR I Hold Time 
Address to RD 1 Setup Time 
Address to RD 1 Hold Time 
Address to WR i Setup Time 

Address to WR I Hold Time 

CE Low to RD 1 Setup Time 

17 TsCEh(RD) CE High to RD I Setup Time 

18 ThCE(RD) CE to RD I Hold Time 

19 TsCEl(WR) CE Low to WR 1 Setup Time 

20 — TsCEh(WR) CE High to WR 1 Setup Time 

21 ThCE(WR) CE to WR 1 Hold Time 

22 TwRDl RD Low Width 

23 TdRD(DRA) RD 1 to Read Data Active Delay 

24 TdRDf(DR) RD 1 to Read Data Valid Delay 

25 — TdRDr(DR) RD t to Read Data Not Valid Delay ■ 

26 TdRD(DRz) RD 1 to Read Data Float Delay 

27 TwWRl WR Low Width 

28 TsDW(WR) Write Data to WR 1 Setup Time 

29 ThDW(WR) Write Data to WR I Hold Time 

30 Trc Valid Access Recovery Time 



100 

200 



-200- 

80 

80 
— 0- 

100 



-100- 



390 




390 



1000* 



255 



70 



100 


200 



-200- 

80 

80 
— 0- 

70 




-70 - 

250 




250 



650 



180 



45 



31 


TdPM(INT) 


Pattern Match to INT Delay (Bit Port) 


2 + 800 


2 + 800 


6 


32 


TdACK(INT) 


ACKIN to INT Delay (Port with Handshake) 


10 + 600 


10 + 600 


4,6 


33 


TdCI(INT) 


Counter Input to INT Delay (Counter Mode) 


2 + 700 


2 + 700 


6 


34 


TdPC(INT) 


PCLK to INT Delay (Timer Mode) 


3 + 700 


3 + 700 


6 



35 

36 

37 

38 

39- 

40 

41 

42 



TsIA(RDA) 
TwRDA 
TdRDA(DR) 
TdlA(IEO) 
-TdlEI(IEO)— 
TsIEI(RDA) 
ThlEI(RDA) 
TdRDA(INT) 



INTACK to RD I (Acknowledge) Setup Time 
RT7(Acknowledge) Width 

RD~I (Acknowledge) to Read Data Valid Delay 



350 
350 



INTACK I to IEO I Delay 

-IEI to IEO Delay 

IEI to RD I (Acknowledge) Setup Time 
IEI to RD~1 (Acknowledge) Hold Time 
RD~I (Acknowledge) to INT 1 Delay 



250 
350 
-150- 



100 
100 



250 
250 



70 
70 



180 
250 
-100- 



600 



600 



NOTES: 

1 . Parameter does nol apply to Interrupt Acknowledge trans- 
actions. 

2. Float delay is measured to the time when the output has 
changed 0.5 V with minimum ac load and maximum dc load. 

3. Trc is the specilied number or 3 TcPC. whichever is longer. 

4. The delay is Irom DAV 1 lor 3 Wire Input Handshake. The 
delay is Irom DAC I for 3 Wire Output Handshake. 

5. t he parameters lor the devices in any particular daisy chain 

. must meet the lollowing constraint: The delay from INTACK i 



to HD 1 must be greater than the sum ol TdlA(lEO) for the 
highest priority peripheral, TslLKHDA) tor the lowest priority 
peripheral, and TdlEI(IEO) for each peripheral separating Iherr. 
in the chain. 
6. Units are equal to TcPC plus ns. 

' Timings are preliminary and subject to change. All timing refer- 
ences assume 2.0 V tor a logic "1" and 0.8 V lor a logic "0". 
t Units in nanoseconds {ns), except as noted. 



4 MHz 6 MHz 

No. Symbol Parameter Min Max Min Max Notes*t 

1 TsDI(ACK) Data Input to ACKIN I Setup Time 

2 ThDI(ACK) Data Input to ACKIN I Hold Time— 500 330 

Strobed Handshake 

3 TdACKl(RFD) ACKIN I to RFD 1 Delay 

4 TwACKl ACKIN Low Width— Strobed Handshake 250 165 

5— TwACKh ACKIN High Width— Strobed Handshake 250 165 

6 TdRFDr(ACK) RFD I to ACKIN I Delay 

7 TsDO(DAV) Data Out to DAV I Setup Time 25 20 1 

8 TdDAVf(ACK) DAV 1 to ACKIN I Delay 

9 ThDO(ACK) Data Out to ACKIN i Hold Time 2 2 2 

10 — TdACK(DAV) — ACKIN 1 to DAV I Delay 2 2 2 — 

11 THDI(RFD) Data Input to RFD I Hold Time— Interlocked 

Handshake 

12 TdRFDf(ACK) RFD 1 to ACKIN t Delay Interlocked Handshake 

13 TdACKr(RFD) ACKIN I (DAV I) to RFD t Delay— Interlocked and 

3- Wire Handwshake 

14 TdDAVr(ACK) DAVl to ACKIN I (RFD 1)— Interlocked and 3- Wire 

Handshake 

15 — TdACK(DAV)— ACKIN 1 (RFD t) to DAV 1 Delay— Interlocked and 

3-Wire Handshake 

16 TdDAVII(DAC) DAV I to DAC I Delay— Input 3-Wire Handshake 

17 ThDI(DAC) Data Input to DAC t Hold Time— 3-Wire Handshake 

18 TdDACOr(DAV) DAC t to DAV t Delay— Input 3-Wire Handshake 

19 TdDAVIr(DAC) DAV t to DAC I Delay— Input 3-Wire Handshake 

20 — TdDAVOf(DAC) DAV I to DAC ! Delay-Output 3-Wire Handshake — 

21 ThDO(DAC) Data Output to DAC t Hold Time— 3-Wire 

Handshake 2 2 2 

22 TdDACIr(DAV) DAC t to DAV t Delay— Output 3-Wire Handshake 2 2 2 

23 TdDAVOr(DAC) DAV I to DAC 1 Delay— Output 3-Wire Handshake 



NOTES: 

1 . This time can be extended through the use of deskew timers. 

2. Units equal to TcPC. 



' Timings are preliminary and subject to change. All timing refer- 
ences assume 2.0 V for a logic "1" and 0.8 V for a logic "0". 
t Units in nanoseconds (ns), except as noted. 



328 



Counter/ 

Timer 

Timing 



I— <n>— 



PCLKI2 

(INTERNAL) 



7" 



KG>~ 

-H® 



v 



■ ® 



/ v 



4 MHz 6 MHz 

No. Symbol Parameter Min Max Min Max Notes*t 

1 TcCI Counter Input Cycle Time S00 330 

2 TCIh Counter Input High Width 230 150 

3 TWCI1 Counter Input Low Width 230 150 

4 TfCI Counter Input Fall Time 20 15 

5 — TrCI Counter Input Rise Time 20 15 

6 TsTI(PC) Trigger Input to PCLK 1 Setup Time (Timer Mode) 150 120 1 

7 TsTI(CI) Trigger Input to Counter Input 1 Setup Time 150 100 

(Counter Mode) 1 

8 TwTI Trigger Input Pulse Width (High or Low) 200 130 

9 TsGI(PC) Gate Input to PCLK 1 Setup Time (Timer Mode) 100 100 1 

10 — TsGI(CI) Gate Input to Counter Input I Setup Time 100 80 

(Counter Mode) I 

11 ThGI(PC) Gate Input to PCLK 1 Hold Time (Timer Mode) 100 70 1 

12 ThGI(CI) Gate Input to Counter Input 1 Hold Time 100 70 

(Counter Mode) 1 

13 TdPC(CO) PCLK to Counter Output Delay (Timer Mode) 475 320 

14 TdCI(CO) Counter Input to Counter Output Delay 475 420 

(Counter Mode) 

NOTES: 



1 . These parameters must be met to guarantee trigger or gate • Timings are preliminary and subject to change. All timing refer - 

are valid for the next counter/timer cycle. ences assume 2.0 V for a logic "1" and 0.8 V for a logic "0". 

t Units in nanoseconds (ns). 



2021-012 



329 



REQUEST/ 

WAIT 

Timing 



\ 



WAIT 



-©- 



J 



J 



No. Symbol 



Parameter 



4 MHz 

Min Max 



6 MHz 
Min Max 



Notes*t 



1 TdRD(REQ) 

2 TdRD(WAIT) 

3 TdWR(REQ) 

4 TdWR(WAIT) 

5 — TdPC(REQ) 

6 TdPC(WAIT) 

7 TdACK(REQ) 

8 TdACK(WAIT) 



RD I to REQ I Delay 



RD I to WAIT I Delay 
WR i to REQ I Delay 



WR I to WAIT 1 Delay 
■PCLK I to REQ I Delay - 



PCLK I to WAIT I Delay 
ACKIN 1 to REQ 1 Delay 



ACKIN 1 to WAIT t Delay 



500 
500 
500 
500 

300 — 

300 
8 + 1000 
10 + 500 



350 
350 
400 
400 

300- 

300 
8 + 900 
10 + 500 



1,2 
1,2 



NOTES: 

1 . The delay is tronm DAV I lor 3-Wire Input Handshake. The 
delay is from DAC I lor 3-Wire Output Handshake. 

2. Units equal to TcPC + ns. 



* Timings are preliminary and subject to change. All timing refer- 
ences assume 2.0 V for a logic "1" and 0.8 V lor a logic "0". 
T Units in nanoseconds (ns), except as noted. 



Reset 
Timing 



k<T>J L^J © 



r 



No. Symbol 



Parameter 



4 MHz 
Min Max 



6 MHz 
Min Max 



Notes*t 



1 TdRD(WR) Delay from RD I to WR I for No Reset 50 

2 TaWR(RD) Delay from WR 1 to RD I for No Reset 50 

3 TwRES Minimum Width of RD and WR both Low for Reset 250 



50 
50 
250 



' Timings are preliminary and subject to change. All timing relftr- 
is assume 2.0 V lor a logic "1" and 0.8 V lor a logic "0". 



t Units in nanoseconds (ns). 



330 



2021-013.014 



Miscellaneous 

Port 

Timing 



MATCH 
INPUT(S) 

DAT* TO BE 
LATCHED TO 
PATTERN MATCH " 





© - 




X 


: v 

PATTERN MATCHES ^ 


t 






© 






> 


; 


V 


( 









4 MHz 


6 MHz 




No. 


Symbol 


Paiameter 


Min Max 


Min 


Max 


Notes't 


1 


TrI 


Any Input Rise Time 


100 




100 




2 


Tfl 


Any Input Fall Time 


100 




100 




3 


Twl's 


l's Catcher High Width 


250 


170 




1 


4 


TwPM 


Pattern Match Input Valid (Bit Port) 


750 


500 






5 


TsPMD 


Data Latched on Pattern Match Setup Time (Bit Port) 












6 


ThPMD 


Data Latched on Pattern Match Hold Time (Bit Port) 


1000 


650 







NOTES: 

1. II the input is programmed inverting, a Low-going pulse o( the 
same width will be detected. 



* Timings are preliminary and subject to change. All timing 

references assume 2.0 V for a logic "1" and 0.8 V for a logig "0". 
T Units in nanoseconds (ns). 



2014-031 



331 



Zilog 



Product Specification 



Z8038/Z8538 
FIO FIFO Input/ 
Output Interface Unit 



October 1988 



Features ■ 128-byte FIFO buffer provides asynchronous 

bidirectional CPU/CPU or CPU/peripheral 
interface, expandable to any width in byte 
increments by use of multiple FIOs. 

■ Interlocked 2-Wire or 3-Wire Handshake 
logic port mode; Z-BUS® or non-Z-BUS 
interface. 

■ Pattern- recognition logic stops DMA 
transfers and/or interrupts CPU; preset byte 
count can initiate variable-length DMA 
transfers. 



Seven sources of vectored/nonvectored 
interrupt which include pattern-match, 
byte count, empty or full buffer status; 
a dedicated "mailbox" register with 
interrupt capability provides CPU/CPU 
communication. 



REQUEST/WAIT lines control high-speed 
data transfers. 

All functions are software controlled via 
directly addressable read/write registers. 



General The Z8038/Z8538 FIO provides an asynchronous 

Description 128-byte FIFO buffer between two CPUs or between 
a CPU and a peripheral device. This buffer interface 
expands to a 16-bit or wider data path and expands 
in depth to add as many Z8060 FIFOs (and an 
additional FIO) as are needed. 

The FIO manages data transfers by assuming 
Z-BUS, non-Z-BUS microprocessor (a generalized 
microprocessor interface), Interlocked 2- Wire 



Handshake, and 3- Wire Handshake operating 
modes. These modes interface dissimilar CPUs or 
CPUs and peripherals running under differing 
speeds or protocols, allowing asynchronous data 
transactions and improving I / O overhead by as 
much as two orders of magnitude. Figures 1 and 2 
show how the signals controlling these operating 
modes are mapped to the FIO pins. 



DATA / 

BUS \ 



CONFIGURATION 



PORT 

1 

SIDE 



Z853B 

no 



SIDE o, 

a 
:• 



\ t 







W 
1 


30 








1 


39 




®c 




1 


36 


]m 








37 




DC 


5 


1 


36 


JtS 


mc 


6 PORT PORT 35 


HE 


BC 


r 1 ' 2 34 

SIDE | SIDE 

B 33 


]E 




DEI 


mL 

CDC 


S 

10 


I 

Z8038/ 
Z8538 


32 
31 


]H 

]m 


DoC 


11 


FIO 


30 


3GD 


O'C 


12 




29 






13 


1 


28 


JD, 


°»c 


14 




37 






15 


1 


26 


5d s 




16 


1 


25 




°.c 


17 


1 








16 


1 


» 






19 


1 


22 


jo, 


gndQ 


20 


1 
1 


21 


]M 



Figure 2a. 40-pin Dual-In-Line Package (DIP). 
Pin Assignments 



332 



General The FIO supports the Z-BUS interrupt pro- 

Description tocols, generating seven sources of interrupts 
(Continued) upon any of the following events: a write to a 
message register, change in data direction, 
pattern match, status match, over/underflow 
error, buffer full and buffer empty status. Each 
interrupt source can be enabled or disabled, 
and can also place an interrupt vector on the 
port address/data lines. 

The data transfer logic of the FIO has been 



specially designed to work with DMA (Direct 
Memory Access) devices for high-speed 
transfers. It provides for data transfers to or 
from memory each machine cycle, while the 
DMA device generates memory address and 
control signals. The FIO also supports the 
variably sized block length, improving system 
throughput when multiple variable length 
messages are transferred amongst several 





« 















5 4 3 2 1 


44 43 42 41 40 \ 




E 


7 






39 


E 


F 


8 






36 


F 


G 


9 






37 


G 


H 


10 






36 


H 


J 


11 
12 


Z8038 


Z853S 


35 
34 


J 


□o 


13 


F 


O 


33 


D<> 


Dj 


14 


PORT 1 
SIDE 


PORT 2 
SIDE 


32 


D, 


Dj 


15 


31 


Di 


0.5 


16 






30 


D? 


Dj 


17 






29 


D, 






19 20 21 22 23 


24 25 26 27 28 f 





^.o <$> o*. ^ ^ c * <> ^, 



Figure 2b. 44-pin Chip Carrier, Pin Assignments 



1 1 

CONTROL AND 
INTERFACE 



A k CPU 
CONTROL AND A \ INTERFACE 



i V i/op 



MESSAGE 
REGISTERS 



INTERRUPT 
LOGIC 



PATTERN 
MATCH 
LOGIC 



PATTERN 
MATCH 
LOGIC 



DATA 
BUFFER 
REGISTER 



128X6 
FIFO BUFFER 



DATA 
BUFFER 
REGISTER 



PORT 2 SIDE 



Figure 3. FIO Block Diagram 



333 



Z-BUS, Interlocked 2-Wire Handshake, and 
3- Wire Handshake modes. Table 1 describes 
the signals and their corresponding pins in 
each of these modes. 



r**r» i a v^uiuiui icyiaici u. xduie ^ uescriDes 
the combinations of operating modes; Table 3 
describes the control signals mapped to pins 
A- J in the five possible operating modes. 



Signal 
Pins 



Z-BUS Z-BUS 
Low Byte High Byte 



Non-Z-BUS 



Interlocked 
HS Port* 



3- Wire 
HS Port* 



B 
B 
B 
B 
B 
E 
B 
B 
B 

m 



REQ/WT REQ/WT 



REQ/WT 



RFD/DAV 



DMASTB 

DS 

R/W 

CS 

AS 

INTACK 
IEO 
IE1 
INT 



DMASTB 

DS 

R/W 

CS 

AS 

A 

*1 

A 2 

A 3 



DACK 
RD 
WR 
CE 

C/D 

INTACK 
IEO 
IEI 
iNT 



ACKIN 

FULL 

EMPTY 



RFD/DAV 
DAV/DAC 
DAC/RFD 
EMPTY 



CLEAR 
DATA DIR 
IN 
OUTj 

51 
out 3 



CLEAR 
DATA DIR 

m 

OUTi 

OE 

OUT3 



*2 side only. 



Table 1. Pin Assignments 



Mode 


Mi 


Mo 


»i 


B 


Port 1 


Port 2 

















Z-BUS Low Byte 


Z-BUS Low Byte 


1 











1 


Z-BUS Low Byte 


Non-Z-BUS 


2 








1 





Z-BUS Low Byte 


3- Wire Handshake 


3 








1 


1 


Z-BUS Low Byte 


2- Wire Handshake 


4 





1 








Z-BUS High Byte 


Z-BUS High Byte 


5 





1 





1 


Z-BUS High Byte 


Non-Z-BUS 


6 





1 


1 





Z-BUS High Byte 


3- Wire Handshake 


7 





1 


1 


1 


Z-BUS High Byte 


2- Wire Handshake 


8 


1 











Non-Z-BUS 


Z-BUS Low Byte 


9 


1 








1 


Non-Z-BUS 


Non-Z-BUS 


10 


1 





1 





Non-Z-BUS 


3- Wire Handshake 


11 




a 


1 


1 


Non-Z-BUS 


2- Wire Handshake 



Table 2. Operating Modes 



334 



Functional 
Description 

(Continued) 



SYSTEM 
MEMORY 



d 



d 



d 



d 



d 



3 



dd 
dd 



SYSTEM 
MEMORY 



Z 1 \ PORT 2 

s — / <8> 



Figure 4. CPU to CPU Configuration 



Figure 5. CPU to I/O Configuration 



335 



Pins Common 
To Both Sides 


Pin 

Signals 


Pin 
Names 


Pin 
Numbers 


Signal 
Description 




M 
Mi 


M 
Mi 




21 
19 


M] and Mo program Port 1 
side CPU interface 




+ 5 Vdc 


+ 5 Vdc 




40 


DC power source 




GND 






20 


DC power ground 


u-DUO 

Low Byte 
Mode 

Z8038 


Pin 

Signals 


Pin 
Names 


Pin Numbers 
Port 
1 2 


Signal 
Description 


AD0-AD7 
(Address/Data) 


D -D 7 


11-1 


.8 29-22 


Multiplexed bidirectional address/data lines, Z-BUS 
compatible. 




REQAVAIT 
(Request/Wait) 


A 


1 


39 


Output, active Low, REQUEST (ready) line ior DMA 
transfer; WAIT line (open-drain) output ior syn- 
chronized CPU and FIO data transiers. 




DMASTB 
(Direct Memory 
Access Strobe) 


B 


2 


38 


Input, active Low. Strobes DMA data to and from 
the FIFO buffer. 




DS 

(Data Strobe) 


C 


3 


37 


Input, active Low. Provides timing for data trans- 
fer to or from FIO. 




R/W 

(Read/Write) 


D 


4 


36 


Input; active High signals CPU read from FIO; 
active Low signals CPU write to FIO. 




CS 

(Chip Select) 


E 


5 


35 


Input, active Low. Enables FIO. Latched on the 
rising edge of AS. 




AS 

(Address Strobe) 


F 


6 


34 


Input, active Low. Addresses, CS and INTACK 
sampled while AS Low. 




INTACK 
' (Interrupt 
Acknowledge) 


G 


7 


33 


Input, active Low. Acknowledges an interrupt. 
Latched on the rising edge of AS. 




IEO 

(Interrupt 
Enable Out) 


H 


8 


32 


Output, active High. Sends interrupt enable to 
lower priority device IEI pin. 




IEI 

(Interrupt 
Enable In) 


I 


9 


31 


Input, active High. Receives interrupt enable from 
higher priority device IEO signal. 




INT 

(Interrupt) 


I 


10 


30 


Output, open drain, active Low. Signals FIO inter- 
rupt request to CPU. 


Z-BUS 
High Byte 

Z8038 


Pin 

Signals 


Pin 
Names 


Pin Numbers 
Port 
1 2 


Signal 
Description 


ADn-ADy 
(Address/Data) 


Do-Dy 


11-18 29-22 


Multiplexed bidirectional address/data lines, Z-BUS 
compatible. 




REQ/WAIT 
(Request/Wait) 


A 


1 


39 


Output, active Low, REQUEST (ready) line for DMA 
transfer; WAIT line (open-drain) output for syn- 
chronized CPU and FIO data transfers. 




DMASTB 
(Direct Memory 
Access Strobe) 


B 


2 


38 


Input, active Low. Strobes DMA data to and from the 
FIFO buffer. 




DS 

(Data Strobe) 


C 


3 


37 


Input, active Low. Provides timing for transfer of data 
to or from FIO. 




R/W 

(Read/Write) 


D 


4 


36 


Input, active High. Signals CPU read irom FIO; active 
Low signals CPU write to FIO. 




CS 

(Chip Select) 


E 


5 


35 


Input, active Low. Enables FIO. Latched on the 
rising edge of AS. 




AS 

(Address Strobe) 


F 


6 


34 


Input, active Low. Addresses, CS and INTACK are 
sampled while AS is Low. 




An 

(Address Bit 0) 


G 


7 


33 


Input, active High. With Ai, A 2 , and A3, addresses 
FIO internal registers. 




Ai 

(Address Bit 1) 


H 


8 


32 


Input, active High. With An, A 2 , and A3, addresses 
FIO internal registers. 




A 2 

(Address Bit 2) 


I 


9 


31 


Input, active High. With An, A], and A3, addresses 
FIO internal registers. 




A 3 

(Address Bit 3) 


I 


10 


30 


Input, active High. With An, Aj, and A 2 , addresses 
FIO internal registers. 



Table 3. Signal/Pin Descriptions 



336 



Non-Z-BUS 
Mode 

Z8S38 



Pin Numbers 



Pin 

Signal! 


Pin 
Names 


Port 

1 


4 




Signal 
Description 


Dn-D-7 

(Data) 




11-18 29-22 




Bidirectional data bus. 


REQ/WT 
(Request/Wait) 


A 


1 


39 




Output, active Low, REQUEST (ready) line for DMA 
transfer; WAIT line (open-drain) output for syn- 
chronized CPU and FIO data transfer. 


DACK 

(DMA Acknowledge) 


B 


2 


38 




Input, active Low. DMA acknowledge. 


SB 

(Read) 


C 


3 


37 




Input, active Low. Signals CPU read from FIO. 


WR 
(Write) 


D 


4 


36 




Input, active Low. Signals CPU write to FIO. 


cl 

(Chip Select) 


E 


5 


35 




Input, active Low. Used to select FIO. 


C/D 

V Vw^Ul ill Uiy Lsa la J 


F 


6 


34 




Input, active High. Identifies control byte on Dg-D?; 
active Low identifies data byte on Dq— D^ 


INTACK 
(Interrupt 
Acknowledge) 


G 


7 


33 




Input, active Low. Acknowledges an interrupt. 


IEO 

(Interrupt 
Enable Out) 


H 


8 


32 




Output, active High. Sends interrupt enable to 
lower priority device IEI pin. 


IEI 

(Interrupt 
Enable In) 


I 


9 


31 




Input, active High. Receives interrupt enable from 
higher priority device IEO signal. 


INT 

(Interrupt) 


J 


10 


30 




Output, open drain, active Low. Signals FIO interrupt 
to CPU. 


Piu 

Signals 


Pin 
Names 


Pin 
Numbers 




Mode 


Signal 
Description 


(Data) 


D0-D7 


29-22 




9 Wire* H 1 ^* 

z- vv ire no 
3- Wire HS 


Bidirectional data bus. 


RFD/DAV 

ineaoy lor un\oj LJaia 
Available) 


A 


39 




2- Wire HS 

q Wins 


Output, RFD active High. Signals peripherals that FIO 
is ready to receive data. DAV active Low signals 
that FIO is ready to send data to peripherals. 


ACKIN 

(Acknowledge Input) 


B 


38 




2- Wire HS 


Input, active Low. Signals FIO that output data is 
received by peripherals or that input data is valid. 


DAV/DAC 

(Data Available/Data 

Accepted) 


B 


38 




3-Wire HS 


Input; DAV (active Low) signals that data is valid on 
bus. DAC (active High) signals that output data is 
accepted by peripherals. 


FULL 


C 


37 




2- Wire HS 


Output, open drain, active High. Signals that FIO 



Port 2-I/0 
Port Mode 



DAC/RFD 

(Data Accepted/Ready 
for Data) 

EMPTY 



CLEAR 



DATA DIR 
(Data Direction) 

Big 

OUT, 
OE 

(Output Enable) 
OUT3 



G 
H 
I 
I 



37 

36 
3S 
34 

33 
32 
31 
30 



3-Wire HS 



2- Wire HS 

3- Wire HS 

2- Wire HS 

3- Wire HS 

2- Wire HS 

3- Wire HS 

2- Wire HS 

3- Wire HS 

2- Wire HS 

3- Wire HS 

2- Wire HS 

3- Wire HS 

2- Wire HS 

3- Wire HS 



buffer is full. 

Direction controlled by internal programming. Both 
active High. DAC (an output) signals that FIO has 
received data from peripheral; RFD (an input) signals 
that the listeners are ready for data. 

Output, open drain, active High. Signals that FIFO 
buffer is empty. 

Programmable input or output, active Low. Clears all 
data from FIFO buffer. 

Programmable input or output. Active High signals 
data input to Port 2; Low signals data output from 
Port 2. 

Input line to Do of Control Register 3. 

Output line from D, of Control Register 3. 

Input, active Low. When Low, enables bus drivers. 
When High, floats bus drivers at high impedance. 

Output line from D3 of Control register 3. 



'Handshake 



Table 3. Signal/Pin Descriptions (Continued) 



337 



ousiy in i-uua mode tnormally illegal). 

■ By forcing RD and WR Low simultaneously 
in non-Z-BUS mode. 

■ By writing a 1 to the Reset bit in Control 
register for software reset. 

In the Reset state, all control bits are cleared 
to 0. Only after clearing the Reset bit (by 



rui i_uupex system conirox, wnen fort 1 is 
reset, Port 2 is also reset. In addition, all Port 
2's outputs are floating and all inputs are 
ignored. To initiate the data transfer, Port 2 
must be enabled by Port 1 . The Port 2 CPU 
can determine when it is enabled by reading 
Control register 0, which reads "floating" data 
bus if not enabled and "01h" if enabled. 



CPU The FIO is designed to work with both 

Interfaces Z-BUS- and non-Z-BUS-type CPUs on both Port 
1 and Port 2. The Z-BUS configuration inter- 
faces CPUs with time-multiplexed address and 
data information on the same pins. The Z8001®, 
Z8002® , and Z8® are examples of this type of 
CPU. The AS (Address Strobe) pin is used to 
latch the address and chip select information 
sent out by the CPU. The R/W (Read/Write) 
pin and the DS (Data Strobe) pin are used 
for timing reads and writes from the CPU to 



the FIO (Figures 6 and 7). 

The non-Z-BUS configuration is used for CPUs 
where the address and data buses are separate. 
Examples of this typed CPU are the_Z80® and 
the Intel 8080. The RD (Read) and WR (Write) 
pins are used to time reads and writes from_the 
CPU to the FIO (Figures 9 and 10). The C/D 
(Control/Data) pin is used to directly access the 
FIFO buffer (C/D = 0) and to access the other 



to cpu y - 



CS 



f 



Figure 6. Z-BUS Read Cycle Timing 



(ADDRESS \_^/ 
VALID / \ 



DATA FROM CPU 



f 



Figure 7. Z-BUS Write Cycle Timing 



CPU registers (C/D = 1 ). Read and write to all registers 

Interfaces except the FIFO buffer! are two-step operations, 
(Continued) described asjollows (Figure 8). First, write the 
address (C/D = 1 ) of the register to be accessed 
into the Pointer Register (State 0); second, read 
or write (C/D = 1 ) to the register pointed at previ- 
ously (State 1). Continuous status monitoring can 
be performed in State 1 by continuous Control 
Read operations (C/D = 1). 



(C/D = 



A- 



WR TO PTR 

{C/D = 1) 



WR OR RD OF ANY 

(CIS = 1) 



IC/D = 01 



JThe FIFO buffer can also be accessed by this two-step operation. 



Figure 8. Register Access in Non-Z-BUS Mode 



SI 

RD 



X 



X 




s 



Figure 9. Non-Z-BUS Read Cycle Timing 



X 



X 



X 



S 



X 



S 



Figure 10. Non-Z-BUS Write Cycle Timing 



WAIT When d ata is output by the CPU, the 

Operation REQ/WT (WAIT) pin is active (Low) only when 
the FIFO buffer is full, the chip is select ed, 
and the FIFO buffer is addressed. WAIT goes 
inactive when the FIFO buffer is not full. 



When data is input by the CPU, the 
REQ/WT pin becomes active (Low) only when 
the FIFO buffer is empty, the chip is sele cted, 
and the FIFO buffer is addressed. WAIT goes 
inactive when the FIFO buffer is not empty. 



Interrupt The FIO supports Zilog's prioritized daisy 

Operation chain interrupt protocol for both Z-BUS and 
non-Z-BUS operating modes (for more details 
refer to the Zilog Z-BUS Summary). 

Each side of the FIO has seven sources of 
interrupt. The priorities of these devices are 
fixed in the following order (highest to lowest): 
Mailbox Message, Change in Data Direction, 
Pattern Match, Status Match, Overflow/ 



Underflow Error, Buffer Full, and Buffer 
Empty. Each interrupt source has three bits 
that control how it generates the interrupt. 
These bits are Interrupt Pending (IP), 
Interrupt Enable (IE), and Interrupt Under 
Service (IUS). 

In addition, each side of the FIO has an 
interrupt vector and four bits controlling the 
FIO interrupt logic. These bits are Vector 



339 



Interrupt Includes Status (VIS), Master Interrupt Enable 

Operation (MIE), Disable Lower Chain (DLC), and No 
(Continued) Vector (NV). 

A typical Interrupt Acknowledge cycle for 
Z-BUS operation is shown in Figure 1 1 and for 
non-Z-BUS operation in Figure 12 . The on ly 
difference is that in Z-BUS mode, INTACK is 
latched b y AS, and in non-Z-BUS mode 
INTACK is not latched. 

When MIE = 1 , reading the vector always 
includes status, independent of the state of the 



VIS bit. In this way, when VIS = 0, all infor- 
mation can be obtained with one additional 
read, thus conserving vector space. When 
MIE = 0/ reading the vector register returns 
the unmodified base vector so that it can be 
verified. 

In non-Z-BUS mode, the IPs do not get set 
while in State 1 . Therefore, to minimize inter- 
rupt latency, the FIO should be left in State 0. 
In Z-BUS mode IPs are set by an AS following 
the event. 



""^ IGNORED ^ 



INTACK 



f 



T 



f 



Figure 11. Z-BUS Interrupt Acknowledge Cycle 




f 



f 



INT 



f 



Figure 12. Non-Z-BUS Interrupt Acknowledge Cycle 



CPU to CPU DMA Operation. The FIO is particularly well 
Operation suited to work with a DMA in both Z-BUS and 
non-Z-BUS modes. A data transfer between the 
FIO and system memory can take place during 
every machine cycle on both sides of the FIO 

simultaneously. 

In Z-BUS mode, the DMASTB pin (DMA 
Strobe) is used to read or write into the FIFO 
buffer. The R/W (Read/Write) and DS (Data 
Strobe) signals are ignored by the FIO; 



however, the CS (Chip Select) signal is not 
ignored and therefore must be kept invalid. 
Figures 13 and 14 show typ ical tim ing. 

In Non-Z-BUS mode, the DACK pin (DMA 
Acknowledge) is used to tell th e FIO that its 
DMA request is granted. After DACK goes 
Low, every read or write to the FIO goes into 
the FIFO buffer. Figures 15 and 16 show 
typical timing. 



340 



CPU to CPU ^ . . , v 

Operation A ' ' ut X ™m"dma ) ( data from fio to memory ) — 



(Continued) 



A f 



WW 



snuTi 



Figure 13. Z-BUS FIO to Memory Data Transaction 



AID BUI Y ADDRESS \_/~ 

A FROM DMA / \ 



DATA FROM MEMORY TO FIO 



a r 



Figure 14. Z-BUS Memory to FIO Data Transaction 



ADDRESSES MEMORY ADDRESS OF WRITE 



DATA 
BUS 



— ^OATA FROM FIO TO MEMORY^ 



^ r~\ r 



Figure 15. Non-Z-BUS FIO to Memory Transaction 



MEMORY ADDRESS OF READ 



<r>ATA FBflM \ ( 

MEMORY TO FIO / \_ 



READ 



"\ / — \ r 



\ / \ / 

~\ 

Figure 16. Non-Z-BUS Memory to FIO Data Transaction 

341 



CPU to CPU The FIO provides a special mode to enhance 
Operation its DMA transfer capability. Whe n da t a is 
(Continued) written into the FIFO buffer, the REQ/WT 

(REQUEST) pin is active (Low) until the FIFO 
buffer is full. It then goes inactive and stays 
inactive until the number of bytes in the FIFO 
buffer is equal to the value programmed into 
the Byte C ount Comparison register. Then the 
REQUEST signal goes active and the sequence 
starts over again (Figure 17). 



When data is read from the FIO, the 
REQ/WT pin (REQUEST) is inactive until the 
number of bytes in the FIFO buffer is equal to 
the value programme d in the By te Count Com- 
parison register. The REQUEST signal then 
goes active and stays activ e until the FIFO buf- 
fer is empty. When empty, REQUEST goes 
inactive and the sequence starts over again 
(Figure 18). 



342 




OF BYTES IN FIFO 



EMPTY FULL 

NUMBER IN BYTE COUNT COMPARISON REGISTER 

NOTES: 

1. FIFO emp ty, 

2. REQUEST enabled, FIO requests DMA transfer. 

3. DMA transfers data into the FIO. 

4. FIFO full, REQUEST inactive. 

5. The FIFO empties from the opposite port until the number 
of bytes in the FIFO buffer is the same as the number pro- 
grammed in the Byte Count Comparison register. 

Figure 17. Byte Count Control: Write to FIO 




FULL 

1 IN BYTE COUNT COMPARISON REGISTER 



1. FIFO empty. 

2. CPU/DMA fills FIFO buffer from the opposite port. 

3. Number of bytes in FIFO buffer is the same as the number 

of bytes pr ogrammed in the Byte Count Comparison register. 

4. REQUEST goes active. 

5. DMA transfers data out of FIFO until it is empty. 



Figure 18. Byte Count Control: Head from FIO 



Message Registers. Two CPUs can communi- 
cate through a dedicated "mailbox" register 
without involving the 128 x 8 bit FIFO buffer 
(Figure 19). This mailbox approach is useful 
for transferring control parameters between 
the interfacing devices on either side of the 
FIO without using the FIFO buffer. For 
example, when Port l's CPU writes to the 
Message Out register, Port 2's message IP is 
set. If interrupts are enabled, Port 2's CPU is 



interrupted. Port 2's message IP status is 
readable from the Port 1 side. When Port 2's 
CPU reads the data from its Message In regis- 
ter, the Port 2 IP is cleared. Thus, Port l's 
CPU can read when the message has been 
read and can now send another message or 
follow whatever protocol that is set up between 
the two CPU's. The same transfer can also be 
made from Port 2's CPU to Port l's CPU. 




NOTE: Usable only for CPU/CPU interface. 
Figure 19. Message Register Operation 



CPU to CPU CLEAR (Empty) FIFO Operation. The CLEAR 
Operation FIFO bit (active Low) clears the FIFO buffer of 
(Continued) data. Writing a to th is bit empt ies the FIFO 
buffer, inactivates the REQUEST line, and 
disables the handshake (if programmed). The 
CLEAR bit does not affe ct any c ontrol or data 
registe r. To re move the CLEAR state, write a 1 
to the CLEAR bit. 

In CPU/CPU mode, under program control, 
only one of the ports can empty the FIFO by 
writing to its Control Register 3, bit 6. The 
Port 1 CPU must program bit 7 in Control 
Register 3 to determine which port controls the 
CLEAR FIFO operation (0 = Port 1 control; 
1 = Port 2 control). 

Direction of Data Transfer Operation. The 



Data Direction bit controls the direction of data 
transfer in the FIFO buffer. The Data Direction 
bit is defined as = output from CPU and 
1 = input to CPU. This bit reads correctly 
when read by either port's CPU. For example, 
if Port l's CPU reads a (CPU output) in its 
Data Direction bit, then Port 2's CPU reads a 1 
(input to CPU) in its Data Direction bit. 

In CPU/CPU mode, under program control, 
only one of the ports can control the direction 
of data transfer. The Port 1 CPU must program 
bit 5 in Control Register 3 to determine which 
port controls the data direction (0 = Port 1 
control; 1 = Port 2 control). Figure 20 shows 
FIO data transfer options. 



\ RESET / 



(PROGRAM REGISTERS FOR OPERATING MODE, 
PORT 2 CONFIGURATION, DATA TRANSFER CONTROL, ETC.) 



PORT 1 
ENABLES 
PORT 2 



PORT 1 (CPU) 



PORT 2 (CPU) 



PORT 2 (I/O) 



EXCHANGE 
CONTROL 
PARAMETERS 



PARAMETERS 



2- WIRE 
HANDSHAKE 
INTERFACE 



3- WIRE 
HANDSHAKE 
INTERFACE 



DMA- 
CONTROLLED 
TRANSFER 



(DMA OR INTERRUPT- 
DRIVEN TRANSFERS. AS 
FOR PORT 1) 



TRANSFERS DATA BYTE- 
AT-A-TIME UNTIL 
FIFO BUFFER IS 



TERMINATES ON ANY 
OF THESE CONDITIONS: 
•DMA BLOCK LENGTH REGISTER = 
■FIO PATTERN MATCH INTERRUPT 
'BYTE COUNT DISABLES REG 
I 



TERMINATES ON ANY 
OF THESE CONDITIONS: 
•CPU COMPLETES BUFFER DUMP 
•FIO PATTERN MATCH INTERRUPT 
-FIO BYTE COUNT INTERRUPT 
•FIO Full/ Empty INTERRUPT 
I 



I 
I 



EXCHANGE 
CONTROL 
PARAMETERS 
WITH PORT 2 
CPU 



\ / 

Y 
t 



EXCHANGE 
CONTROL 
PARAMETERS 
WITH PORT 1 
CPU 



CONTINUE OR REPROGRAM PORT REGISTERS WITH NEW BLOCKS OF CONTROL BYTES. 



Figure 20. FIO Data Transfer Options 



343 



device. In t he Int erlo cked 2- W ire Handshake 
mode, RFD/DAV and ACKIN strobe data to 
and from Po rt 2. I n the 3- Wire Handshake 
mode, RFD/DAV, DAV/DAC, and DAC/RFD 
signals control data flow. 

Interlocked 2-Wire Handshake. In the Inter- 
locked Handshake, the action of the FIO must 
be acknowledged by the other half of the 
handshake before the next action can take 
place. In output mode, Port 2 does not indicate 
that new data is available until the external 
device indicates it is ready for the data. 
Similarly, in input mode, Port 2 does not indi- 
cate that it is ready for new data until the data 
source indicates that the previous byte of the 
data is no longer available, thereby acknowl- 
edging Port 2's acceptance of the last byte. 
This allows the FIO to directly interface to a 
Z8's port, a CIO's port, a UPC's port, another 
FIO port, or another FIFO Z8060, with no 
external logic (Figures 21 and 22). 

3- Wire Handshake. The 3-Wire Handshake is 
designed for applications in which one output 
port is communicating with many input ports 
simultaneously. It is essentially the same as the 
Interlocked Handshake, except that two signals 
are used to indicate that an input port is ready 
for new data or that it has accepted the present 
data. In the 3-Wire Handshake, the rising 
edge of the RFD status line indicates that the 
port is ready for data, and the rising edge of 
the DAC status line indicates that the data has 
been accepted. With 3-Wire Handshake, the 
lines of many input ports can be bussed 
together with open-drain drivers and the out- 



b i U1 ^cu uiiuei auitware controi, Diairectional 
IEEE-488-type transfers can be performed. 
Figures 23 and 24 show the timings associated 
with 3-Wire Handshake communications. 

CLEAR FIFO Operation. In CPU-to-I/O 
operation, the CLEAR FIFO operation can be 
performed by the CPU side (Port 1) under soft- 
ware control as previously explained. The 
CLEAR FIFO operation can also be performed 
under h ardware control by defining the 
CLEAR pin of Port 2 as an input (Control 

Register 3, bit 7 = 1). 

For cascading purposes, the CLEAR pin can 
also be defined as an output (Control Register 
3, bit 7 = 0), which reflects the current state 
of the CLEAR FIFO bit. It can then empty 
other FIOs or initialize other devices in the 
system. 

Data Direction Control. In CPU-to-I/O mode, 
the direction of data transfer can be controlled 
by the CPU side (Port 1) under software con- 
trol as previously explained. The data direc- 
tion can also be determined by hardware con- 
trol by defining the Data Direction pin 
of Port 2 as an input (Control Register 3, 
bit 5 = 1). 

For cascading purposes, the Data Direction 
pin can also be defined as an output (Control 
Register 3, bit S = 0) pin which reflects the 
current state of the Data Direction bit. It can 
then be used to control the direction of data 
transfer for other FIOs or for external logic. 

On the Port 2 side, when data direction is 0, 
Port 2 is in Output Handshake mode. When 
data direction is 1 , Port 2 is in Input Hand- 
shake mode. 



CPU to I/O 
Operation 

(Continued) 



uw X valid data X X X " 



A / 



— \ r~ 

\ / \ r 



Figure 21. Interlocked Handshake Timing (Input) Part 2 Side Only 



~)( VALID DATA \ ~^ VALID DATA 



a r 

r~ 



a r 



Figure 22. Interlocked Handshake Timing (Output) Port 2 Side Only 



DATA IN VALID DATA ~\ \ VALID DATA ) f 

— s / — \ 



OUT 
DAV 



a r 



a r 

r~ 



Figure 23. Input (Acceptor) Timing IEEE-488 HS Port: Port 2 Side Only 



DAV 

OUT 



VALID DATA ^ X VALID DATA X " 

"A / \_^" 



A. 



J — V 



Figure 24. Output (Source) Timing IEEE-488 HS Port: Port 2 Side Only 



345 



Programming The programming of the FIO is greatly 
simplified by the efficient grouping of the 
various operation modes in the control 
registers. Since all of the control registers are 
read/write, the need for maintaining their 
image in system memory is eliminated. Also, 
the read/write feature of the registers aids in 
system debugging. 

Each side of the FIO has 16 registers. All 16 
registers are used by the Port 1 side; Control 
register 2 is not used on the Port 2 side. All 
registers are addressable Oh through Fjj. 

In the Z-BUS Low Byte mode, the FIO allows 
two methods for register addressing under con- 
trol of the Right Justify Address (RJA) bit in 
Control register 0. When RJA = 0, address 
bus bits 1-4 are used for register addressing 
and bits 1, 5, 6, and 7 are ignored (Table 4). 
When RJA = 1 , bits 0-3 are used for the 
register addresses, and bits 4-7 are ignored. 

Control Registers. These four registers specify 
FIO operation. The Port 2 side control 



Non Z-BUS 


D7-D4 


D 3 


D 2 




Do 




Z-BUS High 




A3 


A 2 


A, 


Ao 




Z-BUS Low 


AD7-AD5 
AD7-AD4 


AD 4 

AD 3 


AD 3 
AD 2 


AD 2 
AD, 


AD, 
AD 


AD 


Description 














Control Register 


X 














X 


Control Register 1 


X 











1 


X 


Interrupt Status Register 


X 








1 





X 


Interrupt Status Register 1 


X 








1 


1 


X 


Interrupt Status Register 2 


X 





1 








X 


Interrupt Status Register 3 


X 





1 





1 


X 


Interrupt Vector Register 


X 





1 


1 





X 


Byte Count Register 


X 





1 


1 


1 


X 


Byte Count Comparison 
Register 


X 













X 


Control Register 2* 


X 










1 


X 


Control Register 3 


X 







1 





X 


Message Out Register 


X 







1 


1 


X 


Message In Register 


X 




1 








X 


Pattern Match Register 


X 




1 





1 


X 


Pattern Mask Register 


X 




1 


1 





X 


Data Buffer Register 


X 




1 


1 


1 


X 



x = Don't Care 

* Register is only on Port 1 side 

Table 4. FIO Register Address Summary 



registers operate only if the Port 2 device is a 
CPU. The Port 2 CPU can control interface 
operations, including data direction, only 
when enabled by the setting of bit in the Port 
1 side of Control Register 2. A 1 in bit 1 of the 
same register enables the handshake logic. 

Interrupt Status Registers. These four 
registers control and monitor the priority 
interrupt functions for the FIO. 

Interrupt Vector Register. This register stores 
the interrupt service routine address. This vec- 
tor is placed on D0-D7 when IUS is set by the 
Interrupt Acknowledge signal from the CPU. 
When bit 4 (Vector Includes Status) is set in 
Control Register 0, the reason for the interrupt 
is encoded within the vector address in bits 1 , 
2, and 3. If bit 5 is set in Control register 0, no 
vector is output by the FIO during an Interrupt 
Acknowledge cycle. However, IUS is set as 
usual. 



Programming Byte Count Compare Register. This register 
(Continued) contains a value compared with the byte count 
in the Byte Count register. If the Byte Count 
Compare interrupt is enabled, an interrupt will 
occur upon compare. 

Message Out Register. Either CPU can place 
a message in its Message Out register. If the 
opposite side Message register interrupt is 
enabled, the receiving side CPU will receive 
an interrupt request, advising that a message 
is present in its Message In register. Bit 5 in 
Control Register 1 on the initiating side is set 
when a message is written. It is cleared when 
the message is read by the receiving CPU. 

Message In Register. This register receives a 
message placed in the Message Out register by 
the opposite side CPU. 

Pattern Match Register. This register contains 
a bit pattern matched against the byte in the 



Data Buffer register. When these patterns 
match, a Pattern Match interrupt will be 
generated, if previously enabled. 

Pattern Mask Register. The Pattern Mask 
register may be programmed with a bit pattern 
mask that limits comparable bits in the Pattern 
Match register to non- masked bits (1 = mask). 

Data Buffer Register. This register contains 
the data to be read from or written to the 
FIFO buffer. 

Byte Count Register. This is a read-only 
register, containing the byte count for the 
FIFO buffer. The byte count is derived by sub- 
tracting the number of bytes read from the buf- 
fer from the number of bytes written into the 
buffer. The count is "frozen" for an accurate 
reading by setting bit 6 (Freeze Status register) 
in Control Register I . This bit is cleared when 
the Byte Count register read is completed. 



© 



51 Ol 



NOTES: 

1. Data from master CPU - Z-FIO Port 2. 

2. Z-FIO Port 1 -DCP. 

3. DCP -RAM. 

4. RAM -Z-SCC. 

5. Z-SCC — data comm. line loop. 



2_t 



Figure 25. Typical Application: Node Controller 



347 



Registers 



Control Register 

Address: 0000 
(Read/Write) 

| D, 1 D 6 I D 5 ' D, j D; 0; | 0, | | 



Li: 



Li 



PORT 2 MODE 



= HT. JUST. ADDRESS (RJA) 

- <Bi)<Bo>* 

- Z-BUS CPU 

1 = NONZBUS CPU 

1 = 3-WIREHSIJO 

1 1 = INTERLOCKED HS 



- 1 = VECTOR INCLUDES STATUS (VISI 
■ 1 ■ NO VECTOR ON INTERRUPT (NV> 

- 1 = DISABLE LOWER DAISY CHAIN (DLC) 

- 1 ■ INTERRUPTS ENABLED (MIE) 



Control Register 1 

Address: 0001 
(Read/Write) 

| D, | D 6 | D; [ D, I 0] ; 0; [ D, I D | 

L 



1 = REQUEST/WAIT ENABLED 



■ 1 = START DMA ON BYTE COUNT 

- 1 = STOP DMA ON PATTERN MATCH 

■ 1 = MESSAGE MAILBOX REGISTER UNDER 

■ 1 = MESSAGE MAILBOX REGISTER FULL* 

■ 1 m FREEZE STATUS REGISTER COUNT 

■ NOT USED (MUST BE PROGRAMMED 01 



Control Register 2* 

Address: 1001 
(Read/Write) 

| D, I D 6 I P., I O, I O, I 0, D, D j 

u 



Li 



PORT 2 SIDE ENABLED 
1 = PORT 2 SIDE ENABLE 



Control Register 3 

Address: 1010 
(Read/Write) 

| 0, | d s Id s Id, I D 3 [d ; I D, [ D | 



Li 



PORT 2 SIDE-INPUT LINE* (PIN 33)** 
PORT 2 SIDE-OUTPUT LINE (PIN 32)"* 

- NOT USED (MUST BE PROGRAMMED 

. PORT 2 SIDE-OUTPUT LINE (PIN 30)" 

. DATA DIRECTION BIT 
1 = INPUT TO CPU 
= OUTPUT FROM CPU 

- = PORT 1 SIDE CONTROLS DATA 
1 = PORT 2 SIDE CONTROLS 

. = CLEAR FIFO BUFFER 



"ONLY WHEN PORT 2 IS AN UO PORT 



■HEAD ONLY BITS 



Figure 26. Control Registers 



Interrupt Status Register 

Address: 0010 
(Read/Write) 

| D/ D 6 i D, ' 0, D- ; D ; D/ pT j 

i NOT USED 

(MUST BE PROGRAMMED 0) 

' MESSAGE INTERRUPT PENDING (IP) 

' MESSAGE INTERRUPT ENABLE (IE) 

MESSAGE INTERRUPT UNDER SERVICE (IUS) 

IUS. IE, AND IP ARE WRITTEN USING 
THE FOLLOWING COMMAND: 

| | | NULL CODE 
_0_ _0_ J_ CLEAR IP A IUS 
_0_ _1_ _0_ SET IUS 

1 1 CLEAR IUS 
_J_ _0_ SET IP 

J_ _0_ T CLEAR IP 

1 1 SET IE 



Figure 27. Interrupt Status Registers 



348 



Registers 

(Continued) 



Interrupt Status Registe 

Address: 0011 
(Read/Write) 

| r ' 0* I Pi 0, ' 0] ' D; ' D, I d7| 



DATA DIRECTION CHANGE INTERRUPT . 

UNDER SERVICE (IUS) 
DATA DIRECTION CHANGE INTERRUPT - 

ENABLE (IE) 
DATA DIRECTION CHANGE INTERRUPT - 
PENDING (IP) 
1US. IE, AND IP ARE WRITTEN USING 
THE FOLLOWING COMMAND: 

NULL CODE 
CLEAR IP A IUS 
SET IUS 
CLEAR IUS 
SET IP 
CLEAR IP 
SET IE 
CLEAR IE 



L 



1 = PATTERN MATCH FLAG* 
. PATTERN MATCH INTERRUPT 
. PATTERN MATCH INTERRUPT 
. PATTERN MATCH INTERRUPT 

UNDER SERVICE (1<JS> 
- NOT USED 
(MUST BE PROGRAMMED 0) 



NULL CODE 
CLEAR IP & IUS 
SET IUS 
CLEAR IUS 
SET IP 
CLEAR IP 
SET IE 
CLEAR IE 



•READ ONLY BITS 



Interrupt Status Registe 

Address: 0100 
(Read/Write) 



E COUNT COMPARE INTERRUPT 
UNDER SERVICE (IUS) 

E COUNT COMPARE INTERRUPT 
ENABLE (IE) 
E COUNT COMPARE INTERRUPT 
PENDING (IP) 



NULL CODE 
CLEAR IP & IUS 
SET IUS 
CLEAR IUS 
SET IP 
CLEAR IP 
SET IE 
CLEAR IE 



UNDERFLOW ERROR* 
ERROR INTERRUPT PENDING (IP) 

ERROR INTERRUPT ENABLED (IE) 

ERROR INTERRUPT UNDER SERVICE (IUS) 

OVERFLOW ERROR' 

IUS. IE, AND IP ARE WRITTEN USING 
THE FOLLOWING COMMAND; 

NULL CODE 
CLEAR IP * IUS 
SET IUS 
CLEAR IUS 
SET IP 
CLEAR IP 
SET IE 
CLEAR IE 



'READ-ONLY BITS 



Interrupt Status Register 3 

Address: 0101 
(Read/Write) 



D. D, D, D, D, D, Do 



FULL INTERRUPT UNDER SERVICE (IUS) 
FULL INTERRUPT ENABLE (IE) 
FULL INTERRUPT PENDING (IP) 



NULL CODE 
CLEAR IP & IUS 
SET IUS 
CLEAR IUS 
SET IP 
CLEAR IP 
SET IE 
CLEAR IE 



BUFFER EMPTY* 
EMPTY INTERRUPT PENDING (IP) 

- EMPTY INTERRUPT ENABLE (IE) 

- EMPTY INTERRUPT UNDER SERVICE (IUS) 

- BUFFER FULL* 



NULL CODE 
CLEAR IP & IUS 
SET IUS 
CLEAR IUS 
SET IP 
CLEAR IP 
SET IE 
CLEAR IE 



Figure 27. Interrupt Status Registers (Continued) 



349 



I I I I I I I 

REFLECTS NUMBER OF BYTES IN BUFFER 

Figure 28. Byte Count Register 



VECTOR STATUS 



_L 



NO INTERRUPTS PENDING 
BUFFER EMPTY 
BUFFER FULL 
OVER' UNDERFLOW ERROR 
BYTE COUNT MATCH 
PATTERN MATCH 
DATA DIRECTION CHANGE 
MAILBOX MESSAGE 



Figure 29. Interrupt Vector Register 



Pattern Match Register 


Pattern Mask Register 


Address: 1101 


Address: 1110 


(Read/Write) 


(Read/Write) 


| D r | D„ [ D & | D, | Dj | D, | D, [ Do | 


[ D, | D B | D 5 [ t Oj D a j D, D„ | 


1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 


STORES BYTE COMPARED WITH 


IF SET. BITS 0-7 MASK BITS 0-7 


BYTE IN DATA BUFFER REGISTER 


IN PATTERN MATCH REGISTER. 




MATCH OCCURS WHEN ALL 
NON MASKED BITS AGREE 


Figure 30. Pattern Match Register 






Figure 31. Pattern Mask Register 



Data Buffer Register 

Address: 1111 
(Read/Write) 

|d,|d,[d,|d,|d,|d ; |d,|d,| 

I I I M I I I 

CONTAINS THE BYTE TRANSFERRED 
TO OR FROM FIFO BUFFER RAM 

Figure 32. Data Buffer Register 



Byte Count Comparison Register 

Address: 1000 
(Read/Write) 



| D, | D. | D, | D, | P. | D z | D, | D, | 

I I I I I I 1 I 
CONTAINS VALUE COMPARED TO BYTE COUNT 
REGISTER TO ISSUE INTERRUPTS ON MATCH 
(BIT 7 ALWAYS 0.) 

Figure 33. Byte Count Comparison Register 



Message Out Register 

Address: 1011 
(Read/Write) 

[d7| D. [ D, ] D. | D, | D, | D, [ D, | 

STORES MESSAGE SENT TO MESSAGE 
IN REGISTER ON OPPOSITE PORT OF FIO 

Figure 34. Message Out Register 



Message In Register 

Address: 1100 
(Read Only) 

| D, | D, [ D, 1 D. | D, 1 D, ] D,7d71 
I I I I I I I I 



OUT REGISTER ON OPPOSITE PORT OF CPU 

Figure 35. Message In I 



Absolute Voltages on all pins with respect 

Maximum to GND - . 3V to + 7 . OV 

Ratings Operating Ambient 

Temperature See Ordering Information 

Storage Temperature - 65 °C to + 1 50 °C 



Stresses greater than those listed under Absolute Maxi- 
mum Ratings may cause permanent damage to the device. 
This is a stress rating only; operation of the device at any 
condition above those indicated in the operational sections 
of these specifications is not implied. Exposure to absolute 
maximum rating conditions for extended periods may affect 
device reliability. 



Standard The DC characteristics and capacitance sec- 

Test tions below apply for the following standard test 

Conditions conditions, unless otherwise noted. All voltages 

are referenced to GND. Positive current flows 

into the referenced pin. 

Standard conditions are as follows: 

■ +4.75 V < V cc < +5.25 V 

■ GND = V 

■ Ta as specified in Ordering Information 




FROM OUTPUT c 
UNDER TEST 



Standard Test Load 



Open-Drain Test Load 



DC 

Charac- 
teristics 


Symbol 


Parameter 


Min 


Max 


Unit 


Condition 


V,H 


Input High Voltage 


2.0 


Vcc + 0.3 


V 






V,L 


Input Low Voltage 


-0.3 


0.8 


V 






V OH 


Output High Voltage 


2.4 




V 


I OH = - 250 fiA 




Vol 


Output Low Voltage 




0.4 
0.5 


V 
V 


I OL = + 2.0 mA 
I OL = +3.2 mA 






Input Leakage 


-10.0 


+ 10.0 


piA 


0.4 £ V [N £ +2.4V 




hi 


Output Leakage 


-10.0 


+ 10.0 


nA 


0.4 < V OUT < +2.4V 






Mode Pins Input Leakage 
(Pins 19 and 21) 


-100 


+ 10.0 





o<v IN <v cc 




*CC 


V cc Supply Current 




200 


mA 






v cc = sv ± : 


°/o unless otherwise specified, over 


specified temperature range. 






Capacitance 


Symbol 


Parameter 


Min 


Max 


Unit 


Condition 




C IN 


Input Capacitance 




10 


pf 






C OUT 


Output Capacitance 




15 


pf 






c i/o 


Bidirectional Capacitance 




20 


pf 






Unmeasured pins returned to ground. 










Inputs 


tr 


Any Input Rise Time 




100 


ns 






ti 


Any Input Fall Time 




100 


ns 





f = 1 MHz, over specified temperature range. 



351 



AC Characteristics 



No. Symbol 



Parameter 



4 MHz 

Min Max 



6 MHz 
Min Max 



Notes*t 



1 

2 
3 
4 

5- 

6 

7 

8 

9 

lO- 
ll 
12 
13 
14 
15- 
16 
17 
18 
19 



TwAS 
TsA(AS) 
ThA(AS) 
TsCSO(AS) 

- ThCSO(AS) - 
TdAS(DS) 
TsA(DS) 
TsRWR(DS) 
TsRWW(DS) 

-TwDS 

TsDW(DSf) 
TdDS(DRV) 
TdDSf(DR) 
ThDW(DS) 

- TdDSr(DR) — 
TdDS(DRz) 
ThRW(DS) 
TdDS(AS) 
Trc 



AS Low Width 
Address to AS 1 Setup Time 
Address to AS 1 Hold Time 
CS to AS t Setup Time 
CS to AS 1 Hold Time - 
AS 1 to DS I Delay 
Address to DS I (with AS t to DS I 
R/W (Read) to DS I Setup Time 
R/W (Write) to DS I Setup Time 
■ DS Low Width 



60 ns) 



Write Data to DS 1 Setup Time 
DS (Read) I to Address Data Bus Driven 
DS I to Read Data Valid Delay 
Write Data to DS I Hold Time 

■ DS 1 to Read Data Not Valid Delay 

DS t to Read Data Float Delay 

R/W to DS 1 Hold Time 

DS t to AS I Delay 

Valid Access Recovery Time 



70 
30 
SO 

60 
60 
120 
100 


■390 ■ 
30 


30 
— 0- 



55 
50 
1000 



250 



70 



50 
10 
30 


40 
40 
100 
80 



■250 
20 


20 
— • 



40 
25 
650 



180 



45 



NOTES: 

1 . Parameter does not apply to Interrupt Acknowledge transactions. 

2. Float delay is measured to the time when the output has 
changed 0.5V from steady state with minimum ac load and 
maximum dc load. 



3. This is the delay from DS of one FIO access to DS of another FIO 

access (either read or write). 
* All timing references assume 2.0V for a logic "1" and 0.8V for 

a logic "0". 
t Units in nanoseconds (ns). 




Figure 36. Z-BUS CPU Interface liming 



AC Characteristics 



No. Symbol 



Parameter 



4 MHz 
Min Max 



6 MHz 
Min Max 



Notes t 



20 TsIA(AS) 

21 ThlA(AS) 

22 TsDSA(DR) 

23 TwDSA 

24 TdAS(IEO)- 

25 TdlEI(IEO) 

26 TsIEI(DSA) 

27 ThlEI(DSA) 

28 TdDS(INT) 

29 TdDCST 



INTACK to AS I Setup Time 



INTACK to AS 1 Hold Time 

DS (Acknowledge) 1 to Read Data Valid Delay 

DS (Acknowledge) Low Width 




250 



390 



•AS 1 to IEO 1 Delay (INTACK Cycle) - 
IEI to IEO Delay 

IEI to DS (Acknowledge) 1 Setup Time 
IEI to DS (Acknowledge) t Hold Time 



100 
50 



DS (INTACK Cycle) to INT Delay 
Interrupt Daisy Chain Settle Time 



250 

-350- 
150 

900 




250 

250 



70 
30 



180 

-250- 
100 

800 



NOTES: 

4. The parameters for the devices in any particular daisy chain 
must meet the following constraint: The delay from AS to DS 
must be greater than the sum of TdAS(IEO) for the highest 
priority peripheral, TsIElCDSA} for the lowest priority peripheral 



and TdlEKIEO) for each peripheral, separating them in the 
chain. 



t Units in nanoseconds (ns). 



ADq-ADt y undefined 



INTACK 




Figure 37. Z-BUS CPU Interrupt Acknowledge Timing 



AC Characteristics 



No. Symbol 



Parameter 



4 MHz 

Min Max 



6 MHz 
Min Max 



Notes t 



30 TdMW(INT) 

31 TdDC(INT) 

32 TdPMW(INT) 

33 TdPMR(INT) 
34 TdSC(INT) — 

35 TdER(INT) 

36 TdEM(INT) 

37 TdFL(INT) 

38 TdAS(INT) 



Message Write to INT Delay 
Data Direction Change to INT Delay 
Pattern Match to INT Delay (Write Case) 
Pattern Match (Head Case) to INT Delay 

-Status Compare to INT Delay 

Error to INT Delay 
Empty to INT Delay 
Full to TNT Delay 
ASlolNT Delay 



NOTES: 

5. Write is from the other side of FIO. 

6. Write can be from either side, depending on programming 
of FIO. 



WRITE 
REGISTER 



T Units equal to AS Cycles + ns. 



Bi' 



X 



-®- 



-®- 



READ DATA DS 
BUFFER — 
REGISTER 



-®- 



STATUS WRITE OR READ DS* 
DATA BUFFER 
REGISTER 



-<Sh 



X 



-®- 



a DATA DS* 
FER 
REGISTER 



-®- 



WRITE DATA DS* 

BUFFER 

REGISTER 



-®- 



-®- 



Figure 38. Z-BUS Interrupt Timing 



354 



AC Characteristics 

No. Symbol Parameter 



4 MHz 6 MHz 

Min Max Min Max Notes f 



1 


TdDS(WAIT) 


2 


TdDSl(WAIT) 


3 


TdACK(WAIT) 


4 — 


TdDS(REQ) 


5 


TdDMA(REQ) 


6 


TdDSl(REQ) 


7 


TdACK(REQ) 


8 — 


TdSU(DMA) 


9 


TdH(DMA) 


10 


TdDMA(DR) 


11 


TdDMA(DRH) 


12 


TdDMA(DR2) 


NOTES: 



AS 1 to WAIT 1 Delay 
DS1 I t o W AIT 1 D elay 
ACKIN I to WAIT t Delay 

PS I to R EQ I Dela y ~- 

DMASTB J_to REQ I Delay 
DS1 I t o RE Q I D elay 
ACKIN ) to REQ I Delay 
Data Setup Time to DMASTB - 
Data Hold Time to DMASTB 
DMASTB 1 to Valid Data 
DMASTB 1 to Data Not Valid 
DMASTB t to Data Bus Float 



190 
1000 
1000 
-350- 

350 
1000 
1000 



■200- 
30 



-150 - 
20 



150 



70 



160 
1000 
1000 
-300- 
300 
1000 
1000 



100 



45 



1. The delay is from DAV for 3- Wire Input Handshake. The delay 
is from DAC lor 3- Wire Handshake. 



T Units in nanoseconds (ns). 



DS1 

READAWRITE OATA 
BUFFER REGISTER BY 
OTHER SIDE 




Figure 39. Z-BUS Request/Wait Timing 



AC Characteristics 

4 MHz 6 MHz 

No. Symbol Parameter Min Max Min Max Notes*t 

1 TdDSQ(AS) Delay from PS 1 toAS I for No Reset 40 20 

2 TdASQ(DS) Delay for AS I to DS_I for NoReset 50 30 

3 Tw(AS + DS) Minimum Width of AS and DS Both Low for Reset. 500 350 1 



NOTES: 

1 . Internal circuitry allows for the reset provided by the Z8 (DS 

held Low while AS pulses) to be sufficient. t Units in nanoseconds (ns). 




Figure 40. Z BUS Reset Timing 



2 
3 

4 - 

5 
6 
7 

8- 

9 
10 
11 
12- 
13 
14 
15 
16 ■ 
17 
19 
20 



TsA(WR) 
ThA(RD) 

-ThA(WR) — 
TsCEI(RD) 
TsCEI(WR) 
ThCEI(RD) 

-ThCEI(WR)- 
TsCEh(RD) 
TsCEh(WR) 
TwRDl 

-TdRD(DRA) - 
TdRDf(DR) 
TdRDr(DR) 
TdRD(DRz) 

-TwWRl 

TsDW(WR) 

Trc(WR) 

Trc(RD) 



Address Setup to WR I 
Address Hold Time to RD I 

-Address Hold Time to WR t - 
CE Low Setup Time to RD 
CE Low Setup Time to WR 
CE Low Hold Time to RD 

- CE Low Hold Time to WR — 



CE High Setup Time to RD 
CE High Setup Time to WR 
RD Low Width 

- RD I to Read Data Active Delay 

RD I to Valid Data Delay 

RD t to Read Data Not Valid Delay 
RD t to Data Bus Float 

- WR Low Width 



Data Setup Time to WR 

Write Valid Access Recovery Time 

Read Valid Access Recovery Time 



80 


— - 





— 0- 
100 
100 
390 

— 0- 



390 - 



1000 
1000 + WR n 



250 



70 



80 


— 0- 





— 0- 
70 
70 

250 

— ■ 



250- 


650 

650 + WR n 



180 



45 



NOTES: 

1 . Parameter does not apply to Interrupt Acknowledge transactions. 

2. Float delay is measured to the time the output has changed 0.5V from 
steady state with minimum ac load and maximum dc load. 



3. Recovery time equal to Trc(WR) -t- write pulse width of the opposite 
side. 

t Units in nanoseconds (ns). 




Do-Dr 

FIO WHITE 



<S>» 

DC 



^ @ 



Figure 41. Non-Z-BUS CPU Interface Timing 



RD, DS READ 



WR, DS WRITE 



f 



-©- 



-©- 



y 



j — \ 



-ff- 



-fS- 



Figure 42. Z-BUS/Non-Z-BUS Recovery Time 



356 



AC Characteristics 



No. Symbol 



Parameter 



4 MHz 
Min Max 



6 MHz 
Min Max 



Notest 



20 TdlEI(IEO) 

21 Tdl(IEO) 

22 TsIEI(RDA) 

23 TdRD(DR) 
24 TwRDl(IA)- 

25 ThlA(RD) 

26 ThIEKRD) 

27 TdRD(INT) 

28 TdDCST 



IEI to IEO Delay 
INTACK I to IEO I Delay 
IEI Setup Time to RD (Acknowledge) 
RD I to Vector Valid Delay 
-Read Low Width (Interrupt Acknowledge)- 



INTACK I to RD I Hold Time 

IEI Hold Time to RD 1 

RD I to INT I Delay 

Interrupt Daisy Chain Settle Time 



100 

-390- 
30 
20 

350 



150 
350 



250 



900 



70 

-250- 
20 
10 

250 



100 
250 

180 



800 



NOTES: 

4. The parameter for the devices in any particular daisy chain 
must mee t the tollowing constraint: The delay from 
INTACK 1 to RD I must be greater than the sum ot 
TdKIEO) lor the highest priority peripheral. TsIEKBD) 



for the lowest priority peripheral , and TdlEI(IEO) lor each 
peripheral separating them in the chain, 
t Units in nanoseconds (ns). 









VECTO 


3 E 








\ 




















' 


) 












! 
















Figure 43. Non-Z-BUS Interrupt Acknowledge Timing 



357 



AC Characteristics 

4 MHz 6 MHz 

No. Symbol Parameter Min Max Min Max Notes 



29 


TdMW(INT) 


Message Write to INT Delay 




30 


TdDC(INT) 


Data Direction Change to INT Delay 




31 


TdPMW(INT) 


Pattern Match (Write Case) to INT Delay 




32- 


— TdPMR(INT) 


-Pattern Match (Read Case) to INT Delay 




33 


TdSC(INT) 


Status Compare to INT Delay 




34 


TdER(INT) 


Error to INT Delay 




35 


TdEM(INT) 


Empty to INT Delay 




36 


TdFL(INT) 


Full to INT Delay 




37 


TdSO(INT) 


State to INT Delay 


600 



Note: Parameter values for numbers 
29 through 36 were left blank 
as they are software dependent. 



WRITE 
MESSAGE 

REGISTER 

OUT 



DATA WRITE 
DIRECTION CONTROL 
CHANGE REGISTER 3 



WRITE DATA WRS 
BUFFER 



PATTERN 
MATCH 



READ DATA 

BUFFER 

REGISTER 



STATUS WRITE OR READ WRS-'ORRDS' 
COMPARE DATA BUFFER 
REGISTER 



ERROR WRITE OR READ WRS 'ORRDS ? 
DATA BUFFER 



DATA 
FER 
REGISTER 



WRITE DATA 

BUFFER 

REGISTER 



-®- 



J 



-®- 



-®- 



-®- 



-®- 



-®- 



Figure 44. FIO Non-Z-BUS Interrupt Timing 



358 



AC Characteristics 



No. Symbol 



Parameter 



4 MHz 

Min Max 



6 MHz 
Min Max 



Notes t 



1 

2 

3 

4- 

5 

6 

7 

8- 

9 
10 
11 
12 



TdCE(WT) 

TdRDl(WT) 

TdACK(WT) 

-TdRD(REQ) — 
TdRDl(REQ) 
TdACK(REQ) 
TdDAC(RD) 

-TSU(WR) 

Th(WR) 
TdDMA 
TdDMA(DRH) 
TdDMA(DRZ) 



CE 1 to WAIT Active 



RD1 t or WR1 ! to WAIT Inactive 



ACKIN I to WAIT Inactive 
- RE) I or WR I to REQ Inactive - 
RD1 I or WR1 t to REQ Active 



ACKIN 1 to REQ Active 



DACK I to RD I or WR 1 
- Data Setup Time to WR — 
Data Hold Time to WR 
RD I to Valid Data 
RD I to Data Not Valid 
RD I to Data Bus Float 



100 
-200- 
30 



200 
1000 
1000 
-350- 
1000 
1000 



170 
1000 
1000 
- 300- 
1000 
1000 



80 



150 



70 



20 
100 

45 



NOTES: 

1 . The delay is from DAV I for 3- Wire Input Handshake. The 
delay is fro m DAC I for 3- Wire Output Handshake. 

2. Only when DACK is active. 



t Units in nanoseconds (ns). 



RDrWR 

READ/WRITE OF DATA 



WR,IRD, 

WRITE/READ OF DATA 
BUFFER REGISTER 
BY OTHER SIDE 



INPUT/OUTPUT PORT 



DATA FROM FIO 



DACK 



WR 



I 



-©- 



7~z 



Jf 



\ 



@ 



-©- 



-3>- 



-®- 



-H ® r— 



1 



FIO WRITE TO DATA 



/ 



Figure 45. Non-Z-BUS Request/Wait Timing 



359 



2 TdfiD(WR) Delay from RD I to WR I 

3 TwRD + WR Width of RD and WR, both Low for Reset 



100 
500 



70 
350 



NOTES: 

T Units in nanoseconds (ns). 




Figure 46. Non-Z-BUS Reset Timing 



AC Characteristics 

No. Symbol Parameter 



4 MHz 
Min Max 



6 MHz 
Min Max 



1 


TwCLR 


Width of Clear to Reset FIFO 


700 




700 




2 


TdOE(DO) 


Ol 1 to Data Bus Driven 




210 




210 


3 


TdOE(DRZ) 


OE t to Data Bus Float 




150 




150 


4 


TdCLR(ACK) 


CLEAR t to ACKIN 1 


800 




800 





NOTES: 

t Units in nanoseconds (ns). 



CLEAR 
INPUT 



t 



"©- 



f 



Figure 47. Port 2 Side Operation 



360 



AC Characteristics 

No. Symbol Parameter 



4 MHz 

Min Max 



6 MHz 
Min Max 



Notes t 



1 TsDI(ACK) 

2 TdACKf(RFD) 

3 TdRFDr(ACK) 
4 — TsDO(DAV) 

5 TdDAVf(ACK) 

6 ThDO(ACK) 

7 TdACK(DAV) 

8 — ThDI(RFD) 

9 TdRFDf(ACK) 
10 TdACKr(RFD) 



Data Input to ACKIN 1 to Setup Time 
ACKIN I to RFD 1 Delay 



RFD I to ACKIN 1 Delay 
-Data Out to DAV 1 Setup Time- 



DAV 1 to ACKIN I Delay 



Data Out to ACKIN Hold Time 
ACKIN 1 to DAV t Delay 
-Data Input to RFD 1 Hold Time- 



RFD I to ACKIN I Delay 



ACKIN I (DAV 1) to RFD ! Delay— Interlocked and 
3- Wire Handshake 



11 TdDAVr(ACK) DAV I to ACKIN 1 (RFD t) 
12 — TdACKr(DAV)— ACKIN I to DAV 1 

13 TdACKf(Empty) ACKIN I to Empty 

14 TdACKf(Full) ACKIN I to Full 

15 TcACK ACKIN Cycle Time 



50 




-50- 


50 







-0- 



1 



500 



500 



400 
-800- 



50 



-25- 

50 


— 0- 





500 



500 



400 






-0 800- 



1 



NOTES: 

t Units in nanoseconds (ns), except as noted. 
1 . Units in microseconds. 



■zx 



— ®~ 



/ 



r — \ 



Figure 48. 2-Wire Handshake (Port 2 Side Only) Output 




Figure 49. 2-Wire Handshake (Port 2 Side Only) Input 



361 



AC Characteristics 



No. Symbol 



Parameter 



4 MHz 
Min Max 



6 MHz 
Min Max 



Notes t 



1 

2 
3 

4- 
5 
6 
7 

8- 

9 
10 
11 
12- 
13 
14 
15 
16 



TsDKDAV) 
TdDAVIf(RFD) 
TdDAVf(DAC) 
-ThDI(DAC) 



TdDACIr(DAV) 
TdDAVIr(DAC) 
TdDAVIr(RFD) 

-TdRFDI(DAV) — 
TsDO(DAC) 
TdDAVOf(RFD) 
TdDAVOf(DAC) 

-ThDO(DAC) 

TdDACOr(DAV) 
TdDAVOr(DAC) 
TdDAVOr(RFD) 
TdRFDO(DAV) 



Data Input to DAV 1 Setup Time 
DAV I to RFD 1 Delay 
DAV 1 to DAC t Delay 

■Data In to DAC t Hold Time 

DAC I to DAV I Delay 
DAV 1 to DAC I Delay 
DAV I to RFD I Delay 

-RFD 1 to DAV 1 Delay 

Data Out to DAV I 
DAV t to RFD 1 Delay 
DAV I to DAC I Delay 
■Data Out to DAC I Hold Time — 
DAC t to DAV t Delay 
DAV t to DAC I Delay 
DAV I to RFD I Delay 
RFD I to DAV 1 Delay 



50 

500 
500 
-0 



500 
500 
-0 



400 



800 



50 

500 
500 
-0 



500 
500 
-0 



400 



800 



NOTES: 

t Units in nanoseconds (ns). 



PIN DAV 

\ 38 I INPUT 



I PIN I RFD 

\ 39 I OUTPUT 



PIN DAC 

\ 37 ' OUTPUT 



DATA VALID 



he*/ 



X 



- — © — -ft 



Figure 50. 3- Wire Handshake Input 




Figure 51. 3- Wire Handshake Output 



362 



Zilog 



Product Specification 



Z8060/Z8560 
FIFO Buffer Unit 



October 1988 



FEATURES 

■ Bidirectional, asynchronous data transfer capability. 

■ Large 1 28-bit-by-8-bit buffer memory. 

■ Two-wire, interlocked handshake protocol. 

■ Wire-ORing of empty and full outputs for sensing of 
multiple-unit buffers. 



GENERAL DESCRIPTION 

The Z8060/Z8560 First-ln First-Out (FIFO) Buffer Units 
consist of a 128-bit-by-8-bit memory, bidirectional data 
transfer and handshake logic. The structure of the FIFO unit 
is similar to that of other available buffer units. FIFO is a 
general-purpose unit; its handshake logic is compatible with 
that of other members of Zilog's Z8® and Z8000® Families. 

FIFOs can be cascaded end-to-end without limit to form a 
parallel 8-bit buffer of any desired length (in 128-byte 



■ 3-state data outputs. 

■ Connects any number of FIFOs in series to form buffer of 
any desired length. 

■ Connects any number of FIFOs in parallel to form buffer 
of any desired width. 



increments). Any number of single- or multiple-unit FIFO 
serial buffers can be connected in parallel to form buffers of 
any desired width (in 8-bit increments). 

The FIFO buffer units are available as 28-pin packages. 
Figures 1 and 2 show the pin functions and pin assignments, 
respectively, of the FIFO device. A block diagram is shown in 
Figure 3. 



DATA . 
BUS\ 



COMMON 
CONTROL 



0, 


I 

! - 


n, 




°5 A 


j * ° 5 


o« 


! D > 


°l 


I °3 


Dj zBoe 


>/Z8560 D, 
"° 


Di 9 


I 


Do 


I D„ 


ACKIN 


I ACKIN 


RFD/DAV 


{ RFD/DAV 


OUTPUT 


I OUTPUT 


ENABLE 


x ENABLE 


DIR UB 




FULL 




EMPTY 




CLEAR 





t t 



DATA 
BUS 



RFD/DAVa £ 

ackTna C 

FULL £ 
EMPTY £ 
OEa C 
DoA C 
D,A C 
D2A C 
D3A C 
D.A C 
D5A C 
DSA C 
0,. C 
GND 



i 

\ 

A I B 

28060/ 
Z8680 



+ 5V 

RFD/DAVs 
ACKINb 
CLEAR 
OIR A/B 

OEa 
Dob 
d,b 

D 2 B 
D3B 

o n 

D 5 B 

Dm 

D/8 



Figure 2. FIFO Pin Assignments 



363 



YL 



CONTROL 
AND 
STATUS 



\ CONTROL A 

/ LOQIC ^ 



\ CONTROL / \ 

j/ LOGIC ^ J 



CONTROL 
AND 
STATUS 



Figure 3. Functional Block Diagram 



PIN DESCRIPTIONS 



ACKIN. Acknowledge Input (input, active Low). This line 
signals the FIFO that output data has been received by 
peripherals or that input data is valid. 

CLEAR. Clear Buffer (input, active Low). When set to Low, 
this line causes all data to be cleared from the FIFO buffer. 

D -D 7 . Data Bus (inputs/outputs, bidirectional). These 
bidirectional lines are used by the FIFO to receive and to 
transmit data. 

DIR A/B. Direction Input A/B (input, two control states). A 
High on this line signals that input data is to be received at 
Port B. A Low on this line signals that input data is to be 
received at Port A. 

EMPTY. Buffer Status (output, active High, open-drain). A 
High on this line indicates that the FIFO buffer is empty. 



FULL. Buffer Status (output, active High, open-drain). A 
High on this line indicates that the FIFO buffer is full. 

OEA, OEB. Output E nable A, Output Enable B (inputs, 
active Low). When Low, OEA enables the bus drivers for Port 
A; when High, OEA causes the bus drivers to float to a 
high-impedance level. Input OEB contro ls the bus drivers 
for Port B in the same manner as OEA controls those for 
Port A. 

RFD/DAV. Ready-for-Data/Data Available (outputs RFD, 
active High; DAV active Low). RFD, when High, signals to 
the p eriph erals involved that the FIFO is ready to receive 
data. DAV, when Low, signals to the peripherals involved that 
FIFO has data available to send. 



FUNCTIONAL DESCRIPTION 

Interlocked 2-Wire Handshake. In interlocked 2-wire 
handshake operation, the action of FIFO must be 
acknowledged by the other half of the handshake before the 
next action can occur. In an Output Handshake mode, the 
FIFO indicates that new data is available only after the 
external device has indicated that it is ready for the data. In 
an Input Handshake mode, the FIFO does not indicate that it 
is ready for new data until the data source indicates that the 
previous byte of the data is no longer available, thereby 
acknowledging the acceptance of the last byte. This control 
feature allows the FIFO, with no external logic, to directly 
interface with the port of any CPU in the Z8 Family— a CIO, a 
UPC, an Z-FIO, or another FIFO. The timing for the input 
and output handshake operations is shown in Figures 4 and 
5, respectively. 

Resetting or Clearing the FIFO. The CLEAR input is used 
to initialize and clear the FIFO. A Low level on this input 
clears all data from the FIFO, allows th e EM PTY outpu t to g o 
High and forces both outputs RFD/DAV A and FSFD/DAV B 
High. A High level on CLEAR allows the data to transfer 
through the FIFO. 



Bidirectional Transfer Control. The FIFO has 
bidirectional data transfer capability under control of the DIR 
A/B input. When DIR A/B is set Low, Port A becomes input 
handshake and Port B becomes output handshake; data 
transfers are then made from Port A to Port B. Setting DIR 
A/B High reverses the handshake assignments and the 
direction of transfer. This bidirectional control is illustrated in 
Table 1 . 



Table 1. Bidirectional Control Function Table 





Port A 


Port B 




DIR A/B 


Handshake 


Handshake 


Transfer 





Input 


Output 


AtoB 


1 


Output 


Input 


B to A 



364 



The FIFO buffer must be empty before the direction of 
transfer is changed; otherwise, the results of the change will 
be unpredictable. If FIFO status is unknown when a transfer 
direction change is to be made, the recommended 
procedure is: 



(1) Force and hold CLEAR Low. 

(2) Set DIR A/B to the level required for the desired direction. 



(3) Force CLEAR High. 

Empty and Full Operation. The EMPTY and FULL output 
lines can be wire-ORed with the EMPTY and FULL lines of 
other FIFOs and Z-FIOs. This capability enables the user to 
determine the empty/full status of a buffer consisting of 
multiple FIFOs, Z-FIOs, or a combination of both. Table 2 
shows the various states of EMPTY and FULL. 

Table 2. Signals EMPTY and FULL Operation Table 



Number of 






Bytes in FIFO 


EMPTY 


FULL 





High 


Low 


1-127 


Low 


Low 


128 


Low 


High 



Interconnection Example. Figure 6 illustrates a simplified 
block diagram showing the manner in which FIFOs can be 
interconnected to extend a Z-FIO buffer. 

Output Enable Operation. The FIFO provides a separate 
Output Enable (OE) signal for each port of the buffer. An OE 
output is valid only when its port is in the Output Handshake 
mode. The control of this output function is shown in Table 3. 
Signal OE operates with lines DIR A/B. A High on a valid OE 
line 3-states its port's data bus but does not affect the 
handshake operation. A Low level on a valid OE enables the 
data bus outputs if its port is in the Output Handshake mode. 
Note that the handshake operation is unaffected by the 
Output Enable pin. 

Table 3. Output Control Function Table 



DIR A/B OE A OE B 



Function 






X 





Disable Port A Output 








Enable Port B Output 





X 


1 


Disable Port A Output 








Disable Port B Output 


1 





X 


Enable Port A Output 








Disable Port B Output 


1 


1 


X 


Disable Port A Output 








Disable Port B Output 



NOTE: X = Don't care. 



cx 



VALID DATA 



X 



X 



X 



/ \ r~ 

\ / \ r 



Figure 4. Two-Wire Interlocked Handshake Timing (input) 



zx 



X 



f 



DC 



— \ r 

^ r~ 



Figure 5. Two-Wire Interlocked Handshake Timing (output) 



365 



FULL 
EMPTY 



PORT 2 

Of 

Z8038/Z8538 

RFDIDAVb 



01 



CLEAR 
DATA DIR 



I 



I 



EMPTY FULL 



Z8060/Z8560 
FIFO 

ACKINj RFDJOAVb 



RFO/DAVa ACKINb 



0E a OE b 
CLEAR DIR A/B 



SYSTEM FULL 
SYSTEM ( 



EMPTY FULL 



ACKINa RFD/DAVb 



RFDIOAVa ACKINj 



oea OEb 
clear dir a/b 



DATA 
BUS 



HANDSHAKE 
SIGNALS 



• OUTPUT CONTROL 



SYSTEM CLEAR 
SYSTEM DIRECTION 



Figure 6. Typical Interconnection (Simplified Diagram) 



ABSOLUTE MAXIMUM RATINGS 

Voltages on all pins with respect 

toGND -0.3V to + 7V 

Operating Ambient 

Temperature See Ordering Information 

Storage Temperature - 65 °C to + 1 50 °C 



Stresses greater than those listed under Absolute Maximum Ratings may 
cause permanent damage to the device. This is a stress rating only; 
operation of the device at any condition above those indicated in the 
operational sections of these specifications is not implied. Exposure to 
absolute maximum rating conditions for extended periods may affect 
device reliability. 



STANDARD TEST CONDITIONS 

The AC characteristics and capacitance sections listed 
below apply for the following standard test conditions, unless 
otherwise noted. All voltages are referenced to GND (OV). 
Positive current flows into the referenced pin. 

Standard conditions are as follows: 



■ + 4.75V <Vcc< + 5.25V 

■ GND = 0V 

■ T A as specified in Ordering Information. All AC 
parameters assume a load capacitance of 50 pf max. 




Figure 7. Standard Test Load Figure 8. Open-Drain Test Load 

366 



DC CHARACTERISTICS 



Symbol 


Parameter 


Min 


Max 


Unit 


Condition 


V| H 


Input High Voltage 


2.0 


V C C + 0.3 


V 




% 


Input Low Voltage 


-0.3 


0.8 


V 




V H 


Output High Voltage 


2.4 




V 


l H = -250fiA 


Vol 


Output Low Voltage 




0.4 


V 


IrjL = 2.0 mA 








0.5 


V 


lOL = 3.2 mA 


IlL 


Input Leakage 




±10 


MA 


0.4 <V| N < 2.4V 




Output Leakage 




±10 


ma 


0.4 <V UT< 2.4V 


>cc 


Vcc Supply Current 




200 


mA 





NOTE: Vcc = + 5V + 5% unless otherwise specified over specified temperature range. 



CAPACITANCE 



Symbol 


Parameter 


Min 


Max 


Unit 


On 


Input Capacitance 




10 


pf 


Cout 


Output Capacitance 




15 


pf 


O/o 


Bidirectional Capacitance 




20 


Pf 


Input 










tr 


Any input rise time 




100 


ns 


tf 


Any input fall time 




100 


ns 



Over specified temperature range; f = 1 MHz. 
Unmeasured pins returned tp ground. 



367 



FIFO 2-Wire Handshake Timing. Timing for 2-wire 
interlocked handshake operation is shown in Figure 9. The 
symbol, description and values for the numbered 
parameters (Figure 9) are given in AC Characteristics. 

AC CHARACTERISTICS 



Number 


Symbol 


Parameter 


Mtn 


Max 


Units* 


1 


TsDKAChQ 


Data Input to ACKIN 4 to Setup ime 


50 




ns 


2 


TdACKf(RFD) 


ACKIN 1 to RFD I Delay 




500 


ns 


3 


TriRFrWAPlO 
lunr ui \r\\ji\f 


RFH t tn APKIN 1 nplav 


o 




ns 


4 


TsDO(DAV) 


Data Out to DAV I Setup Time 


50 




ns 


5 


TdDAVf(ACK) 


DAV i to ACKIN i Delay 







ns 


6 


ThDO(ACK) 


Data Out to ACKIN t Hold Time 


50 




ns 


7 


TdACK(DAV) 


ACKIN J to DAV t Delay 




500 


ns 


8 


ThDI(RFD) 


Data Input to RFD I Hold Time 







ns 


9 


TdRFDf(ACK) 


RFD J to ACKIN t Delay 







ns 


10 


TdACKr(RFD) 


ACKIN t to RFD t Delay 




400 


ns 


11 


TdDAVr(ACK) 


DAV t to ACKIN t 







ns 


12 


TdACKr(DAV) 


ACKIN t to DAV i 




800 


ns 


13 


TdACKINf(EMPTY) 


(Input) ACKIN J to EMPTY i Delay 












(Output) ACKIN i to EMPTY t Delay 




600 


ns 


14 


TdACKINf(FULL) 


(Input) ACKIN J to FULL t Delay 












(Output) ACKIN J to FULL i Delay 




600 


ns 


15 


ACK IN Clock Rate 


(Input or Output) 




1.0 


MHz 


16 


TdACKINf(DAVf) 


(Bubble Time) 




1000 


ns 


17 


TwCLR 


Width of Clear to Reset FIFO 


700 




ns 


18 


TdOE(DO) 


OEito Data Bus Driven 




210 


ns 


19 


TdOE(DRZ) 


OE t to Data Bus Float 




150 


ns 


20 


TdCLR(ACK) 


CLEAR t to ACKIN i 




800 


ns 



■All timing references assume 2.0V for a logic 1 and 0.8V for a logic 0. Timings are preliminary and subject to change. 



369 



Zilog 



Product Specification 



Z8068 Z9518Z-DCP 
Data Ciphering Processor 



October 1988 



Features ■ Encrypts and decrypts data using the 

National Bureau of Standards encryption 
algorithm. 

■ Supports three standard ciphering modes: 
Electronic Code Book, Chain Block and 
Cipher Feedback. 

■ Three separate registers for encryption, 
decryption, and master keys improve system 



security and throughput by eliminating fre- 
quent reloading of keys. 

Three separate programmable ports (master, 
slave, and key data) provide hardware 
separation of encrypted data, clear data, 
and keys. 

Data rates greater than 1M bytes per second 
can be handled. 

Key parity check. 



General The Z8068 / Z9518 Data Ciphering Processors 

Description (DCP) are n-channel, silicon-gate LSI devices, 
which contains the circuitry to encrypt and de- 
crypt daya using national Bureau of Standards 
encryption algorithms. It is designed to be used in 
a variety of environments, including dedicated 
controllers, communication concentrators, termi- 
nals, and peripheral task processors in general 
processor systems. 

The DCP provides a high throughput rate using 
Cipher Feedback, Electronic Code Book, or Ci- 
pher Block Chain operating moces. The provi- 
sions of separate ports for key input, clear data, 
and enciphered data enhances security. 



MASTER PORT 
CONTROL 



SLAVE PORT 
CONTROL 



MCS 
MAS 
MDS 
MRfW 
MFLG 

SCS 



ASTS 
AFLG 

AUXo 
AUX t 

AUX;. 

AUX 3 
AUX« 
AUX S 
AUX G 
AUXt 



WPS 
MPt 
mp v 
MP- 
MP, 

I 

SP? 
SPi 
SPi 

sp, 

SP., 
SP, 

sp. 

SP, 



TTTT 



MASTER 
PORT 

(ADDRESS' 
DATA) 



} PORT 
IDATA) 



CONTROL/ KEY 



The host system communicates with the DCP 
using commands entered in the master port or 
through auxiiliary control lines. Once set up, data 
can flow through the DCP at high speeds because 
input, output and ciphering activities can be per- 
formed concurrently. External DMA control can 
easily be used to enhance throughput in some 
system configurations. 

The Z8068 and Z9518 DCP are designed to inter- 
face directly to Zilog's Z-BUS® . Device signal/ 
pin functions are shown in Figure 1; actual pin 
number assignments are shown in Figure 2. 




Figure 1 . Pin Functions 



(DIP) Pin Assignments 



370 



Some of the material used herein is used by permission of Advanced Micro Devices, Inc. 



Pin AFLG. Auxiliary Port Flag (output, active 

Descriptions Low). This output signal indicates that the DCP 
is expecting key data to be entered on pins 
AUX0-AUX7. This can occur only when C/K is 
Low and a "Load Key Throu gh AUX Port" 
command has been entered. AFLG remains 
active (Low) during the input of all eight bytes 
and will go inactive with the leading edge of 
the eighth strobe (ASTB). 



ASTB. Auxiliary Port Strobe (input, active 
Low). In Multiplexed Contr ol mod e (C/K Low), 
the rising (trailing) edge of ASTB strobes the 
key data on pins AUX0-AUX7 into the 
appropriate int ernal k ey register. This input is 
ignored unless AFLG and C/K are both Low. 
One byte of key data is entered on each ASTB 
with the most significant byte entered first. 

AUX0-AUX7. Auxiliary Port Bus (bidirectional, 
active High). When the DCP is_ operated in 
Multiplexed Control mode (C/K Low), these 
eight lines form a key-byte input port, which 
can be used to enter the master and session 
keys. This port is the only path available for 
entering the master key. (Session keys can also 
be entered via the master port.) AUXo is the 
low-order bit and is considered to be the parity 
bit in key bytes. The most significant byte is 
entered first. 

When the DCP is operated in Direct Control 
mode (C/K High), the auxiliary port's key- 
entry function is disabled and five of the eight 
lines become direct control/status lines for 
interfacing to high-speed microprogrammed 
controllers. In this case, AUXo, AUXj and 
AUX4 have no function, and the other pins are 
defined as follows: 

AUX2-BSY. Busy (output, active Low). This 
status output gives a hardware indication that 
the ciphering algorithm is in operation. 
AUX 2 -BSY is driven by the BSY bit in the 
Status register s uch that when the BSY bit is 1 
(active), AUX 2 -BSY is Low. 

AUX3-CP. Command Pending (output, active 
Low). This status output gives a hardware 
indication that the DCP is ready to accept the 
input of key bytes following a Low-to-High 
transition on AUX7-K/D. AUX3-CP is driven 
by the CP bit in the Status register such that 
when the CP bit is 1 (active), AUX3-CP is 
Low. 

AUXj-S/S. Start/Stop (input, Low = Stop). 
When this pin goes Low (Stop), the DCP 
follows the normal Stop command sequence. 
When this pin goes High, a sequence 
equivalent to a Start Encryption or Start 
Decryption command is followed. When 
AUX5-S/S goes High, the level on AUXg-E/D 
selects either the start encryption or start 
decryption operation. 

AUX6-E/D. Encrypt/Decrypt (input, 

Low = Decrypt). When AUX5-S/S goes High, 



it initiates a normal data ciphering operation 
whose input specifies whether the ciphering 
algorithm is to encrypt (E/D High) or decrypt 
(E/D Low). 

When AUX7-K/D goes High, initiating the 
entry of key bytes, the level on AUXg-E/D 
specifies whether the bytes are to be written 
into the E Key register (E/D High) or the D key 
Register (E/D Low). 

The AUXg-E/D input is not latched internally 
and must be held constant whenever one or 
more of JWX5-S/S, AUX7-K/D, AUX 2 -BSY, or 
AUX3-CP are active. Failure to maintain the 
proper level on AUXg-E/D during loading or 
ciphering operations results in scrambled data 
in the internal registers. 

AUX7-K/D. Key/Data (input, Low = Data). 
When this signal goes High, the DCP initiates 
a key-data input sequence as if a Load Clear E 
or D Key Through Master Port command had 
been entered. The level on AUXg-E/D deter- 
mines whether the subsequently entered clear- 
key bytes are written into the E key register 
(E/D High) or the D key register (E/D Low) 

AUX7-K/D and AUX5-S/S are mutually 
exclusive control lines; when one goes active 
(High), the other must remain inactive (Low) 
until the first returns to an inactive state. In 
addition, both lines must be inactive (Low) 
whenever a transition occurs on C/K (entering 
or exiting Direct Control mode). 

C/K. Control/Key Mode Control, (input, 
Low = Key). This input determines the 
operating characteristics of the DCP. A Low 
input on C/K puts the DCP into the Multiplex- 
ed Control mode, enabling programmed 
access to internal registers through the master 
port and enabling input of keys through the 
master or auxiliary port. A High input on C/K 
specifies operation in Direct Control mode. In 
this mode, several of the auxiliary port pins 
become direct control status signals which can 
be driven/sensed by high-speed controller 
logic, and access to internal registers through 
the master port is limited to the Input or Out- 
put register. 

CLK. Clock (input, TTL compatible). An exter- 
nal timing source is inpu t via t he C LK pin. 
The Data Strobe signals (MDS, SDS) must 
change synchronously with this cl ock in put, as 
must Master Port Address Strobe (MAS) in 
Multiplexed Control mod_e (C/K Low), and also 
AUX7-K/D and AUX5-S/S in Direct Control 
mode (C/K High). In addition, the A uxiliar y, 
Master and Slave P ort Flag outputs (AFLG, 
MFLG, and SFLG) change synchronously with 
the clock. When using the DCP with the Z8000 
CPU in Multiplexed Control mode, the clock 
input must agree in frequency and phase with 
the processor clock; however, the DCP does 
not require the high voltage levels of the pro- 
cessor clock. 



371 



Pin MAS. Master Port Address Strobe (input, 

Descriptions active Low). In Multiplexed Control mode 
(Continued) (C/K Low), an active (Low) signal on this pin 
indicates the presence of valid address and 
chip select information at the master port. This 
information is latched internally on t he ris ing 
edge of Master Port Address Strobe (MAS). 
When C/K is High (Direct Control mode), 
MAS can be High or Low without affecting 
DCP operation, except that, regardless of the 
state of C/K^ if both Master Port Add ress 
Strobe (MAS) and Data Strobe (MDS) are Low 
simultaneously, the DCP Mode register will be 
reset to ECB mode. The master port is 
assigned to clear data, the slave port is 
assigned to enable data, and all flags remain 
inactive. 

MCS. Master Port Chip Select (input, active 
High). This signal is used to select the master 
port. In Mul tiplex ed Control mode (C/K Low), 
the level on MCS is latched internally on the 
rising edge of Master Port Address Strobe 
(M AS). This latched le vel is retained as long 
as MAS is High; when MAS is Low, the latch 
becomes i nvisib le and the internal signal 
follows the MCS input. In Direct Control mode 
(C/K High), no latching of Maste r Port Chip 
Select occurs; the level on MCS is passed 
directly to the internal select circuitry, 
regard less of the state of Address Strobe 
(MAS). 

MDS. Maste r Por t Data Strobe (input, active 
Low). When MDS is active and Master Port 
Chip Select (MCS) is valid, it indicates that 
vali d data is present on MP0-MP7 during out- 
put. M DS and Master Port Address Strobe 
(MAS) are normally mutually exclusive; if both 
go Low simultaneously, the DCP is reset to 
ECB mode and all flags remain inactive. 

MFLG. Master Port Flag (output, active Low). 
This flag is used to indicate the need for a data 
transfer into or out of the master port during 
normal ciphering operation. Depending upon 
the control bits written to the Mode register, 
the master port is associated with either the 
Input register or the Output register. 

If data is to be transferred through the 
master port to the Input register, the MFLG 
reflects the contents of the Input register; after 
any start command is entered, MFLG goes ac- 
tive (Low) w henever the Input register is not 
full. MFLG is forced High by any command 
other than a start. Conversely, if the master 
port is associated with the Output register, 
MFLG reflects the contents of the Output 
registe r (except in single- port configuration). 
MFLG goes active (Low) whenever the Output 
regis ter is n ot empty. In single-port configura- 
tion, MFLG reflects the contents of the Input 
register, while the Slave Port Flag (SFLG) is 
associated with the Output register. 



MP0-MP7. Master Port Bus (input/output, 
active High). These eight bidirectional lines 
are used to specify internal register addresses 
in Multiplexed Control mode (see C/K) and to 
input and output data. The master port pro- 
vides software access to the Status, Command 
and Mode registers as well as the Input and 
Output registers. The 3-state master port out- 
puts are enabled only when the mast er por t is 
selected by Master Port Chip Select (MCS) 
being Low, with Master Port Read/Write 
(MR/W) High, and strob ed by a Low on the 
Master Port Data Strobe (MDS). MP is the 
low-order bit. Data and key information is 
entered into this port with most significant byte 
input first. 

MR/W. Master Port Bead/Write (input, 
Low = Write) . This signal indicates to the 
DCP whether the current master port operation 
is a read (MR/W is High) or a write (MR/W is 
Low), thereby indicating whether data is to be 
transferred from or to an internal register. 
MR/W is not latched internally and must be 
held s table while Master Port Data Strobe 
(MDS) is Low. 

PAR. Parity (output, active Low). The DCP 
checks all key bytes for correct (odd) parity as 
they are entered through either the master port 
(Multiplexed or Direct Control mode) or the 
auxiliary port (Multiplexed Control mode 
only). If any key byte contains even parity, the 
PAR bit in the Status register is set to 1 and 
PAR goes Low. The least significant bit of key 
bytes is the parity. 

SCS. Slave Port Chip Select (input, active 
Low). This signal is logi cally combined with 
Slave Port Data Strobe (SDS) to facilitate slave 
port data transfers in a bus environment. SCS 
is not latched internally and can be per- 
manently tied to Low without impairing slave 
port operation. 

SDS. Slave Port Data Stro be (in put, active 
Low). When both SDS and SCS are Low, it 
indicates to the DCP either that valid data is 
on the SP0-SP7 lines for an input operation, or 
that data is to be driven onto the SP0-SP7 lines 
for output. The direction of data flow is deter- 
mined by the control bits in the Mode register. 



SFLG. Slave Port Flag (output, active Low). 
This output indicates the status of either the 
Input register or the Output register, depen- 
ding on the control bits in th e Mod e register. 
In single-port configuration, SFLG goes active 
during normal processing whenever the Out- 
put registe r is no t empty. In dual-port con- 
figuration, SFLG reflects the content of 
whichever register is associated with the slave 
port. If the input register is assigned to the 
slave port, SFLG goes active whenever the 
Input register is not full, once any o f the start 
commands has been entered; SFLG is forced 



372 



Pin inactive if any other command is entered. If 

Descriptions the slave port is assigned to the Output 
(Continued) register, SFLG goes active whenever t he Ou t- 
put register is not empty. In this case, SFLG 
goes inactive if any command is aborted. 

SP0-SP7. Slave Port Bus (bidirectional). The 
slave port provides a second data input/output 
interface to the DCP, allowing overlapped 



input, output, and ciphering operations. The 
3-state slave port outpu ts are driven only when 
Slave Port Chip Select (SCS) and Slave Port 
Data Strobe (SDS) are both Low, SFLG is 0, 
and the internal port control configuration 
allows output to the slave port. SPrj is the low 
order bit. The most significant byte of data 
blocks is entered or retrieved through this port 
first. 



Functional The overall design of the DCP, as shown 

Description in Figure 3, is optimized to achieve high data 
throughput. Data bytes can be transferred 
through both the master and slave ports, and 
key bytes can be written through both the aux- 
iliary and master ports. Three 8-bit buses 
(input, output and C bus) carry data and key 
bytes between the ports and the internal 
registers. Three 56-bit, write-only key registers 
are provided for the Master (M) Key, the 
Encryption (E) Key and the Decryption (D) 
Key. Parity checking is provided on incoming 
key bytes. Two 64-bit registers are provided 
for initializing vectors (IVE and IVD) that are 
required for chained (feedback) ciphering 
modes. Three 8-bit registers (Mode, Command 
and Status) are accessible through the master 
port. 

Algorithm Processing. The algorithm pro- 
cessing unit of the DCP (Figure 3) is designed 
to encrypt and decrypt data according to the 
National Bureau of Standards' Data Encryption 
Standard (DES), as specified in Federal Infor- 
mation Processing Standards Publication 46. 
The DES specifies a method for encrypting 
64-bit blocks of clear data ("plain text") into 
corresponding 64-bit blocks of "cipher text." 



The DCP offers three ciphering methods, 
selected by the cipher type field of the Mode 
register: Electronic Code Book (ECB), Cipher 
Block Chain (CBC) and Cipher Feedback 
(CFB). These methods are implemented in 
accordance with Federal Information Process- 
ing Standards, Publication 46. 

Electronic Code Book (ECB) is a straightfor- 
ward implementation of the DES: 64 bits of 
clear data in, 64 bits of cipher text out, with no 
cryptographic dependence between blocks. 

Cipher Block Chain (CBC) also operates on 
blocks of 64 bits, but it includes a feedback 
step which chains consecutive blocks so that 
repetitive data in the plain text (such as ASCII 
blanks) does not yield repetitive cipher text. 
CBC also provides an error extension 
characteristic which protects against 
fraudulent data insertions and deletions. 

Cipher Feedback (CFB) is an additive 
stream cipher method in which the DES 
algorithm generates a pseudorandom binary 
stream, which is then exclusive-ORed with the 
clear data to form the cipher text. The cipher 
text is then fed back to form a portion of the 
next DES input block. The DCP implements 
8-bit cipher feedback, with data input, output, 



AFLG 




ASTB 


AUXILIARY 

PORT 
CONTROL 



INPUT REGISTER 




SLAVE PORT FLA Q 
SLAVE PORT 




Figure 3. 28068/29518 Block Diagram 



373 



me necessary registers to implement a 
multiple-key or master-key system. In such an 
arrangement, a single master key, stored in 
the DCP M key register, is used to encrypt ses- 
sion keys for transmission to remote DES 
eguipment and to decrypt session keys 
received from such equipment. The M Key 
register may be loaded (with plain text) only 
through the auxiliary port, using the Load 
Clear Master Key command. In addition to the 
M Key register, the DCP contains two session 
key registers: the E key register, used to en- 
crypt clear text, and the D key register, used 
to decrypt cipher text. All three registers are 
loaded by writing commands such as Load 
Clear E Key, through master port, into the 
Command register, and then writing the eight 
bytes of key data to the port when the Com- 
mand Pending bit in the Status register is 1 . 

Operating Modes: Multiplexed Control vs. 
Direct Control. The DCP can be operated in 
either of two basic interfacing modes, deter- 
mined by the logic level on the C/K input pin. 
In Multiplexed Control mode (C/K Low), the 
DCP is configured internally to allow a master 
CPU to address five of the internal con- 
trol/status/data registers directly, thereby con- 
trolling the device via mode and command 
values written to these registers. Also, in this 
mode, the auxiliary port is enabled for key- 
byte input. 

If the logic level on C/K is brought High, 
the DCP enters Direct Control mode, and the 
auxiliary port pins are converted into direct 
hardware status or control signals capable of 
instructing the DCP to perform a" functionally 
complete subset of its cipher processing at 
very high throughputs. This operating mode is 
particularly well suited for ciphering data for 
high-speed peripheral devices such as 
magnetic disk or tape. 

Data Flow. Bits M2 and M3 of the Mode 
register control the flow of data into and out of 
the DCP through the master and slave ports. 
Three basic configurations are provided: one 
single- port and two dual-port. 

Single-Port Configuration. The simplest con- 
figuration occurs when the Mode register con- 



is written to tne master port input register 
address. To facilita te mon itoring of the Input 
register status, the MFLG signal goes Low 
when the Input register is not full. Data is read 
by the master CPU through t he mas ter port 
Output register address. Pin SFLG goe s Low 
when the Output register is not empty. MFLG 
is then redefined as a master input flag and 
SFLG is redefined as a master output flag. 



COMMANDS 
ENCRYPT AND DECRYPT 
KEYS. CLEAR TEXT 
CIPHER TEXT 



Figure 4. Single-Port Configuration. Multiplexed Control 



I COMMANDS 
ENCRYPT AND DECRYPT 
KEYS CLEAR TEXT 



^CIPHER TEXT ^ ) 



PERIPHERAL 
DEVICE OR 
BUFFER 



Figure 5a. Dual-Port Configuration. Multiplexed Control 

Dual Port, Master Port Clear 
Configuration. In the dual-port configura- 
tions, both the master and slave ports are used 
for data entry and removal (Figures 5a and 
Sb). In the master port clear configuration, 
clear text for encryption can be entered only 
through the master port, and clear text 
resulting from decryption can be read only 
through the master port. Cipher text can be 
handled only through the slave port. The 
actual direction of data flow is controlled 
either by the encrypt/decrypt bit (M4) in the 
Mode register or by the Start Encryption or 
Start Decryption commands. If encryption is 
specified, clear data will flow through the 
master port to the Input register, and cipher 
data will be available at the slave port when it 
is ready to be read from the Output register. 
For decryption, the process is reversed, with 
cipher data written to the Input register 



HIGH SPEED 
MICROPROGRAMMED 

DEVICE 



PERIPHERAL 
DEVICE OR 
BUFFER 



Figure 5b. Dual-Port Configuration. Direct Control 



374 



Functional through the master port. Slave port and clear 

Description text read from the Master port. 

(Continued) In both dual-port configurations, the Master 
Port Fl ag (MFLG) and the Slave Port Flag 
(SFLG) are used to indicate the status of the 
data register associated with the master port 
and slave port, respectively. For example, dur- 
ing encryption in the master port clear con- 
figuration, MFLG goes Low (active) when the 
Input register is not full; SFLG goes Low 
(active) when the Output register is not empty. 
If cyph erin g oper ation changes direction, 
MFLG and SFLG switch their register associa- 
tion (see Table 1). 



Mode Register Bits 






Encrypt/ 


Port 




Input 


Output 


Decrypt Configuration 


Register 


Register 


Bit M4 


Bit M3 


Bit M2 


Flag 


Flag 











MFLG 


SFLG 








1 


SFLG 


MFLG 


0' 


1 





MFLG 


SFLG 


1 








SFLG 


MFLG 


1 





1 


MFLG 


SFLG 


1 


1 





MFLG ' 


SFLG 



Table 1. Association of Master Port Flag (MFLG) 
and Slave Port Flag (SFLG) 
with Input and Output Registers 

Dual Port. Slave Port Clear Configuration. 

This configuration is identical to the previously 
described dual-port, master port clear con- 
figuration except that the direction of cipher- 
ing is reversed. That is, all data flowing in or 
out of the master port is cipher text, and all 
data at the slave port is clear text. 

Master Port Read/Write Timing. The master 
port of the DCP is designed to operate directly 
with a multiplexed address/data bus such as 
the Zilog Z-BUS. Several features of the master 
port logic are: 

■ The level on Master Port Chip Select (MCS) 
is latched internally on the rising (tr ailing ) 
edge of Master Port Address Strobe (MAS). 
This action relieves external address decode 
circuitry of the responsibility for latching 
chip select at address time. 

■ The levels on MP; and MP2 are also latched 
internally on the rising edge of MAS and 
are subsequently decoded to enable reading 
and writing of the DCP's internal registers 
(Mode, Command, Status, Input and Out- 
put). This action also eliminates the need for 
external address latching and decoding. 

■ Data transfers through the master port are 
controlled by the levels a nd tr ansitions on 
Master Port Data Strobe (MDS) and Master 
Port Read/Write (MR/W). The former con- 
trols the timing and the latter controls the 
transfer direction. Data transfers disturb 
neither the chip-select nor address latches, 



so once the DCP and a particular register 
have been selected, any number of reads or 
writes of that register can be accomplished 
without intervening address cycles. This 
feature greatly speeds up the loading of 
keys and data, given the necessary transfer 
control external to the DCP. 

Loading Keys and Initializing Vector (IV) 
Registers. Because the key and Initializing 
Vector (IV) registers are not directly 
addressable through any of the DCP's ports, 
keys and vector data must be loaded (and in 
the case of vectors, read) via "command data 
sequences." Most of the commands recognized 
by the DCP are of this type. A load or read 
command is written to the Command register 
through the master port. The command pro- 
cessor responds by asserting the Command 
Pending output. The user then either writes 
eight bytes of key or vector data through the 
master or auxiliary port, as appropriate to the 
specific command, or reads eight bytes of vec- 
tor data from the master port. 

In Direct Control mode, only the E Key and 
D Key registers can be loaded; the M Key and 
IV registers are inaccessible. Loading the E 
and D Key registers is accomplished _by plac- 
ing the proper state on the AUXg-E/D input 
(High for E Key, Low for D Key) and then rais- 
ing the AUX7-K/D input — indicating that key 
loading is required. The command processor 
attaches the proper key re giste r to the master 
port and asserts the AUX3-CP (Command 
Pending) signal (active Low). The eight key 
bytes can then be written to the master port. In 
the Multiplexed Control mode, all key and 
vector registers can be written to and all but 
the Master (M) Key register can be loaded with 
encrypted, as well as clear, data. If the opera- 
tion is a Load Encrypt command, the subse- 
quent data written to the master or auxiliary 
port (as appropriate) is routed first to the Input 
register and decrypted before it is written into 
the specified key or Initializing Vector 
register. 

Parity Checking of Keys. Key bytes contain 
seven bits of key information and one parity 
bit. By DES designation, the low-order bit is 
the parity bit. The parity-check circuit is 
enabled whenever a byte is written to one of 
three key registers. The outp ut of the parity- 
check circuit is connected to PAR and the 
state of this signal is reflected in Status register 
bit PAR (S3). Status register bit PAR goes to 1 
whenever a byte with even parity (an even 
number of Is) is detected. In addition to the 
PAR bit, the Status register has a Latched Pari- 
ty bit (LPAR, S4) that is set to 1 whenever the 
Status register PAR bit goes to 1 . Once set, the 
LPAR bit is not cleared until a reset occurs or 
a new Load Key command is issued. 



375 



Functional When an encrypted key is entered, the 

Description parity-check logic operates only after the 
(Continued) decrypted key is available. Th e en crypted data 
is not checked for parity. The PAR signal 
reflects the state of the decrypted bytes on a 
byte-to-byte basis as they are clocked through 



the parity-check logic on their way to the k ey 
register. Thus, the time during which PAR 
indicates the status of a byte of decrypted key 
data may be as short as four clock cycles. The 
LPAR bit in the Status register indicates if any 
erroneous bytes of key data were entered. 



Program- Initialization. The DCP can be reset in 
ming several ways: 

■ By the "Software Reset" command. 

■ By a hardware reset , whi ch oc curs 
whenever uoth MAS and MDS go Low 
simultaneously. 

■ By writing to the Mode register. 

■ By aborting any command. 

These seguences initiate the same internal 
operations, except that loading the Mode 
register or aborting any command does not 
subseguently reset the Mode register. Once a 
reset process starts, the DCP is unable to 
respond to further commands for approximate- 
ly five clock cycles. If a power-up hardware 
reset is used, the leading edge of the reset 
signal should not occur until approximately 1 
ms after Vqc has reached normal operating 
voltage. This delay time is needed for internal 
signals to stabilize. 

Registers. The registers in the DCP that can 
be addressed directly through the master port 
are shown with their addresses in Table 2. A 
brief description of these registers and those 
not directly accessible follows. 



C/K 


MP2 


MP1 


MR/W MCS Register Addressed 





X 








Input Register 





X 





1 


Output Register 








1 





Command Register 








1 


1 


Status Register 





1 


1 


X 


Mode Register 


X 


X 


X 


X 


1 No Register Accessed 


1 


X 


X 





Input Register 


1 


X 


X 


1 


Output Register 



Table 2. Master Port Register Addresses 



Hex 
Code 



Command 



90 
91 
92 
11 
12 

Bl 
B2 
31 

32 

85 
84 
A5 
A4 

8D 
8C 
A9 
A8 

39 
41 
40 
CO 



Load Clear M Key Through Auxiliary Port 
Load Clear E Key Through Auxiliary Port 
Load Clear D Key Through Auxiliary Port 
Load Clear E Key Through Master Port 
Load Clear D Key Through Master Port 



Load Encrypted 
Load Encrypted 
Load Encrypted 
Load Encrypted 

Load Clear IVE 
Load Clear IVD 
Load Encrypted 
Load Encrypted 



E Key Through Auxiliary Port 
D Key Through Auxiliary Port 
E Key Through Master Port 
D Key Through Master Port 

Through Master Port 
Through Master Port 
IVE Through Master Port 
IVD Through Master Port 



Read Clear IVE Through Master Port 
Read Clear IVD Through Master Port 
Read Encrypted IVE Through Master Port 
Read Encrypted IVD Through Master Port 

Encrypt With Master Key 
Start Encryption 
Start Decryption 
Start 



E0 Stop 

00 Software Reset 



Table 3. Command Codes in Multiplexed Control Mode 

Command Register. Data written to the 8-bit, 
write-only Command register through the 
master port is interpreted as an instruction. A 
detailed description of each command is given 
in the Commands section; the commands 
and their hexadecimal representations are 
summarized in Table 3. A subset of these 
commands can be_entered implicitly in Direct 
Control mode (C/K High) — even though the 
Command register cannot be addressed in that 
mode — by transitions on auxiliary lines 
AUX 5 -S/S, AUXe-E/D, and AUX7-K/D. These 
implicit commands are summarized in Table 4. 



Pins 



C/K 


ATJX,-K/D 


AUXs-E/D 


AUXii-s/s 


Command Initiated 


H 


L 


L 


i 


Start Decryption 


H 


L 


H 


t 


Start Encryption 


H 


L 


X 


1 


Stop 


H 


1 


L 


L 


Load D Key Clear through master port 


H 


t 


H 


L 


Load E Key Clear through master port 


H 


i 


X 


L 


End Load Key command 


H 


H 


X 


H 


Not allowed 


L 


Data 


Data 


Data 


AUX pins become Key-Byte inputs 



Table 4. Implicit Command Sequences in Direct Control Mode 



376 



Program- Status Register. The bit assignments in the 
ming read-only Status register are shown in Figure 

(Continued) 6. The PAR, AFLG, SFLG and MFLG bits 

indicate the status of the corresponding output 
pins, as do the busy and command pending 
bits_when the DCP is in a Direct Control mode 
(C/K High). In each case, the output signal 
will be active Low when the corresponding 
status bit is a 1 . The parity bit indicates the 
parity of the most recently entered key byte. 
The LPAR bit indicates whether any key byte 
with even parity has been encountered since 
the last Reset or Load Key command. 

The Busy bit is 1 whenever the ciphering 
algorithm unit is actively encrypting or 
decrypting data, either as a response to a com- 
mand such as Load Encrypted Key (in which 
case the Command Pending bit is 1 ) or in the 
ciphering of regular text (indicated by the 
Start/Stop bit being 1). If the ciphered data 
cannot be transferred to the Output register 
because that register still contains output from 
a previous ciphering cycle, the Busy bit 
remains 1 even after the ciphering is complete. 
Busy is at all other times, even when cipher- 
ing is not possible because data has not been 
written to the Input register. 

The Command Pending bit is set to 1 by any 
command whose execution requires the 
transfer of data to or from a nonaddressable 
internal register, such as when writing key 
bytes to the E key register or reading bytes 
from the IVE register. Thus, the Command 
Pending bit is set following all commands ex- 



cept the three start commands, the Stop com- 
mand and the Software Reset command. The 
Command Pending bit returns to after all 
eight bytes have been transferred following 
Load Clear, Read Clear, or Read Encrypted 
commands; and after data has been transfer- 
red, decrypted, and loaded into the desired 
register following Load Encrypt commands. 

The Start/Stop bit is set to 1 when one of the 
start commands is entered and it is reset to 
whenever a reset occurs or when a new com- 
mand other than a Start is entered. 



| s, ! S, | S 5 | S« | Sj | S; [ s, | s, | 



MASTER PORT FLAG 

= INACTIVE 

1 = ACTIVE 

- SLAVE PORT FLAG 

- INACTIVE 

1 = ACTIVE 

■ AUXILIARY PORT FLAG 

= INACTIVE 

1 = ACTIVE 

■ PARITY (PAR) 

= ODD PARITY 

1 = EVEN PARITY 



ALL BYTES HAD 
ODD PARITY 
ONE OR MORE BYTES 
HAD EVEN PARITY 



- COMMAND PENDING 

- INACTIVE 

1 = ACTIVE 

• START/STOP 

= STOP ENTERED 

1 - START ENTERED 



Figure 6. Status Register Bit Assignments 



Mode Register. Bit assignments in this 5-bit 
read/write register are shown in Figure 7. The 
cipher type bits (Mi and Mo) indicate to the 
DCP which ciphering algorithm is to be used. 
On reset, the Cipher Type mode defaults to 
Electronic Code Book mode. 

Configuration bits (M3 and M2) indicate 
which data ports are to be associated with the 
Input and Output registers and flags. When 
these bits are set to the single-port, master- 
only configuration (M3 M2 = 10), the slave 
port is disabled a nd no manipulation of Slave 
Port Chip Select (SCS) or Slave Data Strobe 
(SDS) can result in data movement through the 
slave port; all data transfers are accomplished 
through the master port, as previously 
describ ed i n the F unctional Description. Both 
MFL G and SFLG are used in this configura- 
tion; MFLG gives the status of the Input 
register and SFLG gives the status of the Out- 
put register. 

When the configuration bits are set to one of 
the dual-port configurations (M3 M2 = 00 or 
01), both the master and slave ports are 
available for input and output. When M3, 
M2 = 01 (the default configuration), the 
master port handles clear data while the slave 
port handles encrypted data. Configuration 



M3, M2 = 00 reverses this assignment. Actual 
data direction at any particular moment is con- 
trolled by the Encrypt/Decrypt bit. 

The Encrypt/Decrypt bit (M4) instructs the 
DCP algorithm processor to encrypt or decrypt 
the data from the Input register using the 
ciphering method specified by the Cipher 
Type bits. The Encrypt/Decrypt bit also con- 
trols data flow within the DCP. For example, 
when the configuration bits are 0,1 (dual-port, 
master clear, slave encrypted) and the 
Encrypt/Decrypt bit is 1 (encrypt), clear data 
will flow into the DCP through the master port 
and encrypted data will flow out through the 
slave port. When the Encrypt/Decrypt bit is set 
to (decrypt), data flow is reversed. 



iMilMejMsjMalMa'.MzlMT-Mol 



• CIPHER TYPE 

00 = ELECTRONIC CODE BOOK (DEFAULT) 

01 = CIPHER FEEDBACK 

10 - CIPHER BLOCK CHAIN 

11 = RESERVED 

■ PORT CONFIGURATION 

00 = DUAL PORT, MASTER 

ENCRYPTED, SLAVE CLEAR 

01 = DUAL PORT, MASTER CLEAR. 

SLAVE ENCRYPTED (DEFAULT) 

10 = SINGLE PORT. MASTER ONLY 

11 • RESERVED 

■ ENCRYPTJDECRYPT 

1 = ENCRYPT 
= DECRYPT 



Figure 7. Mode Register Bit Assignments 



377 



Program- Input Register. The 64-bit, write-only Input 
ming register is organized to appear to the user as 

(Continued) eight bytes of pushdown storage. A status cir- 
cuit monitors the number of bytes that have 
been stored. The register is considered empty 
when the data stored in it has been or is being 
processed; it is considered full when one byte 
of data has been entered in Cipher Feedback 
mode or when eight bytes of data have been 
entered in Electronic Code Book or Cipher 
Block Chain mode. If the user attempts to write 
data into the Input register when it is full, the 
Input register disregards the attempt; no data 
in the register is destroyed. 

Output Register. The 64-bit, read-only Output 
register is organized to appear to the user as 
eight bytes of pop-up storage. A status circuit 
detects the number of bytes stored in the Out- 
put register. The register is considered empty 
when all the data stored in it has been read by 
the master CPU and is considered full if it still 
contains one or more bytes of output data. If a 
user attempts to read data from the Output 
register when it is empty, the buffers driving 
the output bus remain in a 3-state condition. 

M, E, D Key Registers. The following 
multibyte key registers cannot be addressed 
directly, but are loaded in response to com- 
mands written to the Command register. 



There are three 64-bit, write-only key 
registers in the DCP: the Master (M) Key 
register, the Encrypt (E) key register, and the 
Decrypt (D) key register. The Master key 
register can be loaded only with clear data 
through the auxiliary port. The Encrypt and 
Decrypt Key registers can be loaded in any of 
four ways: (1) as clear data through the aux- 
iliary port, (2) as clear data through the master 
port, (3) as encrypted data through the aux- 
iliary port, or (4) as encrypted data through 
the master port. In the last two cases, the 
encrypted data is first routed to the Input 
register, decrypted using the M Key, and final- 
ly written to the target key register from the 
Output register. 

Initializing Vector Registers (IVE and 
IVD). Two 64-bit registers are provided to 
store feedback values for cipher feedback and 
chained block ciphering methods. One initia- 
lizing vector register (IVE) is used during 
encryption, the other (IVD) is used during 
decryption. Both registers can be loaded with 
either clear or encrypted data through the 
master port (in the latter case, the data is 
decrypted before being loaded into the IV 
register), and both may be read out either 
clear or encrypted through the master port. 



All operations of the DCP result from com- 
mand inputs, which are entered in Multiplexed 
Control mode by writing a command byte to 
the Command register. Command inputs are 
entered in Direct Control mode by raising_and 
lowering J.he logic levels on the AUX7-K/D, 
AUXg-E/D, and AUX5-S/S pins. Table 3 shows 
all commands that can be given in Multiplexed 
Control mode. Table 4 shows a subset of the 
implicit commands that can be executed in the 
Direct Control mode. 

Load Clear M Key Through Auxiliary Port 
(90H). 

Load Clear E Key Through Auxiliary Port 
(91H). 

Load Clear D Key Through Auxiliary Port 
(92H). 

These commands may be used only for 
multiplexed operations; they override the data 
flow specifications set in the Mode register and 
cause the Master (M) Key, Encrypt (E) Key, or 
Decrypt (D) Key register to be loaded with 
eight bytes written to the auxiliary port. After 
the Load command is written to the Command 
register, the Auxiliary Port Flag (AFLG) goes 
active (Low) and the corresponding bit in the 
Status register (S2) becomes 1 , indicating that 
the device is able to accept key bytes at the 
auxiliary port pins. Additionally, the Com- 
mand Pending bit (Sg) becomes 1 during the 
entire loading process. 



Each byte is written to its respective key 
register by placing an active Low signal on the 
Auxiliary Port Strobe (ASTB) once data has 
been set up on the auxiliary port pins. The 
actual write proces s occurs on the rising (trail- 
ing) edge of ASTB. (See Switching Character- 
istics section for exact setup, strobe width, and 
hold times.) 

The Auxiliary Port Flag (AFLG) goes inac- 
tive immediately after the eighth strobe goes 
active (Low). However, the Command Pending 
bit (S6) remains 1 for several more clock 
cycles, until the key loading process is com- 
pleted. All key bytes are checked for correct 
(odd) parity as they are entered. 

Load Clear E Key Through Master Port 
(11H). 

Load Clear D Key Through Master Port 
(12H). 

These commands are available in both 
Multiplexed Control and Direct Control 
modes. They override the data flow specifica- 
tions set in the Mode register and attach the 
master port inputs to the Encrypt (E) Key or 
Decrypt (D) Key register, as appropriate, until 
eight key bytes have been written. In 
Multiplexed Control mode, the command is 
initiated by writing the Load command to the 
Command register. In Direct Control mode, 
the command is initiated by raising the 
AUX7-K/D control input while the AUX5-S/S 



378 



1 



Commands input is Low. In this latter case, the level on 
(Continued) AUXg-E/D determines which key register is 
written (High = E register). 

Once the command has been recognized, 
the Command Pending bit (Sg in the Status 
register) becomes 1 . In Direct Control mode, 
AUX3-CP goes active (Low), indicating that 
key entry may proceed. The host system then 
writes exactly eight bytes to the master port (at 
the Input register address in Multiplexed Con- 
trol mode). When the key register has been 
loaded, the Command Pending bit returns to 
0. In Direct Control mode, the AUX3-CP out- 
put goes inactive, indicating that the DCP can 
accept the next command. 

Load Encrypted E Key Through Auxiliary 
Port (B1H). 

Load Encrypted D Key Through Auxiliary 
Port (B2H). 

These commands are used in Multiplexed 
Control mode only. Their execution is similar 
to that of the Load Clear E (D) Key Through 
Auxiliary Port command, except that key bytes 
are first decrypted using the electronic code 
book algorithm and the Master (M) Key 
register. The key bytes are then loaded into 
the appropriate key register, after having 
passed through the parity-check logic. 

The Command Pending bit (Sg) is 1 during 
the entire decrypt-and-load operation. In addi- 
tion, the Busy bit (S5) is 1 during the actual 
decryption process. 

Load Encrypted E Key Through Master Port 
(31H). 

Load Encrypted D Key Through Master Port 
(32H). 

These commands are used in Multiplexed 
Control mode only. Their execution is similar 
in effect to that of the Load Clear E (D) Key 
Through Master Port command. The commands 
differ in that key bytes are initially decrypted 
using the electronic code book algorithm and 
the Master (M) Key register. Once decrypted, 
they are loaded byte-by-byte into the target 
key register, after having passed through the 
parity-check logic. 

The command pending bit (Sg) is 1 during 
the entire decrypt-and-load operation. In addi- 
tion, the busy bit (S5) is 1 during the actual 
decryption process. 

Load Clear IVE Register Through 
Master Port (85H) 
Load Clear IVD Register Through 
Master Port (84H) 

These commands are used in Multiplexed 
Control mode only. Their execution is virtually 
identical to that of the Load Clear E (or D) Key 
Through Master Port command. The commands 
differ in that the data written to the input 
register address is routed to either the Encryp- 
tion Initializing Vector (IVE) or Decryption 
Initializing Vector (IVD) register instead of a 
key register. No parity checking occurs. The 



Command Pending bit (Sg) is 1 during the 
entire loading process. 

Load Encrypted IVE Register Through 
Master Port (ASH). 

Load Encrypted IVD Register Through 
Master Port (A4H). 

These commands are analogous to the Load 
Encrypted E (or D) Key Through Master Port 
command. The data flow specifications set in 
the Mode register are overridden and the eight 
vector bytes are decrypted using the Decryp- 
tion (D) Key register and the electronic code 
book algorithm. The resulting clear vector 
bytes are loaded into the target Initializing 
Vector register. No parity checking occurs. 
The Busy bit (S5) does not become 1 during 
the decryption process, but the Command 
Pending bit (Sg) is 1 during the entire 
decryption-and-load operation. 

Read Clear IVE Register Through 
Master Port (8DH). 
Read Clear IVD Register Through 
Master Port (8CH). 

In the Multiplexed Control mode, these com- 
mands override the data flow specifications 
set in the Mode register and connect the 
appropriate Initializing Vector register to the 
master port at the Output register address. In 
this state, each IV register appears as eight 
bytes of FIFO storage. The first byte of data is 
available six clocks after loading the Com- 
mand register. The Command Pending bit in 
the Status register remains a 1 until sometime 
after the eighth byte is read out. The host 
system is responsible for reading exactly eight 
bytes. 

Read Encrypted IVE Register Through 
Master Port (A9H). 

Read Encrypted IVD Register Through 
Master Port (A8H). 

In the Multiplexed Control mode only, these 
commands override the specifications set in 
the Mode register and encrypt the contents of 
the specified Initializing Vector register using 
the electronic code book algorithm and the 
Encrypt (E) key. The resulting cipher text is 
placed in the output register, where it can be 
read as eight bytes through the master port. 
During the actual encryption process, the Busy 
bit (S5) is 1. When the Busy bit becomes 0, the 
encrypted vector bytes are ready to be read 
out. The Command Pending bit (Sg) is 1 
during the entire encryption and output pro- 
cess; it becomes when the eighth byte is read 
out. The host system is responsible for reading 
exactly eight bytes. 

Encrypt with Master (M) Key (39H). 

In the Multiplexed Control mode, this com- 
mand overrides the data flow specifications set 
in the Mode register and causes the DCP to 
accept eight bytes from the master port, which 
are written to the Input register. When eight 
bytes have been received, the DCP encrypts 



379 



indicators in the three phases of this operation. 

The Command Pending bit becomes 1 as 
soon as the Input register can accept data. 
When exactly eight bytes have been entered, 
the Busy bit becomes and remains 1 until the 
encryption process is complete. When Busy 
becomes 0, the encrypted data is available to 
be read out. '.he Command Pending bit 
returns to when the eighth byte has been 
read. 

Start Encryption (41H) 
Start Decryption (40H) 
Start (COH). 

The three start commands begin normal data 
ciphering by setting the Status register's 
Start/Stop bit (S7) to 1 . The Start Encryption 
and Start Decryption commands explicitly 
specify the ciphering direction by forcing the 
Encrypt or Decrypt bit (M4) in the Mode 
register to 1 or 0, respectively. The Start com- 
mand, however, uses the current state of the 
Encrypt/Decrypt bit, as specified in a previous 
Mode register load. 

When a start com mand h as been e ntered, 
the port status flag (MFLG or SFLG) asso- 
ciated with the Input register becomes active 
(Low), indicating that data may be written to 



AUX6-E/D is High when AUX5-S/S goes High, 
the command is Start Encryption; if AUXg-E/D 
is Low, it is Start Decryption. 

Stop (EOH). 

The Stop command clears the Start/Stop bit 
(S7) in the Stat us regi ste r. This action causes 
the input flag (MFLG or SFLG) to become 
inactive and inhibits the loading of any further 
input into the algorithm unit. If ciph ering is in 
progress [Busy bit (S5) is 1 or AUX2-BSY is 
active], it is allowed to finish, and any data in 
the Output register remains accessible. 

In Direct Control mode, the Stop command 
is implied_when the signal level on the 
AUX5-S/S input goes from High to Low 
(Table 4). 

Software Reset (00). 

This com mand has the sa me effect as a hard- 
ware reset (MAS and MDS Low): it forces the 
DCP back to its default configuration, and all 
processing flags go into Inactive mode. The 
default configuration includes setting the Mode 
register to Electronic Code Book ciphering 
mode and establishes a dual-port configuration 
with master port clear and slave port 
encrypted. 



Timing 
Requirements 



The control and/or data signals and the 
timing requirements for clock/reset, Direct 
Control mode, Multiplexed Control mode 
(master port), master (slave) port read/write, 
and auxiliary port key entry functions are 
illustrated in Figures 8 through 12. The ac 
switching characteristics of the signals 
involved in the above functions are described 
in the AC Characteristics. The specific timing 
periods described are identified by numerics 
(1 through 48), which are referenced in both 
the timing diagrams and in the AC 
Characteristics. 

A two-to-seven character symbol is listed in 
AC Characteristics for each period described. 
The symbol specifies the signal(s) involved, the 
state of each signal, and optionally, the port 
associated with a signal. Symbols are encoded 
as follows: 

General Form: Ta Ab (Cb) 
Where: 

(1) T is a constant. 

(2) a represents any one of the following sym- 
bols: 

Symbol Meaning 
c Clock 
d Delay 
f Fall Time 



h Hold Time 

r Rise Time 

s Setup Time 

w Width 

(3) A,C represent any of the following signal 
names: 

Symbol Signal Name 
A Add ress Strobe 
B BSY, Busy 
C Clock 

D* Data In or the address 

at the master port. 
E E/D, Enable / Disable 
F* Fl ag (MF LG, SFLG, or 

(AFLG) 
G* Data Strob e (MD S, 

SDS, or ASTB) 
K K/D, Key/Data 
M C/K, Control/Key 

Mode 
N S/S^ Start/Stop 
P PAR, Parity 
Q* Data Out (master or 

slave port) 

R ■ CP, Clock Pulse 

S* Chip Select (master or 

slave port) 
W MR/W, Master Port 

read/write 



380 



Timing 
Requirements 

(Continued) 



(4) b represents any one of the 
following signal state descrip- 
tors (symbol). 

Symbol State Indicated 

h High 

, 1 Low 

v Valid 

x Invalid 

z High Impedance 

'These signal names may be 
modified by the following op- 
tional numeric port identifiers: 

Identifier Port 

1 Master Port 

2 Slave Port 

3 AUX (Key) Port 



For example: Dl specifies data 
in at Master Port; F2 specifies 
Slave Port flag-SFLG. 



MDS 



"©- 



— © 

L 



-©- 



L 



Figure 8. Clock and Beset 



MAXIMUM RATINGS (Above which useful life may be impaired) 



Storage Temperature 


-65 to +150°C 


Ambient Temperature Under Bias 


to +70°C 


Voltage on Any Pin with Respect to Ground 


-0.5 to +7.0V 


Power Dissipation 


1.5W 



The products described by this specification include internal circuitry designed to protect input devices from damaging accumulations of 
static charge. It is suggested nevertheless, that conventional precautions be observed during storage, handling and use in order to avoid 
exposure to excessive voltages. 



Z8068, Z9518 ELECTRICAL CHARACTERISTICS (over operating range unless otherwise specified) 

T A = to 70°C, V CC = +5.0V ±5%, V ss = 0V 



Parameters 


Description 


Test Conditions 


Min 


Typ 


Max 


Units 


V|L 


Input Low Voltage 




-0.5 




.8 


Volts 


V,H 


Input High Voltage 




2.2 




Vcc 


Volts 


Vol 


Output Low Voltage 


l OL = 3.2mA 






.40 


Volts 


Voh 


Output High Voltage 


Iqh = -400nA 


2.4 






Volts 


h 


Input Leakage Current 


V SS * V IN = V CC 






±10 


HA 


Ipz 


Output Leakage Current 


V ss + .40 « V, N « V CC 






±10 


MA 


'cc 


Supply Current (AVER.) 






150 


250 


mA 



X 2 ° - TEST - 2 ° V" 

oe POINTS^ 0B j\ 



INPUT WAVEFORMS FOR A.C. TESTS 



381 



Z8068/Z9518 SWITCHING CHARACTERISTICS (Note 1) 

The table below specifies the guaranteed performance of this LOW and 2.0V for a HIGH. Outputs are fully loaded, with C|_ =- 
device over the commercial operating range of to + 70 C with 50pF. See switching waveform figures following table for graphic 
Vcc ,rom 4 75 10 5 25V - A " da,a are in nanoseconds. Switching illustration of timing parameters, 
tests are made with inputs and outputs measured at 0.8V for a 



SWITCHING CHARACTERISTICS over operating range 









Z8068 


Z9518 




Parameter 


Number 


Description 


Min 


Typ 


Max 


Min 


Typ 


Max 


Units 


Clock 


TWH 


1 


Clock Width (HIGfj) 


115 






150 






ns 


TWL 


2 


Clock Width (LOW) 


115 






150 






ns 


TC 


3 


Clock HIGH to Next Clock HIGH (Clock Cycle) 


250 




1000 


320 




1000 


ns 


Reset 


TG1LG1H 


5 


MDS • MAS LOW to MDS • MAS HIGH 
(Reset Pulse Width) 


TC 






TC 






ns 


TCHG1H 


6 


Clock HIGH to MDS • MAS HIGH 







50 







50 


ns 


Direct Control Mode 


TNLMH 


9 


S/S LOW to C/K HIGH (Setup) 


3TC 






3TC 






ns 


TKLMH 


10 


K/D LOW to C/K HIGH (Setup) 


3TC 






3TC 






ns 


TMHNH 


11 


C/K HIGH to S/S HIGH 


6TC 






6TC 






ns 


TMHKH 


12 


C/K HIGH TO K/D HIGH 


6TC 






6TC 






ns 


TEVKH 


14 


E/D VALID to K/D HIGH (Setup) 


3TC 






3TC 






ns 


TKHRL 


15 


K/D HIGH to CP LOW 






300 






300 


ns 


TKLEX 


17 


K/D LOW to E/D INVALID (Hold) 


TC 






TC 






ns 


TCLNV 


19 


Clock LOW to S/S VALID 


20 




80 


20 




80 


ns 


TEVNH 


20 


E/D VALID to S/S HIGH (Setup) 


3TC 






3TC 






ns 


TNHF1L 


21 


S/S HIGH to MFLG (SFLG) LOW (Port Input Flag) 






230 






300 


ns 


TCHF1L 


22 


Clock HIGH to MFLG (SFLG) LOW (Port Input Flag) 
(Note 2) 






230 






300 


ns 


TCHBL 


24 


Clock HIGH to BSY LOW 






300 






400 


ns 


TCLBH 


25 


Clock LOW to BSY HIGH 






230 






300 


ns 


TCHF1L 


27 


Clock HIGH to MFLG (SFLG) LOW 
(Port Output Flag) 






230 






300 


ns 


TNLF1H 


28 


S/S LOW to MFLG (SFLG) HIGH (Port Input Flag) 
(Note 3) 






230 






300 


ns 


Multiplexed Control Mode - Master Port 


TWA 


32 


MAS Width (LOW) 


80 






115 I 




ns 


TS1LAH 




34 


MCS LOW to MAS HIGH (Setup) 


















TAHS1H 


35 


MAS HIGH to MCS HIGH (Hold) 


60 






60 






ns 


TD1VAH 


36 


Address-In VALID to MAS HIGH 
(Address Setup Time) 


55 






90 






ns 


TAHD1X 


37 


MAS HIGH to Address-In INVALID 
(Address Hold Time) 


60 






60 






ns 



382 



AC SWITCHING CHARACTERISTICS 











Z8068 


Z9518 




Parameter Number 


Description 


Min 


Typ 


Max 


Min 


Typ 


Max 


Units 


Master (Slave) Port Read/Write 


TS1LG1L 


40 


MCS (SCS) LOW to MDS (SDS) LOW (Select Setup) (Note 4) 


100 






100 






ns 


TG1HS1H 


41 


MDS (SDS) HIGH to MCS (SCS) HIGH (Select Hold Time) 
(Note 4) 


25 






25 






ns 


TWVG1L 


42 


MR/W VALID to MDS LOW (Setup) 


100 






100 






ns 


TG1HWX 


43 


MDS HIGH to MR/W INVALID (Hold) 


25 






25 






ns 






MDS (SDS) LOW to 
MDS (SDS) HIGH 


Width - Write, Data Read 


125 




1000 


160 




1000 




TG1LG1H 


44 


Width - Status Register 
Read 


200 




1000 


300 




1000 


ns 


TCLG1H 


45 


Clock LOW to MDS (SDS) HIGH (Note 11) 







TWL - 
65 







TWL - 
100 




TGIHG1L 


46 


MDS (SDS) HIGH to MDS (SDS) LOW (Data Strobe 
Recovery Time) 


125 






160 






ns 






Write-Data VALID 
MDS (SDS) HIGH 


Setup Time - Key Load 
(Note 8) 


125 






160 








TD1VG1H 


47 


Setup Time - Data Write 


125 




160 






ns 






Setup Time - Command/ 
Mode Register Write 


125 






160 








TG1HD1X 


48 


MDS (SDS) HIGH to Write-Data INVALID 
(Hold Time - All Writes) 


25 






25 






ns 


TG1LQ1 V 


49 


MDS (SDS) LOW to 
Read-Data VALID 


Read Access Time - 
Status Register 






200 






300 


ns 






Read Access Time - Data 






120 






150 




TG1HQ1V 


50 


MDS (SDS) HIGH to Read-Data INVALID (Read Hold Time) 


5 






5 






ns 


TG1LF1H 


51 


MDS (SDS) LOW to MFLG (SFLG) HIGH (Last Strobe) 
(Note 5) 






125 






160 


ns 


TG1LRH 


52 


MDS HIGH to CP HIGH 


Last Strobe, Key Load 






TC + 500 






TC+500 


ns 


TG1HNL 


53 


MDS (SDS) HIGH to S/S LOW (Hold Time) (Note 9) 


4TC 






4TC 






ns 


TG1HPV 


54 


MDS HIGH to PAR VALID (Key Write) 






200 






250 


ns 


Auxiliary Port Key Entry 


TG3LG3H 


61 


ASTB LOW to ASTB HIGH (Width) 


160 






160 






ns 


TCLG3H 


62 


Clock LOW to ASTB HIGH 







50 







50 


ns 


TG3HG3L 


63 


ASTB HIGH to Next ASTB LOW (Recovery Time) 


250 






320 






ns 


TD3VG3H 


64 


Write-Data VALID to ASTB HIGH (Data Setup Time) 


200 






300 






ns 


TG3HD3X 


65 


ASTB HIGH to Write-Data INVALID (Data Hold Time) 


80 






80 






ns 


TG3HPV 


66 


ASTB HIGH to PAR VALID 






200 






300 


ns 


TG3LF3H 


67 


ASTB LOW to AFLG HIGH (Last Strobe) 






230 






300 


ns 



Notes: 1 . All input transition times assumed ^20ns. 

2. Parameter TCHF1L applies to all input blocks except the first (when S/S first goes HIGH). 

3. When S/S goes inactive (LOW) in direct control mode, the flag associated with the input port will turn off. 

4. Direct control mode only. 

5. In Cipher Feedback, the port flag (MFLG or SFLG) will go inactive following the leading edge of the first data strobe (MDS or SDS): in all other 
modes and operations, the flags go inactive on the eighth data strobe. 

6. Do not remove K/D until CP is i nactive (HIGH). 

7. Do not change BID until MFLG (SFLG) is inactive (HIGH). 

8. 300ns Min if parity check i s nee ded. 

9. In Cip her Feedback mode BSY mus t be in active before S/S goes LOW. 

10. AFLG must go active (LOW) before ASTB goes active (LOW). 

11. This limit is valid when the clock frequency is 4MHz. At slower clock rates, the range is wider. 



383 




X 



) — { 



> 



I— - 36 — |— 37 — 



1 / 



Figure 10. Master Port. Multiplexed Control Mode Read/Write Timing 



384 



MFLG 
SFLG 



WRITE 
DATA 



40 

i 

42 — 

SE&M>C 



X 



:xmxs 



REAO 
DATA ' 



PAR 



CH3 



X 



x 



X 
/ 1 



Figure 11. Master (Slave) Port Read/Write 




X 



z 



Figure 12. Auxiliary Port Key Entry 



385 



Z8516 Z9516 DMA Transfer 
Controller (DTC) 



October 1988 



FEATURES 



Two independent multi-function channels 

Transfer Modes: single, demand dedicated with bus 
hold, demand dedicated with bus release, demand 
interleave 

Memory/peripheral transfers up to 2.66 Megabyte/ 
second at 4MHz and 4 Megabyte/second at 6MHz 

Memory/memory flowthrough transfer up to 1.33 
Megabyte/second at 4MHz and 2 Megabyte/second at 6 
MHz 

1 6 Megabyte physical addressing range in each address 
space 

Data types: byte-to-byte, word-to-word, byte/word 
tunneling 

Automatic loading/reloading of control parameters by 
each channel 



Optional automatic chaining of operations 

Masked data pattern matching for search operations 

Vectored interrupts on selected transfer conditions 

Software or hardware wait state insertion 

Address increment, decrement, or hold 

Channel interleave operations 

Interleave operations with system bus 

Base registers for efficient repetitive operations 

Reload word table for efficient channel initialization 

Software DMA request 



GENERAL DESCRIPTION 



The Z851 6/Z951 6 Universal DMA Transfer Controller (DTC) is 
a high performance peripheral interface circuit for 
non-Z-BUS CPUs (Figure 1). In addition to providing data 
block transfer capability between memory and periph- 
erals, each of the DTC's two channels can perform 
peripheral-to-peripheral and memory-to-memory transfers 
(Figure 2). A special Search Mode of Operation compares 
data read from a memory or peripheral source with the 
contents of a pattern register. 

For all DMA operations (search, transfer, and transfer- 
and-search), the DTC can operate with either byte or word 
data sizes. In some system configurations it may be 
necessary to transfer between word-organized memory and 
a byte-oriented peripheral. The DTC provides a byte 
packing/unpacking capability through its byte-word 
funnelling transfer or transfer-and-search option. Some DMA 
applications may continuously transfer data between the 



same two memory areas; these applications may not require 
the flexibility inherent in reloading registers from memory 
tables. To service these repetitive DMA operations, base 
registers, which reinitialize the current source and 
destination Address and Operation Count registers, are 
provided on each channel. To change the data transfer 
direction under CPU control, provision is made for 
reassigning the source address as a destination and the 
destination as a source, eliminating the need for actual 
reloading of these address registers. 

DMA devices frequently must interface to slow peripherals 
or slow memory. In addition to providing a hardware WAIT 
input, the Z8516/Z9516 DTC allows the user to program the 
automatic insertion of either 0, 1 , 2, or 4 wait states for either 
source or destination addresses. The user may even disable 
the wait pin function and exclusively use these software- 
programmed wait states. 



High throughput and powerful transfer options are less 
useful if a DMA requires frequent reloading by the host CPU. 
The Z8516/Z9516 minimizes CPU interactions by allowing 
each channel to load its control parameters from memory 
into the channel's control registers. The only CPU action 
required is to load the control parameter table's address into 



the channel's Chain Address register and then issue a Start 
Chain Command to start the register loading operation. This 
reloading operation is called command chaining and the 
table is called the Chain Control Table. 

The Z8516/Z951 6 DTC is packaged in a 48-pin DIP and uses 
a single + 5V power supply. 



CHANNEL 1 
REGISTERS 



EXTERNAL BUS 



BUS 
INTERFACE 



INTERNAL BUS 



^) COMMAND 



CHANNEL 2 
REGISTERS 



MASTER 
MODE 



CHAIN 
CONTROL 



CONTROL 
LOGIC 



A K INTERFACE 

X TO 

PERIPHERALS 



Figure 1 . DTC Block Diagram 



CPU 




SYSTEM 




MEMORY 



O O £t 



PARALLEL 

I/O 



FIO 


DREO 


DTC 


DREO 


sec 


DACK 


DACK 









Figure 2. DTC Configuration 



SIGNAL DESCRIPTIONS (Figures 3 and 4) 

AD -AD 15 . Address/Data Bus (bidirectional, active High, 
3-state). The time-multiplexed bus is used for all I/O and 
memory transactions. AD is the least significant bit 
position; AD-|5 is the most significant. The presence of 
addresses is defined by the timing edge of ALE; the 



asserted or requested presence of data is defined by the DS 
signal. When the DTC is in control of the system bus, it 
dominates the AD Bus; when the DTC is not in control of the 
system bus, the CPU or other external devices dominate the 
AD Bus. 



387 



BUS 
CONTROL 



Z8516/ 
Z9516 
DTC 



□ HEOi . DREO2 
DACK, . DACK; 

EOP 



1—TT 



A D 








AD, 




AD- 




AD, 




AD j 




ADt, 




AD- 




AD t 




AD, 




AD,, 

AO,; 






A0. : 
AD-- 






M>U 




AD,, 





INTERRUPT 
CONTROL 



INT £ 
BAI ^ 
auSREO £ 
»ccC 
ADo C 

AD: C 
AD, C 
AD.C 
AD, C 
AD, C 
AD 7 C 
AD, C 
AD, Q 
AO«C 

ad„ rj 
ad„[; 
»o,»C 

AD„ C 
AD, 5 £ 
AuC 
A^C 
Ai, C 
AmC 



28516/ 
Z9518 
DTC 



] INTACK 
] RLoET 
J CLK 
] ALE 
] P(D 

□ os 
J cs 

□ R/W 

□ OACK, 
J DACK 3 

□ EOP 
J DREQ; 
J OREO, 

□ B/VV 

J WAIT 
3 TBlft 

J rben 

] M/IO 

J n;s 
3 a, 6 

□ A„ 

3 *« 

J A 19 



ZZZ< «<< <<< 4«4XZ 

.nnnnnnnnnnnnnnnnn v 

/:; o X 



N/C 
AD14 
AD19 
All 



uuuuuuuuuuuuuuuuu 

3Sl>'>g|B|S|'Si|i|>i£3 



Figure 3. Pin Functions 



Figure 4. Pin Assignments 



A1S-A23. Upper Address Bus (output, 3-state). are 
activated only when the DTC is controlling the system bus. 
Combined with the lower 1 6 address bits appearing on AD 
through AD 15 , this 24-bit linear address allows the DTC to 
access anywhere within 16 Megabytes of memory. 

ALE. Address Latch Enable (output, active High). This 
signal is provided by the DTC to latch the address signals 
AD -ADi 5 into the address latch. This pin is never floated. 

BAI. Bus Acknowledge In (input, active High). BAI is an 
asynchronous signal indicating that the CPU has 
relinquished the bus and that no higher priority device has 
assummed bus control. Since BAI, before being used, is 
internally synchronized by the DTC, transitions on BAI do 
not have to be synchronous with the DTC clock. The BAI 
input is usually connected to the HLDA line from the CPU or 
to the output of a priority decoder. 

BUSREQ. Bus Request (output, active High). This signal is 
used by the DTC to obtain control of the bus from the CPU. 
BUSREQ lines from multiple devices are connected to a 
priority encoder. 

B/W. Byte/Word (output, 3-state). This output indicates the 
size of data transferred on the AD -AD 15 bus. High indicates 
a byte (8-bit) transfer; Low indicates a word (16-bit) transfer. 
This output is activated when ALE is High and remains valid 
for the duration of the whole transaction. All word-sized data 
is word aligned and must be addressed by even addresses 
(Aq = 0). When addressing byte read transactions, the least 
significant address bit determines which byte is needed; an 



even address specifies the most significant byte (ADs-AD 15 ) 
and an odd address specifies the least significant byte 
(AD0-AD7). This addressing mechanism applies to memory 
accesses as well as I/O accesses. When the DTC is a slave, it 
ignores the B/W signal and this pin floats to 3-state OFF. 

CLK. DTC Clock (input). The clock signal controls the 
internal operations and the rates of data transfers. It is 
usually derived from a master system clock or the 
associated CPU clock. The Clock input requires a high 
voltage input signal. Many DTC input signals can make 
transitions independent of the DTC clock; these signals can 
be async hronous to the DTC clock. On other signals, such 
as WAIT inputs, transitions must meet setup and hold 
requirements relative to the DTC clock. 

CS. Chip Select (input, active Low). A CPU or other external 
device uses CS to activate the DTC for reading and writing of 
its internal registers. There are no timing requirements 
between the CS input and the DTC clock; the_CS input 
timing requirements are only defined relative to DS signal 
timings. This pin is ignored when the DTC is in control of the 
system bus. 



DACK-,, DACK 2 . D MA Ac knowledge (output, active Low, 
one per channel). DACK in dicates that the channel is 
performing a DMA operation. DACK is pulsed, held active, 
or held inactive during DMA operations as programmed in 
the Channel Mode register. For Flowthrough operations, the 
peripheral is fully addressed using the conventional I/O 
addressing protocols and therefore may choose to ignore 



388 



DACK. DACK is always output as programmed in the 
Channel Mode register for a DM A operation, even when the 
operation is initiated by a C PU so ftware request command 
or as a result of chaining. DACK is not output during the 
chaining operations. 

DREQ<|, DREQ 2 . DMA Request (input, active Low, one per 
channel). DREQ may make transitions independent of the 
DTC clock; these lines are used by external logic to initiate 
and control DMA operations performed by the DTC. 

DS. Data Strobe (bidirectional, active Low). A Low on this 
signal indicates that the AD0-AD15 bus is being used for 
data transfer. When the DTC is not in control of the system 
bus and the external system is transferring information to or 
from the DTC, DS is a timing input used by the DTC to move 
data to or from the AD -AD 15 bus. Data is written into the 
DTC by the external system on the Low-to-High DS 
transition. Data is read from the DTC by the external system 
while DS is Low. There are no timing requirements between 
DS as an input and the DTC clock; this allows use of the DTC 
with a system bus which does not have a bussed clock 
(Figure 26). During a DMA operation when the DTC is in 
control of the system, DS is an output generated by the DTC 
and used by the system to move data to or from the 
AD0-AD15 bus. When the DTC has bus control, it writes to 
the external system by placing data on the AD -AD-| 5 bus 
before the High-to-Low DS transition and holding the data 
stable until after the Low-to-High DS transition; while reading 
from the external system the Low-to-High transition of DS 
inputs data from the AD -AD-|5 bus into the DTC (Figure 27). 

EOP . End of Process (bidirectional, active Low, open drain). 
EOP must be pulled up with an external resistor of 1 .8 ohm 
or more. When a TC or M C ter mination occurs, the DTC 
emits an output pulse on EOP. An external so urce may 
term inate a DMA operation in progress by driving EOP Low. 
EOP al ways applies to the active channel; if no channel is 
active, EOP is ignored. 

INT. Interrupt Request (output, open drain, active Low). INT 
is used to interrupt the CPU. It is driven Low whenever the IP 
and CIE bits of the Status Register are set. It is cleared by the 
DTC after receiving a clear IP command. 

INTACK . Interrupt Acknowledge (input, active Low). 
INTACK indicates that the request for interrupt has been 
granted. The DTC places a vector onto the AD bus if the No 
Vector on Interrupt bit (MM3) is reset. 

NI/IO. Memory/Input-Output (output, 3-state). This signal 
specifies the type of transaction. A High on this pin indicates 
a memory transaction; a Low indicates an I/O transaction. It 
floats to a tri-state level when DTC is not in control of the 
system bus. 

N/S. Normal/System (output, 3-state). This signal is 
activatedonly when DTC is the master. Normal isjndicated 
when N/S is High. This signal supplements the M/IO line and 
is used to indicate whether memory or I/O space is being 
accessed. 



P/D. Pointer/Data (input). This signal indicates information 
on the ADo-ADi 5 bus only when the DTC is the bus slave. A 
High on this signal indicates that the information on the AD 
bus is an address of the internal register to be accessed. The 
data on the AD bus is loaded into the Pointer register of the 
DTC. A Low on this signal indicates that a data transfer is 
taking place between the bus and the internal register 
designated by the Pointer register. Note that if a transaction 
is carried out with R/W High and P/D High, the contents of 
the Pointer register will be read. 

RBEN. Receive Buffer Enable (output, open drain, active 
Low). When DTC is in control of the system bus, a Low on this 
output indicates that the data is being transferred from the 
data bus lines to the DTC through the buffer. The purpose of 
this signal is to eliminate bus contention. This pin floats to a 
tri-state level when the DTC is not in control of the system 
bus. 

RESET. Reset (input, active Low). RESET disables the DTC 
and clears its Master Mode register. 

R/W. Read/Write (bidirectional, 3-state). Read polarity is 
High and write polarity is Low. R/W indicates the data 
direction of the current bus transaction, and is stable from 
when ALE is High until the bus transaction ends. When the 
DTC is not in control of the system bus and the external 
system is transferring information to or from the DTC, R/W is 
a status input used by the DTC to determinejf data is 
entering or leaving on the AD -AD 15 bus during DS time. In 
such a case, Read (High) indicates that the system is 
requesting data from the DTC and Write (Low) indicates that 
the system is presenting data to the DTC. There are no 
timing requirements between R/W as an input and the DTC 
clock; transitions on R/W as an input are only defined 
relative to DS. When the DTC is in control of the system bus, 
R/W is an output generated by the DTC, with Read 
indicating that data is being requested from the addressed 
location or device, and Write indicating that data is being 
presented to the addressed location or device. Flyby DMA 
operations are a special case where R/W is valid for the 
normally addressed memory or peripheral locations and 
must be interpreted in reverse by the Flyby peripheral that 
uses it. 

TBEN. Transmit Buffer Enable (output, open drain, active 
Low). When DTC is a bus master, a Low on this output 
indicates that the data is being transferred through the buffer 
from the DTC to the data bus lines. The purpose of this signal 
is to eliminate bus contention. When DTC is not in control of 
the system bus, these pins float to 3-state OFF. 

WAIT. Wait (input, active Low ). Slow memorie s and 
pe riphera l devices may use WAIT to extend DS and RBEN 
or TBE N dur ing operation. Unlike the CS input, transitions 
on the WAIT input must meet certain timing requirements 
relative to the DTC clock. The Wait function may be disabled 
using a control bit in the Master Mode register (MM2). 



389 



uv-^coo iBaiiiouuns. i-iegisiers wmch can be 

read by the CPU are either fast (F) or slow (S) readable. Fast 
registers can be read by a normal CPU I /O operation without 
additional wait states. Reading slow registers requires 



during chaining (C). All reads or writes must be word 
accesses since, in slave mode, the DTC ignores the B/W 
line. It is the responsibility of the user to supply the necessary 
external logic if slow readable registers are to be read. 



Table 1 . DTC Internal Registers 



Name 


Bit 

Size 


Number 


Access 
Type 


Port Address 
CH-1/CH-2 


Master Mode Register 


4 


1 


FW 


38 


Pointer Register 


6 


1 


rW 




Cham-Control Register 


10 


1 


c 




Temporary Register 


16 


1 


D 




Command Register 


8 


1 


W 


2E/2C 


Current Address Register — A: 










Upper-Address/Tag field 


14 


2 


CFW 


1A/18 


Lower-Address field 


16 


2 


CFW 


OA/08 


Current Address Register— B: 










Upper-Address/Tag field 


14 


2 


CFW 


12/10 


Lower-Address field 


16 


2 


CFW 


02/00 


Base Address Register— A: 










Upper-Address/Tag field 


14 


2 


CFW 


1E/1C 


Lower-Address field 


16 


2 


CFW 


OE/OC 


Base Address Register— B: 










Upper-Address/Tag field 


14 


2 


CFW 


16/14 


Lower-Address field 


16 


2 


CFW 


06/04 


Current Operation Count 


16 


2 


CFW 


32/30 


Base Operation Count 


16 


2 


CFW 


36/34 


Pattern Register 


16 


2 


CSW 


4A/48 


Mask Register 


16 


2 


CSW 


4E/4C 


Status Register 


16 


2 


F 


2E/2C 


Interrupt Save Register 


16 


2 


F 


2A/28 


Interrupt Vector Register 


8 


2 


CSW 


5A/58 


Channel Mode Register— High 


5 


2 


CS 


56/54 


Channel Mode Register— Low 


16 


2 


CSW 


52/50 


Chain Address Register: 










Upper-Address/Tag tield 


10 


2 


CFW 


26/24 


Lower-Address field 


16 


2 


CFW 


22/20 


Access Codes: C = Chain Loadable 

D = Accessible by DTC channel 
F = Fast Readable 


S = Slow Readable 
W = Writeable by CPU 





NOTE: The address of the register to be accessed is stored in the Pointer register. 

'The port addresses of the Command register can be used alternately for both channels except when issuing a Set/Clear IP command. 



390 



The internal registers are read or written in two steps. When 
the P/D input is High, the address of the register to be 
accessed is written to the Pointer register. When P/D input is 
Low, the data is read from or written into the desired register 
which is indicated by the Pointer register. Note that a read 
with P/D High causes the contents of the Pointer register to 
be read on AD-| through AD 6 . 

The DTC registers can be categorized into chip-level 
registers and channel-level registers. 

Chip-Level Registers 

Chip-level registers are duplicated for each channel and 
control the overall operation and configuration of the DTC. 

The five chip-level registers are: 

■ Master Mode 

selects the way the DTC chip interfaces to the system 

■ Pointer 

written to by the host CPU when the P/D input is High. 
The data in the Pointer register is the address of the 
internal register to be accessed 

■ Chain Control 

used by a channel while it is reloading its channel-level 
registers from memory 

■ Temporary 

used to hold data for Flowthrough Transfer/Transfer-and- 
Searches 

■ Command 

written to by the host CPU to initiate certain operations 
within the DTC chip, such as resetting the unit 

Master Mode Register. The 4-bit Master Mode register 
(Figure 5) controls the chip-level interfaces. It can be read 
from and written to by the host CPU through pins AD -AD 3 
without wait states, but it is not loadable by chaining. On a 
reset, the Master Mode register is cleared to all zeroes. 



MM3 MM2 MM1 MMO 



CHIP ENABLE 

CPU INTERLEAVE ENABLE 

WAIT LINE ENABLE 

NO VECTOR ON INTERRUPT 



Figure 5. Master Mode Register 

The Chip Enable bit, when set to 1, enables the DTC to 
request the bus. When enabled, the DTC can perform DMA 
Operations and reload registers. It can always issue 
interrupts and respond to interrupt acknowledges. When 
the Chip Enable bit is cleared to 0, the DTC is inhibited from 
requesting control of the system bus and, therefore, 
inhibited from performing chaining or DMA operations. 



The CPU Interleave bit enables interleaving between the 
CPU and the DTC. 

The Wait Line Enable bit enables sampling of the WAIT line 
during Memory and I/O transactions. Because the DTC 
provides the ability to insert software progra mmab le wait 
states, users may disable sampling of the WAIT pin to 
eliminate the logic driving this pin. The Wait Line Enable bit 
provides this flexibility. The Wait States section of this 
document includes details on wait state insertion. 

The No Vector on Interrupt bit selects whether the DTC 
channel or a peripheral returns a vector during interrupt 
acknowledge cycles. When this bit is cleared, a channel 
receiving an interrupt acknowledge drives the contents of its 
Interrup t Save register onto the AD -AD 15 data bus while 
INTACK is Low. If this bit is set, interrupts are serviced in an 
identical manner, but the AD0-AD15 data bus remains in a 
high impedance state throughout the acknowledge cycle. 

Pointer Register. The Pointer register contains the address 
of the internal register to be accessed. It can be read or 
written by the CPU when the P/D line is H igh . 

Chain Control Register. When a channel starts a chaining 
operation, it fetches a Reload word from the memory 
location pointed to by the Chain Address register (Figure 
11). This word is then stored in the Chain Control register. 
The CPU cannot read to or write from the Chain Control 
register. Once a channel starts a chain operation, the 
channel will not relinquish bus control until all registers 
specified in the Reload word are reload ed u nless an EOP 
signal is issued to the chip. Issuing an EOP to a channel 
during chaining prevents the chain operation from resuming 
and allows the contents of the Reload Word register to be 
discarded. 

Temporary Register. The Temporary register is used to 
store data during Flowthrough transfers and to hold data 
being compared during a Search or a Transfer-and-Search. 
The CPU cannot read to or write from the Temporary 
register. In byte-word funnelling, data may be loaded into or 
out of the Temporary register on a byte-by-byte basis, with 
bytes moving between the low byte of the data bus and the 
high byte of the Temporary register. The Transfer section 
carries further details. 

Command Register. The DTC Command register (Figure 
25) is an 8-bit write-only register written to by the host CPU. 
The Command register is loaded from the data on AD 7 -AD ; 
the data on AD 15 -AD 8 is disregarded. A complete 
discussion of the commands is given in the Command 
Descriptions section. 

Channel-Level Registers 

Each of the DTC's two channels has a complete set of 
channel-level registers (Figure 6), which can be divided into 
two subcategories: General Purpose and Special Purpose. 



391 



DTC INTERNAL 
BUS 



CURRENT 
ADDRESS REGISTER A 



ADDRESS REGISTER A 



CURRENT 
ADDRESS REGISTER B 



CURRENT OPERATION 
COUNT REGISTER 



BASE OPERATION 
COUNT REGISTER 



CHANNEL MODE 



CHAIN ADDRESS 
REGISTER 



INTERRUPT 
SAVE REGISTER 



INTERRUPT 
VECTOR REGISTER 



SPECIAL-PURPOSE CHANNEL REGISTERS 

Figure 6. Channel-Level Registers 



General Purpose Registers 

The general purpose registers are: 

■ Current Address Register A (ARA) 

■ Current Address Register B (ARB) 

■ Base Address Register A (ARA) 

■ Base Address Register B (ARB) 

■ Current Operation Count 

■ Base Operation Count 

■ Channel Mode 

Current and Base Address Registers A and B. The 

Current Address registers A and B (Current ARA and ARB) 
are used to point to the source and destination addresses for 
DMA operations. The contents of the Base Address 
registers A and B (Base ARA and ARB) are loaded into the 



Current ARA and ARB registers at the end of a DMA 
operation if the user enables Base-to-Current reloading in 
the Completion Field of the Channel Mode register. This 
facilitates DMA operations without reloading of the Current 
registers. The ARA and ARB registers can be loaded during 
chaining, can be written to by the host CPU without wait 
states, and can be read by the CPU. 

Each of the Base and Current ARA and ARB registers 
consists of two words organized as a 6-bit Tag Field and an 
8-bit Upper Address in one word and a 16-bit Lower 
Address in the other (Figure 7). The Tag Field selects 
whether the address is to be incremented, decremented, or 
left unchanged, as well as the status codes associated with 
the address. The Tag Field also allows the user to insert 0.1. 
2, or 4 wait states into memory or I/O accesses addressed 
by the offset and segment fields. 



392 



ADDRESS REFERENCE FIELD - 

00 = SYSTEM I/O 

01 = SYSTEM MEMORY 

10 = NORMAL I/O 

11 = NORMAL MEMORY 



• ADDRESS CONTROL FIELD 

00 = INCREMENT ADDRESS 

01 = DECREMENT ADDRESS 
1X = HOLD ADDRESS 

- WAIT CONTROL FIELD 

00 = WAIT STATES 

01 • 1 WAIT STATES 

10 = 2 WAIT STATES 

11 = 4 WAIT STATES 



15 8 


7 6 5 4 3 2 





UPPER ADDRESS (A 16 -A 22 ) 


1 1 V V 'J 1 1 1 

vXV TAG 
i k\Vi i i i 


U 


LOWER ADDRESS (A -A 15 ) 



Figure 7. Address Registers A and B 



CHAIN 
ENABLE 

(CM13-15) 

BTOC 
RELOAD 
ENABLE 

(CM10-12) 

INTERRUPT 
ENABLE 

(CM7-9) 



Oa D 3 Dj D, Do I 



- MATCH CONTROL FIELD (CM16-17) 

- pulsed Back (CM18I 

- HARDWARE REQUEST MASK (CM19I 

- SOFTWARE REQUEST (CM20I 



p ls D14 D13 Di 2 Dn D10 



TC 
MC 

EOF 
TC 
MC 

EOP 
TC 
MC 

EOP 



I 



D 5 D 4 D 3 2 Di Do 



- DATA OPERATION FIELD (CM0-CM3) 



- FLIP BIT (CM4| 

(0) - ARA » src, ARB = dsl 

(1) - ARA « dsl. ARA = src 



- TRANSFER TYPE FIELD (CM5-6) 



Figure 8. Channel Mode Register 



The Address Reference Select Field in the Tag Field selects 
whether the address pertains to memory space or I/O 
space. Note that the N/S output pin may be either High 
(indicating Normal) or Low (indicating System). At the end of 
each iteration of a DMA Operation, the user selects to 
increment, decrement, or leave the address unchanged. I/O 
addresses, if changed, are always incremented/ 
decremented by 2. Memory addresses are changed by 1 if 
the address points to a byte operand (as programmed in the 
Channel Mode register's Operation field) and by 2 if the 
address points to a word operand. For word operands, the 
address must be even to avoid unpredictable results. An 
even or odd address may be used to point to a byte 
operand. Since memory byte operand addresses 
increment/decrement by 1 , they toggle between even and 
odd values. Since I/O byte operand addresses 
increment/decrement by 2, once programmed to an even or 
an odd value, they remain even or odd, allowing 
consecutive I/O operations to access the same half of the 
data bus. High bus is for even address; low bus is for odd. 

Current and Base Operation Count Registers. Both the 
Current and Base Operation Count registers may be loaded 
during chaining, and may be written to, and read from, by 
the host CPU. 

The 16-bit Current Operation Count register is used to 
specify the number of words or bytes to be transferred- 
and-searched. For word-to-word operations and byte-word 



funnelling, the Current Operation Count register must be 
programmed with the number of words to be transferred or 
searched. 

Each time data is transferred or searched, the Operation 
Count register is decremented by 1 . Once all of the data is 
transferred or searched: the transfer or search operation 
stops, the Current Operation Count register contains all 
zeroes, and the TC bit in the Status register is 1 . If the transfer 
or search stops before the Current Operation Count register 
reaches 0, the contents of the register indicate the number of 
bytes or words remaining to be transferred or searched. This 
allows a prematurely stopped channel to be restarted where 
it left off without requiring reloading of the Current Operation 
Count register. 

For byte-to-byte operations, the Current Operation Count 
register should specify the number of bytes to be transferred 
or searched. Setting the Current Operation Count register to 
0000 allows the maximum number of 64K bytes to be 
specified. 

Channel Mode Registers. The Channel Mode registers 
are two words wide. There are 21 bits defined in each 
Channel Mode register; the other 1 1 bits are unused. 
(Figure 8). The Channel Mode registers may be loaded 
during chaining and may be read by the host CPU. CPU 
reads of the Channel Mode register are slow reads and 
require insertion of multiple wait states. The Channel Mode 



393 



low word (bits 0-15) may be written to directly by the host 
CPU. The Channel Mode register selects what type of DMA 
operation the channel is to perform, how the operation is to 
be executed, and what action, if any, is to be taken when the 
channel finishes. 

The Data Operation Field and the Transfer Field select the 
type of operation the channel is to perform and the operand 
size of bytes or words. The possible bit combinations and 
their interpretation are given in Table 2. The Flip bit is used to 
select whether the Current ARA points to the source and the 
Current ARB points to the destination, or vice-versa. The 
types of operations are described in detail in the DMA 
operations section. 

Table 2. Channel Mode Coding 



Data Operation Field 




Operand Size 


Transaction 


Code ARA 


ARB 


Type 






Transfer 




0001 


Byte 


Byte 


Flowthrough 


100X Byte 


Word Flowthrough 


0000 Word 


Word Flowthrough 


0011 


Byte 


Byte 


Flyby 


0010 Word 


Word Flyby 




Transfer-and-Search 


0101 


Byte 


Byte 


Flowthrough 


11 OX Byte 


Word Flowthrough 


0100 Word 


Word Flowthrough 


0111 


Byte 


Byte 


Flyby 


0110 Word 


Word Flyby 






Search 




1111 


Byte 


Byte 


N/A 


1110 Word 


Word N/A 


101X Illegal 






Match Control Field/Transfer Type 


Code 


Match Control 


Transfer Type 


00 


Stop on No Match 


Single Transfer 


01 


Stop on No Match 


Demand (Bus Hold) 


10 


Stop on Word Match 


Demand (Bus Release) 


11 


Stop on Byte Match 


Demand Interleave 



The Completion Field defines the action taken by the 
channel at the end of a DMA operation. This field is 
discussed in the Completion Options section. 

The 2-bit Match Control Field selects whether matches use 
an 8-bit or 16-bit pattern and whether the channel is to 
Stop-On-Match or Stop-On-No-Match. See Table 2 and the 
Search section for details. 

The Software Request bit and Hardware Mask bit can be set 
and cleared by software command by loading the Channel 
Mode register. These bits are described in detail in the 
Initiating DMA Operations section. 



Don't care 



The DACK Control bit is used to specify when the PA CK pin 
is driven active. When this bit is cleared, the channel's DACK 
pin is active whenever the channel is performing a DMA 
Operati on, reg ardless of the type of transaction. If this bit is 
set. the DACK pin is inactive during chaining, Flowthrough 
Transfers, Flowthrough Transfer-and-Searches, and 
Searches. It is pulsed active during Flyby Transfers and 
Flyby Transfers-and-Searches when necessary to strobe 
data into or out of the Flyby peripheral. Flyby operations are 
discussed in detail in the Flyby Transactions section. 

Special Purpose Registers 

The special-purpose registers are: 

■ Pattern and Mask 

■ Status 

■ Interrupt Save 

■ Interrupt Vector 

■ Chain Address 

Pattern and Mask Registers. The 1 6-bit Pattern and Mask 
registers are used in Search and Transfer-and-Search 
operations. Both the Pattern and Mask registers may be 
loaded by chaining, and may be written to, and read from, 
by the host CPU (provided wait states are inserted since 
these registers are slow readable). The Pattern register 
contains the pattern which is compared to the read data. 
Setting a Mask register bit to 1 specifies that the bit always 
matches. The Search and Transfer-and-Search sections 
include further details. 

Status Register. The two 1 6-bit Status registers, depicted 
in Figure 9, are read-only registers which the CPU can read 
without wait states. Each of these registers reports on the 
status of its associated channel. 



| 15 | H 1 13 | 12 | 1 1 1 10 | 9 | 6 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | | 




COMPLETION 
STATUS 



HRQ \ HARDWARE 
V INTERFACE 
STATUS 



Figure 9. Status Register 



394 



The Interrupt Status Field contains the Channel Interrupt 
Enable (CIE) and Interrupt Pending (IP) bits. These bits are 
described in detail in the Interrupt section of this document. 

The DTC Status Field's four bits are the Second Interrupt 
Pending (SIP), Waiting For Bus (WFB), No Auto-Reload or 
Chain (NAC), and Chain Abort (CA) bits. These bits reflect 
the current channel state and are accessible to the CPU. 

When the channel has been properly initialized and is 
waiting for a command from the host CPU, all four of these 
bits are set to 0. If the channel requires access to the bus to 
carry out a DM A o peration, it sets the WFB bit. Whether the 
channel also sets BUSREQ Low depends on the setting of 
MMO, the Chip Enable bit, and the current status of the bus. 

If a channel completes a DMA operation and neither 
base-to-current reloading nor auto-chaining was enabled, 
the NAC is set. This bit is reset if the channel receives a Start 
Chain command. 

When two interrupts are queued in the channel, the SIP bit is 
set, which prohibits any further activity until an Interrupt 
Acknowledge clears this bit. 

Both CA and NAC bits are set by an EOP signal during 
chaining or if a Reset command is issued to the DTC. The CA 
bit is cleared when a new Chain Address Segment/Tag word 
or Offset word is loaded into the Channel's Address 
registers. NAC cannot be cleared until CA is cleared. 

The Hardware Interfac e Field 's Hardware Reques t (HRQ ) bit 
monitors the channel's DREQ input pin. When the DREQ pin 
is Low, the HRQ bit is set to 1 ; when the DREQ pin is High, 
the HRQ pin is cleared to 0. The Hardware Mask (HM) bit, 
when s et, prevents the DTC from responding to a Low on 
DREQ. Note, however, that the Hardwa re Req uest bit always 
reports the true (unmasked) status of DREQ regardless of 
the setting of the HM bit. 

The Completion Field indicates why the most cecent DMA 
operation ended. New data is loaded into these bits 
overwriting, and thereby erasing, the old setting. Three bits 
indicate whether the DMA operation ended as a result of a 
terminal count (TC), match condition (MC), or 
end-of-process (EOP) termination. If the DMA operation 
ended as a result of the Operation Count reaching 0, this is a 



TC termination and STO, the TC bit, is set to 1 . The MC bit is 
set to 1 if an MC termination occurred because the match 
condition has been met, regardless of whether 
Stop-On-Match or Stop-On-No-Match was s elected. The 
EOP bit is set to 1 only when an ext ernal EOP ends a DMA 
transfer; it is not set to 1 for an EOP issued during chaining. 
Note that two, or even all three bits, may be set if multiple 
reasons exist for ending the DMA operation. The MCH and 
MCL bits report on the match state of the upper and lower 
comparator bytes respectively. These bits are set to 1 when 
the associated comparator byte has a match and are reset 
otherwise, regardless of whether Stop-On-Match or 
Stop-On-No-Match is programmed. Regardless of the DMA 
operation performed, these bits determine which byte 
matched or did not match when using 8-bit matches with 
word searches and transfer-and-searches. 

The three reserved bits return 0s during reads. 

Interrupt Vector and Interrupt Save Registers. Each 
channel has an Interrupt Vector register and an Interrupt 
Save register. The Interrupt Vector is 8 bits wide and is written 
to, and read from, on AD0-AD7. The Interrupt Vector register 
contains the vector or identifier to be output during an 
Interrupt Acknowledge cycle. When an interrupt occurs 
(IP = 1) eithe r because a DMA operation terminated or 
because EOP was driven Low during chaining, the contents 
of the Interrupt Vector register and part of the Channel Status 
register are stored in the 16-bit Interrupt Save register 
(Figure 10). The Interrupt Save register is read without wait 
states by the CPU. 

With the vector and status safely stored, a new vector can be 
loaded into the Interrupt Vector register during chaining and 
a new DMA operation can be performed before an interrupt 
acknowledge cycle occurs. A second interrupt suspends 
activity in the channel until one of the bits is cleared. 

As soon as the first clear IP command is issued, the status 
and vector for the second interrupt are loaded into the 
Interrupt Save register and channel operation resumes. The 
DTC can retain only two interrupts for each channel; a third 
operation cannot be initiated until the first interrupt has been 
cleared. The Interrupt section has further details. 



|Pl 5 |0«|Pl3| D "| D " N °« I ° 8 1 1 08 1 Ds I Dt I "»l ° 2 I I °°1 



• VECTOR 
CHANNEL NUMBER 

■ = CH1 
1 = CH2 

■ TC 

■ EOP 

• MC 

■ CHAIN ABORTED 

■ MCL 
. MCH 

■ HARDWARE REQUEST 



Figure 10. Interrupt Save Register 



395 



.. ^^no.oij u i u ii upper 

Address and Tag field. The second word contains the 1 6-bit 
Lower Address portion of the memory address. The Tag field 
contains 2 bits used to designate the number of wait states to 
be inserted during accesses to the Chain Control Table. 

The Chain Address register may be loaded during chaining 
and the host CPU, without wait states, may read from and 
write to it. During chaining, if an EOP is issued to the DTC, 
the Chain Address register holds the old address. This is 
true even if the access failure occurred while new Chain 
Address data was being loaded, since, unless both words of 



LOWER ADDRESS 



WAIT STATES 

1 WAIT STATES 

2 WAIT STATES 
4 WAIT STATES 



3 2 10 



f . . j <«-t\ 



Figure 1 1 . Chain Address Register 



FUNCTIONAL DESCRIPTION 

Any DMA operation, transfer, search, or transfer-and- 
search, consists of three phases: 

■ The channel's registers are initialized to specify and 
control the desired DMA operation. 

■ The DMA operation is started and performed. 

■ The DMA operation is terminated and actions selected to 
occur on termination are performed. 

Reset 

Either hardware or software can reset the DTC. The software 
reset command is described in the Co mmand s section. 
Hardware resets are applied by pulling RESET Low. The 
DTC may be in control of the bus when a reset is applied. BAI 
is removed internally causing the outputs to go 3-state. If BAI 
remains High after reset, the DTC does not drive the bus 
unless BUSREQ is active. As soon as BAI goes inactive, the 
DTC places the AD -AD 15 , AD 16 -AD 23 , R/W, DS, N/S, M/IO, 
B/W, TBEN and RBEN signals in the high impedance state. 

Both software and hardware resets clear the Master Mode 
register to all 0s, clear the CIE, IP, and SIP bits to 0, and set 
the CA and NAC bits to 1 in each Channel's Status register. 
The contents of all other DTC registers will be unchanged by 
a software reset. Since a hardware reset may have been 
applied during a DMA operation being performed by the 
DTC channel, the channel's registers may contain 
indeterminate data following a hardware reset. 

The Master Mode register contains all Os after a reset. The 
DTC is disabled and the CPU interleave and hardware wait 
are inhibited. 

Because the CA and NAC bits in the Status register are set to 
1 by a reset, the channel is prevented from starting a DMA 
operation until its Chain Address register's Segment Tag and 
Offset fields are programmed and the channel is issued a 
Start Chain Command. 



Channel Initialization 

The Z8516/Z9516 DTC operates with a minimum of 
interaction with the host CPU. This goal is achieved by 
having the DTC load its own control parameters from 
memory into each channel. The CPU has to program only the 
Master Mode register and each Channel's Chain Address 
register. All other registers are loaded by the channels 
themselves from a table located in the System memory 
space and pointed to by the Chain Address register. This 
reloading operation is called chaining and the table is called 
the Chain Control Table (Figure 12). 

SYSTEM 
MEMORY 



Z8516/Z9516 
DTC 
CHANNEL 



CHAIN ADDRESS 
REGISTER 



RELOAD WORD 



DTC 
REGISTER 
DATA 



NEW CHAIN ADDRESS 



RELOAD WORD 



DTC 
REGISTER 
DATA 



CHAIN 
> CONTROL 
' TABLE-1 



CHAIN 

CONTROL 

TABLE-2 



Figure 12. Chaining and Chain Control Tables 



396 



The Upper and Lower Address fields of the Chain Address 
Register form a 24-bit address which points to a location in 
system memory space. Chaining is performed by 
repetitively reading words from memory. Note that the Chain 
Address register should always be loaded with an even 
Address; loading an odd Address causes unpredictable 
results. The 2-bit Tag field facilitates interfacing to slow 
memory by allowing the user to select 0, 1, 2, or 4 
programmable wait states. During chaining, the DTC 
automatically inserts the programmed number of wait states 
in each memory access. 

The Chain Address register points to the Reload Word, the 



first word in the Chain Control Table. The purpose of the 
Reload Word is to specify which registers in the channel are 
to be reloaded. Reload Word bits 10-15 are undefined and 
may be or 1 . Reload Word bits through 9 correspond to 
either one or two registers in the channel (Figure 1 3). When 
a Reload Word bit is 1 , the register(s) corresponding to that 
bit are to be reloaded; if 0, the register(s) corresponding to 
that bit are not to be reloaded. The data to be loaded into the 
selected register(s) follow(s) the Reload Word in memory 
(i.e., the data is stored at successively larger memory 
addresses). The Chain Control Table is a variable length 
table; the data is packed together. 



| iD.lD.lDzlD.lB.lD.lD.lD.l.hlDn 

I CHAIN ADDRESS (2 WORDS) 

I CHANNEL MODE (2 WORDS) 

INTERRUPT VECTOR (1 WORD) 

I PATTERN AND MASK (2 WORDS) 

BASE OP-COUNT (1 WORD) 

I BASE ARB (2 WORDS) 

I BASE ARA (2 WORDS) 

I CURRENT OP-COUNT (1 WORD) 

CURRENT ARB (2 WORDS) 

CURRENT ARA (2 WORDS) 



Figure 13. Reload Word/Chain Control Register 



When the channel is to reload itself, it first uses the Chain 
Address register's contents to load the Reload Word into the 
DTC's Chain Control register. Next, the Chain Address 
register's contents are incremented by two to point to the 
next word in memory. The channel then scans the Reload 
Word register from bit 9 down to bit to see which registers 
are to be reloaded. If no registers are specified (bits 9-0 are 
all 0), no registers are reloaded. If at least one of bits 9-0 are 
set to 1, the register(s) corresponding to the set bit are 
reloaded, the bit is cleared, and the Chain Address register 
is incremented by 2. The channel continues this operation of 
scanning the bits from the most significant to least significant 
bit position, clearing each set bit after reloading its 
associated registers, and incrementing the Chain Address 
register by 2. If all of bits 9 to are set, all the registers will be 
reloaded in order beginning with Current ARA and ending 
with Chain Address. Figure 14 shows examples of Chain 
Control Tables. Example 14a shows the ordering of data 
when all registers are to be reloaded. In example 14b, only 
some registers are reloaded. Once the channel is reloaded, 
it is ready to perform a DMA operation. When loading 
address registers, the Upper Address and Tag word are 
loaded before the Lower Address word. 



I1l1hl1l1l1l1l1l,l1 




CURRENT ARA (2 WORDS) 






CURRENT ARB (2 WORDS) 




CURRENT OP COUNT (1 WORD) 




BASE ARA (2 WORDS) 






BASE ARB (2 WORDS) 




BASE OP COUNT (1 WORD) 




PATTERN REGISTER (2 WORDS) 
MASK REGISTER 




| INTERRUPT VECTOR 




CHANNEL MODE (2 WORDS) 






CHAIN ADDRESS (2 WORDS) 





h|o|i|o|o|o|o|o|i|i 




CURRENT ARA (2 WORDS) - 


CURRENT OP COUNT (1 WORD) 




CHANNEL MODE |2 WORDS) — 




CHAIN ADDRESS (2 WORDS) — 



397 



Initiating DMA Operations. DMA operations can be 
initiated by: 

■ Software request 

■ Hardware request 

■ Starting after chaining 

Software Requests. The CPU can issue Software Request 
commands to start DMA Operations on a channel. The 
channel must then request control of the bus and perform 



transfers. See the description of the Software Request 
command for details. 

Hardware Requests. DMA operations can be started by 
forcing a channel's DREQ input L ow. T he Channel 
Response describes w hen t he Low DREQ signals are 
sampled and when the DREQ requests can be applied to 
start the next DMA operation after chaining (Figures 15 and 
16). 



HEAD OR FLVBY DMA ITERATION | | LAST ACCESS OF DMA ITERATION 
- T, ■+« T 2 // Twa or T 2 — T 3 - 



CLOCK 




NOTES: 1 . HIGH-to-LOW DREQ transitions will only be recognized after the HIGH-to-LOW 
transition of the clock during T, of a read or flyby DMA iteration. 

2. A HIGH-to-LOW DREQ transition must meet the conditions in Note 1 and TsDRQ(c) 
must occur before state T 3 of the last access of the DMA iteration if the channel is to 
retain bus control and immediately start the next iteration. DREQ may go HIGH 
before TsDRQ(c) if it has met the TwDRQ parameter. 

3. Flyby and Search transactions have only a single access; parameter TsDRQ(c) 
should be referenced to the start of T 3 of the access. All other operations will always 



See Appendix D for timing parameters 

* State T, P is a pseudo-T, state, without active AS generated following termination of any 
DMA operation. 



Figure 15. Sampling DREQ During Single Transfer DMA 



Starting After Chaining. If the software request bit of the 
Channel Mode register is loaded with a 1 during chaining, 
the channel performs the programmed DMA operation at 
the end of chaining. If the channel is programmed for Single 
Operation or Demand mode, it performs the operation 
immediately. The channel gives up the bus after chaining 
and before the operation if the CPU interleave bit in the 
Master Mode register is set. See the Channel Response 
section for details. Note that once a channel starts a 
chaining operation by fetching a Reload Word, it retains bus 
control at least until all of the registers specified in the Reload 
Word have been loaded from memory. 

Bus Request/Grant 

Before the DTC can perform a DMA Operation, it must gain 
control of the system bus. The BUSREQ and BAI interface 
pins provide connections between the DTC and the host 
CPU and other devices, if present, to arbitrate which device 
has control of the system bus. When the DTC wants to gain 
bus control, it drives BUSREQ High. 

After the DTC drives BUSREQ High, the CPU relinquishes 
bus control and drives its bus acknowledge signal Low. 
When the DTC's BAI input goes High, it may begin 



performing operations on the system bus. When the DTC 
finishes its operation, it stops driving BUSREQ High. 

When more than one device is used, a priority encoder/ 
decoder or hardware daisy-chain encoder and a priority 
decoder are used to decide the bus grant priority. 

DMA Operations 

There are three types of DMA operations: Transfer, Search, 
and Transfer-and-Search. Transfers move data from a 
source location to a destination location. Two types of 
transfers are provided: Flowthrough and Flyby. Searches 
read data from a source and compare the read data to the 
contents of the Pattern register. A Mask register allows the 
user to declare "don't care" bits. 

The user can program the search to stop either when the 
read data matches the masked pattern (Stop-On-Match) or 
when the read data fails to match the masked pattern 
(Stop-On-No-Match). Transfer-and-Search combines the 
two functions to facilitate the transferring of variable length 
data blocks. Like Transfer, Transfer-and-Search can be 
performed in either Flowthrough or Flyby mode. 



(A) Sampling of DREQ While in Bus Hold Mods 




(B) DREQ Sampling in Demand Mode During DMA Operations 




(C) Sampling DREQ al Hie End of Chaining 




(D) Sampling OREO at End of BaseloCurrent Reloading 

NOTES: 1 . DREO must be LOW from the start of T 5 DRQ(C) to the end of ThDRQfc) to ensure that the request is recognized. Failure to meet this setup time will result 
in the channel releasing the bus. 

2. T s is a setup state, generated before entering DMA operation cycle. 

3. T AU 2. T A U3. and T A U4 are auto-reload states, followed by TCD (chain decision) state. 



Figure 16. DREQ Sampling Demand Mode 



Transfers. The transfer operation uses four channel 
registers: 

■ Current ARA 

■ Current ARB 

■ Current Operation Count 

■ Channel Mode 

Channel Mode register bit CM 4 is called the Flip bit and is 
used to select whether Current ARA is to point to the source 
and Current ARB is to point to the destination or whether 
Current ARA is to point to the destination and Current ARB is 



to point to the source. The Current Operation register 
specifies the number of words or bytes to be transferred. 

Bits CM 3 -CM in the Channel Mode register program 
whether a Flowthrough or Flyby transfer is to be performed 
in either two or three steps. First, the channel outputs the 
address of the source and reads the source data into the 
DTC's Temporary register. In two-step Flowthrough Transfer, 
the channel then addresses the destination and writes the 
Temporary register data to the destination location. The 
three-step Flowthrough operation (i.e. the byte-word 
funnelling) is described later in this section. The source and 
destination for Flowthrough Transfers can be memory 



399 



locations, peripheral de vices, o r a memory location and a 
peripheral device. The DACK output for the transferring 
channel may be programmed to be inactive or active during 
the transfer. This is controlled by bit CM 1 8 in the Channel 
Mode register. 

Flyby transfers provide improved transfer throughput over 
Flowthrough but are restricted to transfers between memory 
and peripherals or between two peripherals. Flyby 
operations are described in detail in the Flyby Transactions 
section. 

Transfers can use both byte- and word-sized data. 
Flowthrough byte-to-byte transfers are performed by 
reading a byte from the source and writing a byte to the 
destination. The Current Operation Count register must be 
loaded with the number of bytes to be transferred. Both the 
Current ARA and ARB registers, if programmed to 
increment/decrement, will change by 1 if the register points 
to a memory space (TG6 = 2) and by 2 if the register points 
to an I/O space (TG 6 = 0). 

Flowthrough word-to- word transfers require that the Current 
Operation Count specify the number of words to be 
transferred. Both the Current ARA and ARB registers, if 
programmed to increment/decrement, will change by 2 
regardless of whether the register points to a memory or an 
I/O space. 

Byte-word funnelling provides packing and unpacking of 
byte data to facilitate high speed transfers between byte and 
word peripherals and/or memory. This funnelling option can 
only be used in Flowthrough mode. Funnelled Flowthrough 
transfers are performed in three steps. For transfers from a 
byte source to a word destination, two consecutive byte 
reads are performed from the source address. The data 
read is assembled into the DTC's Temporary register. In the 
third step, the Temporary register data is written to the 
destination address in a word transfer. Funnelled transfers 
from a word source to a byte destination are performed by 
first loading a word from the source into the DTC's 
Temporary register. The word is then written out to the 
destination in two byte writes. For funnel operations, the 
byte-oriented address must be in the Current ARA register 
and the word-oriented address must be in the Current ARB 
register. The Flip bit (CM 4 ) in the Channel Mode register is 



used to specify which address is the source and which is the 
destination. When the byte address is to be incremented or 
decremented, the increment/decrement operation occurs 
after each of the two reads or writes. The Current Operation 
Count Register must be loaded with the number of words to 
be transferred. 

In byte-to-word funnelling operations it is necessary to 
specify which half of the Temporary register is written out 
first. Table 3 summarizes these characteristics for both 
byte-to-word and word-to-byte funnelling operations. The 
criteria to determine the packing/unpacking order is based 
on whether the Current ARB register is programmed for 
incrementing or decrementing of the address. Note that if 
the address is to remain unchanged (i.e. if bit TG 4 on the Tag 
Field of the Current ARB register is I), the increment/ 
decrement bit (bit TG3) still specifies the packing order. 

Search. Searches use five of the Channel registers: 

■ Current ARA 

■ Current ARB 

■ Operation Count 

■ Pattern and Mask 

■ Channel Mode 

Channel Mode register bit CM4 is called the Flip bit and is 
used to select either Current ARA or Current ARB as the 
register specifying the source for the search. Only one of the 
Current Address registers is used for search operations 
since there is no destination address required. The Current 
Operation Count register specifies the maximum number of 
words or bytes to be searched. 

Search operations involve repetitive reads from the 
peripheral or memory until the specified match condition is 
met. The search then stops. This is called a Match Condition 
or MC termination. Each time a read is performed, the 
Source address, if so programmed, is incremented or 
decremented by 1 . If the match condition has not been met 
by the time the Operation Count reaches 0, the value 
forces a TC termination, ending the search. Sear ches can 
also stop due to a Low being applied to the EOP in terface 
pin. During a search operation, the channel's DACK output 



Table 3. Byte/Word and Word/Byte Funneling 



Funneling 


Current ARB 


Increment/Decrement and 


Direction 


Tag Field 


Packing/Unpacking Rules 




TG 4 


TG 3 




Word-to-Byte 








Incremnt ARB, Write High Byte First 


(Flip Bit = 1) 





1 


Decrement ARB, Write Low Byte First 




1 





Hold ARB, Write High Byte First 




1 


1 


Hold ARB, Write Low Byte First 


Byte-to-Word 








Increment ARB, Read High Half of Word First 


(Flip Bit = 0) 





1 


Decrement ARB, Read Low Half of Word First 




1 





Hold ARB, Read High Half of Word Written First 




1 


1 


Hold ARB, Read Low Half of Word Written First 



400 



will be either inactive or active throughout the search. This is 
controlled by bit CM-ie in the Channel Mode register. The 
peripheral or memory reads performed during search follow 
the timing sequences described in the Flowthrough 
Transactions sections. 

On each read during a Search operation, the DTC's 
Temporary register is loaded with data and compared to the 
Pattern register. The user can select whether the search is to 
stop when the Pattern and Temporary register contents 
match or when they do not match. This Stop-On-Match/ 
Stop-On-No-Match feature is programmed in bit CM 17 of the 
Channel Mode register. CM 2 is an enable for the output of 
the comparator and allows the MC signal to be generated. A 
Mask register allows the user to exclude, or mask, selected 
Temporary register bits from the comparison by setting the 
corresponding Mask register bit to 1. The masked bits 
always are defined to match. Thus, in Stop-On-Match, 
successful matching of the unmasked bits, in conjunction 
with the always-matched masked bits, causes the search to 
stop. For Stop-On-No-Match, the always-matched masked 
bits are, by definition, excluded from not matching and 
therefore excluded from stopping the search. 

For word reads the user may select either 8-bit or 16-bit 
compares through Channel Mode register bit CM-|6- In an 
8-bit, Stop-On-Match, word-read operation, successful 
matching of either the upper or lower byte of unmasked 
Pattern and Temporary registers bits stops the search. Both 
types do not have to match. In 16-bit Stop-On-Match with 
word reads, all unmasked Pattern and Temporary register 
bits must match to stop the search. In an 8-bit or 16-bit, 
Stop-On-No-Match, word-read Search operation, failure of 
any bit to match terminates the Search operation. 

In an 8-bit Stop-On-Match with byte-reads, the Search stops 
if either the upper or lower byte of unmasked Pattern and 
Temporary register bits match. For an 8-bit Stop-On-No- 
Match with byte reads, failure of matching in any unmasked 
Pattern and Temporary register bit causes the search to 
stop. For 8-bit searches, the upper and lower bytes of the 
Pattern and Mask register should usually be programmed 
with the same data. Failure to set the upper and lower bytes 
of the Pattern and Mask registersto identical values results in 
different comparison criteria being used for the upper and 
lower bytes of the Temporary register. Users failing to 
program identical values for the upper and lower bytes can 
predict the results by recognizing that in 8-bit 
Stop-On-Match, the search ends if all the unmasked bits in 
either the upper or lower byte match, and for 8-bit 
Stop-On-No-Match, the failure of any unmasked bit to match 
ends the search. For word reads the Temporary register 
high and low bytes are loaded from ADs-ADi 5 and AD0-AD7 
respectively. In byte reads, except in funnelling, the read 
byte is duplicated in both halves of the Temporary register. 



Transfer-and-Search. Transfer-and-Search combines the 
operations of the Transfer and the Search functions. The 
registers which control Transfer-and-Searches are: 

■ Current ARA 

■ Current ARB 

■ Operation Count 

■ Pattern and Mask 

■ Channel Mode 

A Transfer-and-Search operation ends when the data 
transferred meets the match condition specified in Channel 
Mode register bits CM17-CM16. The Mask and Pattern 
registers indicate those bits being compared with the 
Temporary register contents. Like Transfers and Searches, 
Transfers-and-Searches are also terminated if the operation 
count goes to or if a Low is applied to the EOP pin. 
Regardless of whether Transfer-and-Search stops because 
of a TC, MC, or EOP it always completes the iteration by 
writing to the destination address before ending (writing 
twice for word-to-byte funnelling). 

In Flowthrough mode, the Transfer-and-Search timing is 
identical to Flowthrough Transfer. While the data 'is in the 
Temporary register, it is masked by the Mask register and 
compared to the Pattern register. For word Transfer and 
Transfer-and-Search, the high and low bytes of the 
Temporary register are always written to, and read from, 
AD 8 -AD 15 and AD -AD 7 respectively. For byte Transfer and 
Transfer-and-Search, the byte read is always loaded into 
both halves of the Temporary register and the entire register 
is driven directly out onto the AD -ADi 5 bus. 
Transfer-and-Search can also be used with byte word 
funnelling. In funnelling, the match is an 8-bit match as 
determined by the setting of the bit CM 16 . 

Flyby Transfer-and-Search can be used to increase 
throughput for transfer between two peripherals or between 
memory and a peripheral. Memory-to-Memory Flyby is not 
supported. Also, in Flyby, the operand sizes of the source 
and destination must be the same; funnelling is not 
supported. A complete discussion of Flyby timing is given in 
the Flyby Transactions section. During a Flyby 
Transfer-and-Search, data is loaded into the Temporary 
register to facilitate the comparison operation and, at the 
same time, data is transferred from the source to the 
destination. When byte operands are used, data is loaded 
into both bytes of the Temporary register, from the AD 8 -AD 15 
bus if the Current ARA register is even, and from AD -AD/ 
line if the Current ARA register is odd. This alternates for 
memory bytes so the user must drive both halves of the bus 
to use the search. When word operands are used, data is 
loaded directly from AD 8 -ADis and AD0-AD7 into the 
Temporary register's high and low bytes respectively. 



401 



Channel Response 

Channel Mode register bits CM6-CM5 select the channel's 
response to the request to start a DMA operation. The 
response falls into either of two types: Single Operation or 
Demand. There are three subtypes for Demand operations: 
Demand Dedicated with Bus Hold, Demand Dedicated with 
Bus Release, and Demand Interleave. For Search 
operations, one iteration consists of a single read operation 
and a comparison of the read data to the unmasked Pattern 
register bits. The Operation Count is decremented by 1 and 
the Current Address register, if so programmed, is 
incremented or decremented. For Transfer and Transfer- 
and-Search operations, a single iteration comprises reading 
data from the source, writing it to the destination, comparing 
the read data to the unmasked Pattern register bits 
(Transfer-and-Search only), decrementing the Operation 
Count by 1, and incrementing/decrementing the Current 
ARA amd ARB registers if so programmed. In byte-word 
funnelling, a single iteration consists of two reads followed by 
a write (Byte-to-Word funnelling) or one read followed by two 
writes (Word-to- Byte funnelling). In all Transfer and 
Transfer-and-Search cases the iteration does not stop until 
the data in the Temporary register is written to the 
destination. (Appendix B). 

Single Operation. The Single Operation response is used 
with peripherals which transfer single bytes or words at 
irregular intervals. Each Software Request command 
causes the channel to perform a single iteration of the DMA 
operation. Similarly, if the Software Request bit is set by 
chaining, the channel performs a single iteration of the DMA 
operation at the end of chai ning. E ach application of a 
High-to-Low transition on the DREQ input also causes a 
single iteration of the DMA operation. If the hardware mask 
bit is set when the High to Low transition is made, the 
iteration is performed when the mask is cleared, providing 
the DMA operation has not terminated. See the Set/Clear 
Hardware Mask bit command in the Command section for 
details. Each time a Single Operation ends, the channel 
gives up co ntrol o f the bus unless a new transition has 
occurred on DREQ. The new transition can occur anytime 
after the High-to-Low ALE transition of a read or Flyby 
memory or I/O access of the DMA iteration. Figure 1 5 shows 
the times after which a new transition can be applied and 
recognized to avoid giving up the bus at the end of the 
current iteration. 

Demand Dedicated With Bus Hold. In Demand 
Dedicated with Bus Hold (abbreviated Bus Hold), the 
application of a Software Request command, the setting 
during chaining of the software request bit, or applying a 
Low level on the DREQ input, causes the channel to acquire 
bus control. 

If DACK is programmed as a level output (CM-ig = 0), DACK 
is active while the channel controls the bus. A Software 
Request causes the channel to request the bus and perform 
the DMA operations until TO MC, or EOP occurs. 



Once the channel gains bus control due to a Lo w DRE Q 
level, it samples DREQ as shown in Figure 16. If DREQ is 
Low, an iteration of the DMA operation is performed. If 
DREQ is High, the channel retains bus control and 
continues to drive all bus control signals active or inactive, 
but performs no DMA operation. Thus the user can start, o r 
stop, execution of DMA operations by modulating DREQ. 
OnceTC, MC, or EOP occurs, the channel releases the bus, 
or, if chaining or Base-to-Current reloading is to occur, 
performs the desired operation. After chaining or 
Base-to-Current reloading, if the channel is still in Bus Hold 
mode and does not have a set Software Request bit (set 
either by chaining or co mmand ), the channel relinquishes 
bus control unless a Low DREQ level occurs within the time 
limits. 

Demand Dedicated With Bus Release. In Demand 
Dedicated with Bus Release (abbreviated Bus Release), a 
Software Request command causes the channel to request 
the bus and performs the programmed DMA operation until 
TC, MC, or EOP occurs. If the channel was programmed for 
Bus Release and the Software Request bit was set during 
chaining, the channel starts the DMA operation as soon as 
chaining ends, without releasing the bus, and continues 
performing the operation until TC, MC, or EOP occurs. 

When an active Low DREQ is applied to a channel 
programmed for Bus Release, the channel acquires the bus 
and pe rforms DMA operations until TC, MC, or EO P occu rs 
or until DREQ goes inactive. Figure 1 6 shows when DREQ is 
sampled to determine if the channel should perform another 
cycle or release the bus. Note that this sampling also occurs 
on the l ast cyc le of a chaining operation. If a channel has an 
active DREQ at the end of chaining, it performs DMA 
operations immediately, without releasing the bus. When a 
TC, MC, or EOP occurs terminating a Bus Release mode 
operation, the channel, if enabled for chaining and/or 
Base-to-Current Reloading, performs chaining and/or 
reloading (assuming the Status register's SIP bit is clear) 
without releasing the bus. 

If the SIP bit of Channel Mode register is set when a DMA 
termination occurs, the channel reliquishes the bus control 
until an Interrupt Acknowledge is received and the SIP bit is 
cleared. After an interrupt is serviced, the channel, if 
enabled for the termination, performs the Base-to-Current 
reloading and/or chaining. 

If an active request is not applied and the channel is in 
Demand Dedicated with Bus Hold, the channel goes into 
state THLD (Figure 16a). If an active request is not applied 
and the channel is in Demand Dedicated with Bus Release 
or Demand Interleave mode, it releases the bus. Note that 
even if an active request is applied in Demand Interleave, 
the channel may still release the bus. The request for 
Demand Interleave should continue to be applied to ensure 
that the channel eventually responds to the request by 
acquiring the bus (i.e. the request is not latched by the 
channel). 



402 



Demand Interleave. Demand Interleave behaves in 
different ways depending on the setting of Master Mode 
register bit MM2. If MM2 is set, the DTC always reliquishes 
bus control and then again requests it after each DMA 
iteration. This permits the CPU and other devices to gain 
access to the bus in the following execution control 
sequence: Channel 1, CPU, Channel 2, CPU, Channel 1, 
CPU. The CPU could be some other external device. 

When MM2 is clear and both channels have active requests 
and are in Demand Interleave mode, control toggles 
between the channels after each DMA operation iteration 
and the DTC retains bus control until both channels are 
finished with the bus. Appendix B's, Figure B.2 is a flowchart 
of the Demand Interleave operation. 

A software or hardware request causes a channel 
programmed for Demand Interleave to perform interleaved 
DMA operations until TC, MC, or EOP. If the Software 
Request bit is set during chaining, the channel retains the 



bus after chaining and immediately starts perf orming DMA 
iterations interleaving after the first operation. If DREQ is Low 
on the last cycle during chaining, the channel performs a 
single iteration immediately after chainin g and interleaves 
thereafter until TC, MC, or EOP occurs or DREQ goes High. 
If the latter occurs, the channel relinquishes the bus 
interleaved operations. If a TC, MC, or EOP occurs, the 
channel first performs chaining and/or Base-to-Current 
reloading (assuming SIP is cleared) before interleaving. 



The waveform of DACK is progr amme d in Channel Mode 
register (CM-is). The Pulsed DACK is only for Flyby 
transactions. Figure 1 7 shows the timing for a single Search 
or Flyby operation. State T W a is optionally inse rted if 
programmed. For more than one iteration, the level DACK 
output stays active during the ti me the channel has bus 
control. When CM 18 is set, the DACK output is inactive 
during Flowthrough modes. 




NOTES: 1. Slate Ttp is a pseudo-Ti state, without active AS generated following termination ot any DMA 

2. State Taui . is an auto-initialization state generated following the TC. MC, or EOP termination. 

3. Level DACK Rising Edge occurs as shown if auto-reloading is not programmed, otherwise it stays 



Low tor three additional clock cycles. 



Figure 17. DACK Timing 



Wait States 

The number of wait states to be added to the memory or I/O 
transfer can be programmed by the user as 0, 1 , 2, or 4; it 
can be programmed separately for the Current Address 
registers A and B and for the Chain Address register. This 
allows different speed memories and peripherals to be 
associated with each of these addresses. The Base Address 
registers A and B also have a Tag Field which is loaded into 
the Current ARA and ARB registers during Base-to-Current 
reloading. Because many users utilizing the software 
programmable wait states do not need the ability to 



generate hardware wait states through the WAIT pin, the wait 
function can be disabled by clearing the Wait Line Enable bit 
(MM2) in the Master Mode register. 

During DMA transactions, the WAIT input is sampled in the 
middle of the T 2 state. If WAIT is High, and if no 
programmable wait states are selected, the DTC proceeds 
to stat e T 3 . Otherwise, at least one wait state is inserte d. The 
WAIT line is then sampled in the middle of state T W a. If WAIT 
is High the DTC proceeds to state Tg. Otherwise additional 
wait states are inserted (Figure 1 8). 




ThWT(c) 



-«-@ ThWT(c) 



Figure 18. WAIT Timing 



403 



In a transaction when both har dware and software wait 
states are inserted, each time the WAIT line is sampled Low, 
a hardware wait state is inserted in the next cy cle. T he 
software wait state insertion is suspended until WAIT is 
sampled and is High. The hardware wait states may be 
inserted anytime during the software wait state sequence. 
Hardware wait states are served consecutively rather than 
concurrently with software wait states. For example, assume 
for a Flowthrough I/O Transaction that a user has 
progr ammed four software wait states. Driving a Low on the 
WAIT input during J 2 for t wo cyc les would insert two 
hardware wait states. Driving WAIT High for three cycles 
would allow in sertion of three of the four software wait states. 
Driving WAIT Low for two more cycle s wou ld insert two more 
hardware wait states. Finally, driving WAIT High would allow 
the final software wait state t o be inserted. During this last 
software wait state, the WAIT pin would be sampled for the 



last time. If it is High, the channel proceeds to state T3. If the 
pin is Low, the channel inserts hardware wait states until the 
pin goes High and the channel then enters state T 3 to 
complete the I/O transaction. 

DMA Transactions 

There are three types of transactions performed by the 
Z8516/Z9516 DTC: Flowthrough, Flyby, and Search. 

Flowthrough Transactions. A Flowthrough Transaction 
(Figure 1 9) consists of three states: T-| , T 2 , and T 3 as shown 
in Figure 20. The user may insert software wait states 
through the Tag fields of the Current ARA and ARB registers. 
In addition, if Master Mode register bit MM2 = 1 , hardware 
wait s tates may be inserted by driving a Low signal on the 
WAIT pin. 



PERIPHERAL 
OR 
MEMORY 



Z8516/Z9516 
DTC 

TEMPORARY 
REGISTER 



PERIPHERAL 
OR 
MEMORY 



Figure 19. Flowthrough Transaction 



The M/IO and N/S lines reflect the appropriate level for the 
current cycle early in T1 . The TGg and TG7 bits of the current 
ARA and ARB registers should be programmed properly. 
The ALE output is pulsed High to mark the beginning of the 
cycle. The offset portion of the address for the accessed 
peripheral appears on AD -AD 15 during T-|. The R/W and 
B/W lines select a_read or wrjte operation for bytes or words. 
The R/W, N/S. M/IO, and B/W lines become stable during T, 
and remain stable until after T3. 

I/O address space is byte-addressed but both 8- and 1 6-bit 
data sizes are supported. During I/O transactions the B/W 
output is High for byte transactions and Low for word 
transactions. For I/O transactions, both even and odd 
addresses can be output, hence the address bit output on 
ADo may be or 1 . 

The channel can_perform both I/O read and write 
operations; the M/IO line is Low. During an I/O read, the 
AD -AD 15 bus is placed in the high impedence state by the 
DTC during T 2 . The DTC drives the DS output Low to signal 
the peripheral that data can be gated onto the bus. The DTC 
strobes the data into its Temporary register during T 3 . DS is 
driven High to signal the end of the I/O transaction. During 
I/O write, the DTC drives the contents of the Temporary 
register onto the ADo-AD 15 bus and shortly after drives the 
DS output Low until T 3 . Peripherals may strobe the data on 
the AD bus into their internal registers on either the clock's 
falling or rising edge. If the peripheral is also to be accessed 



in a Flyby transaction, data should be written only on the 
rising edge of DS. 

For byte I/O writes, the channel drives the same data on data 
bus lines AD -AD 7 and AD 8 -AD 15 . During byte I/O reads, 
when the address bit on AD is 0, the DTC strobes data in 
from data lines AD 8 -AD 15 . During byte I/O reads, when the 
address bit on ADo is 1 . the DTC strobes data in from data 
lines AD0-AD7. Thus, when an 8-bit peripheral is connected 
to the bus, its internal registers typically are mapped at either 
all even or all odd addresses. To simplify accesses to 8-bit 
peripherals, byte oriented I/O addresses are incremented/ 
decremented by 2. 

The channel can perform the I/O read and memory write 
operation, the memory read and I/O write operation, and the 
memory read and memory write operation. The timing for all 
Flowthrough transactions is the same. 

During chaining operations the DTC reads words from an 
address in System memory pointed to by the active 
channel's Chain Address register. Those chaining 
operations are performed identically to the Flowthrough 
memory read transactions, except that the data is loaded 
into an internal DTC Channel register rather than the 
Temporary register. Chaining never causes a write or a byte 
read; thus all memory writes or all byte accesses are due to 
DMA operations. A typical memory operation consists of 
three states; T-i , T 2 , and T3, as shown in Figure 20. The user 



404 




AD0-AD15 



Figure 20. Flow/through Transaction Timing 



may select to insert 1,2, or 4 software wait states between T2 
and T3 by programming the Tag field of the Current Address 
register or the Chain Address register. If the Wait Line Enable 
bit in the Master Mode register is set, the user may also insert 
har dware w ait states between T 2 and T 3 by driving a Low on 
the WAIT line. The operation of Flowthrough memory 
transactions is identical to Flowthrough I/O transactions. 

Flyby Transactions. Flyby transfer and Flyby transfer- 
and-search operations are performed in a single cycle, 
providing a transfer rate significantly faster than 
Flowthrough. In transfers, Flyby mode operations can only 
be performed between memory and peripheral or between 



peripheral and peripheral. Memory-to-memory operations 
cannot be performed in Flyby mode (Figure 21). 

The Flyby Transaction can be used only with peripherals 
having a special Flyby signal input or with external logic. 
This Flyby input is connected to the channel's DACK output. 
For memory-peripheral Flyby, the address of the source 
memory location must be programmed in the Current ARA 
register. The Current ARB register must be programmed 
with the destination memory location for peripheral-memory 
Flyby. For Flyby peripheral-to-penpheral transaction, if both 
peripherals have a Flyby input, onl y one (the Flyby 
peripheral) should be connected to DACK; the other 



PERIPHERAL 
OR MEMORY 



Z8516/Z9516 
DTC 



MEMORY _ 
ADDRESS 



PACK . 



FLYBY 
PERIPHERAL 
(s.g.. FIOI 



Figure 21 . Flyby Transaction 



405 



(Non-Flyby) peripheral's Flyby input should be held High 
during the Flyby operation. When the Non-Flyby peri pheral 
is a destination and not connected to the channel's DACK 
output, its address should be programmed in the current 
ARB register. When the Non-Flyby peripheral is a source, its 
address should be programmed in the current ARA register. 
Table 4 explains that a set Flip bit (CM 4 = 1) is for Flyby 
peripheral to Non-Flyby peripheral or Memory Write 
transaction (From Flyby Transaction) and a clear Flip bit 
(CM 4 = 0) is for the Memory or Non-Flyby peripheral read to 
Flyby peripheral transaction (To Flyby Transaction). 

A Flyby operation requires three states: Ti, Tg, and T 3 . 



During Ti the channel pulses ALE and outputs. The R/W 
line is High for To-Flyby Transaction and Low for From-Flyby 
Transaction (Figure 22). 

Table 4. Flyby Transaction 









Address of Memory 








or Non-Flyby 


Transaction 


CM 4 


R/W 


Peripheral 


To Flyby 





HIGH 


ARA 


From Flyby 


1 


LOW 


ARB 



TO FLYBY 
PERIPHERAL 



FROM FLYBY 
PERIPHERAL 




Toggles lor memory access in logical address space only. 
"For physical addressing only. 
"NIS will be low (or I/O transactions. 



(A) Address is current ARA 
(B| Address is current ARB 



Figure 22. Flyby Transaction Timing 



406 



The channel's M/IO and N/S lines are coded as specified by 
the Current ARA or ARB Tag field. The B/W line indicates the 
operand size programmed in the Channel Mode register 
Operation field. During T, the channel drives R/W to indicate 
the transaction direction; during T2 the channel drives both 
DS an d DACK active. The Flyby Peripheral connected to 
DACK inverts the R/W signal to determine whether it is being 
read from or written to (Figure 23). 



The pulsed DACK input serves two purposes: To select the 
peripheral for the Read/Write, and to provide timing 
information on when to drive data onto, or input data from, 
the AD -AD 15 bus. Because the Flyby Peripheral never is 
explicitly addressed by AD0-AD15, it must know which 
internal register is to be loaded from, or driven onto, the 



AD -AD 15 bus. On state T 3 , the DS and DACK lines are 
driven inactive to conclude the transfer. In Transfer- 
and-Search mode, data is loaded into the DTC's Temporary 
register on the Low-to-High DS transition in order to perform 
the search function. 

To provid e adequate data setup time, the rising edge of DS 
or DACK should be used to perform the wite to the tra nsfer 
destination. To extend the active time of DS and DACK, wait 
states can be inserted between T 2 and T 3 . Software wait 
states can be inserted by programming the appropriate 
code in the Tag field of the Current ARA or AR B reg isters. 
Hardware wait states can be inserted by pulling WAIT Low if 
the Wait Line Enable bit in the Master Mode register is set. 
The WAIT line is sampled in the middle of the T 2 or T WA state. 




R/W' = BAI • R/W + BAI ■ R/W 

DS' = BAI • DACK 4 B7S1 • DS 

RD = DACK • B/W .BAUDS. R/W • BAI 

WR = DACK • R/W • BAI + B5 • R/W • BAi 



Figure 23. Flyby Peripheral Interface 



-T 2 or Ti- 



-T W A or T 2 




EXTERNAL 
EOP 



INTER NAL 
EOP 



*\ r 



a) EOP SAMPLING AND GENERATION DURING DMA OPERATIONS 

CHANNEL HOLDS BUS I CHANNEL RELEASES BUS 



-Thld- 



-Thld- 



-TIDLE— 



EOP 



b) SAMPLING OF EOP DURING BUS HOLD 

Notes: 

1. The diagram lists state names tor both I/O and memory accesses. Sampling of EOP will occur on the falling edge of state T3. 

2. State T 1P is a pseudo-Ti. state, without active AS generated following termination of any DMA operation. 

3. State TAU1 is an auto-inittalization state generated following the TC, MC, or EOP termination. 



Figure 24. EOP Timing 



407 



Termination 

There are three ways a Transfer-and-Search or Search 
operation can end and two ways a Transfer operation can 
end. When a channel's Current Operation Count goes to 0, 
the DMA operation ends; this is called a Terminal Count (TC) 
termination . A DMA operation can also be stopped by 
drivin g the EOP pin Low with external logic; this is called an 
EOP termination. Match Condition (MC) is the last method of 
termination which occurs when the data being 
Transferred-and-Searched or Searched meets the match 
condition programmed in Channel Mode register bits 
CM -i 7-CM ! 6 . These bits allow the user to stop when a match 
occurs between the unmasked Pattern register bits and the 
data read from the source, or when a no-match occurs. Both 
byte and word matches are supported. MC terminations do 
not apply to Transfer operations since the pattern matching 
logic is disabled in Transfer mode. 

End of Process 

The End-of-Process (EOP) int erfac e pin is a bidirectional 
signal. Whenev er a T C, MC, or EOP termination occurs, the 
PTC drives the EOP pin Low. During DMA o perati ons, the 
EOP pin is sampled by the DTC to determine if EOP is being 
drive n Low by external logic. Figure 24 shows when internal 
EOPs are gene rated marking termination of all Transfers and 
when the EOP pin is s ampl ed during the DMA iteratio n. Th e 
generation of internal EOPs and sampling of external EOPs 
for Transfer-and-Searches follow s the same timing used for 
Trans fers. Since there is a single EOP pin for both channels, 
EOPs should only be driven Low by a channel while that 
channel is bein g serv iced. This can be accomplished by 
selecting a leve l DACK outp ut (CMR i 8 = 0) and gating each 
channel's EOP request with DACK, as shown in Figure 25. 



DREQ, 

DACKi 

ZS51S/Z9S1S 
DTC 

EOP 

DREQ 2 
DACK; 




PERIPHERAL 1 






f-^vW + 5V 














PERIPHERAL 2 





^ SYSTEM BUS <j 

Notes: 

1. External E OP st ops channel. 

2. DTC drives EOP Active on TC and MC. 

3. Channel should apply EOP only it its DACK is active. 

Figure 25. EOP Connection 

If an EOP is detected while the channel is trying to reload the 
Chain Address register, the new Chain Address Offset and 
Segment are discarded and the old address +2 is 
preserved to allow inspection of the erroneous address. 



Programming Completion Options. When a channel 
ends a DM A operation, the reason for ending is stored in the 
Completion Status Field of the channel's Status register 
(Figure 7). This information is retained until the next DMA 
operation ends at which time the Status register is updated 
to reflect the reason(s) for the latest termination. More than 
one bit in the Completion Field could be set to 1 . All three of 
the channel's Status register completion bits would be set to 
1 under the following conditions: If a channel decremented 
its Current Operation Count to causing a TC termination, 
input data from the source generat ed a match causing an 
MC t ermination, and a Low on the EOP pin resulted in an 
EOP termination. 

When a DMA operation ends, the channel can: 

(a) Issue an Interrupt request (i.e., setting the IP or SIP bit of 
the channel's Status register) 

(b) Perform Base-to-Current reloading 

(c) Chain reload the next DMA operation 

(d) Perform any combination of the above or 

(e) None of the above 

The user selects the action to be performed by the channel 
in the Completion option field of the Channel Mode register. 
For each type of termination (TC, MC or EOP) the user can 
choose which action or actions are to be taken. If no 
reloading is selected for the type of termination that 
occurred, the NAC bit in the Status register is set. 

More than one action can occur when a DMA operation 
ends. This may arise because more than one action was 
programmed for the applicable termination. The priorities of 
those actions are Interrupt request, Base-to-Current 
reloading, and chaining. The Interrupt cannot be serviced 
unless the DTC has relinquished the bus. 

Interrupts 

To permit the DTC to begin a new DMA operation after 
issuing an interrupt but before the CPU acknowledges that 
interrupt, a two-deep interrupt queue is provided on each 
channel of the DTC. Interrupt handling by the Z8000 
microprocessor is summarized in this section, followed by a 
brief discussion of the DTC's queueing capability and its 
implications for the system. 

A complete Interrupt cycle on the Z8000 CPU consists of an 
Interrupt Request followed by an Interrupt Acknowledge 
transaction. The request, which consists of the CPU's 
Interrupt pin being pulled Low by a peripheral, notifies the 
processor that an interrupt is pending. The Interrupt 
Acknowledge cycle, initiated by the CPU as a result of the 
interrupt request, performs two functions: it selects the 
peripheral whose interrupt is to be acknowledged and it 
obtains a vector that identifies the device involved and the 
reason for the interrupt. 



408 



dllU II llfcN I Upi Ul lUGi OCl VIOC UUO. w. IOC bQ^l I M ICU M 

on the DTC contains all three of these bits (bits CM 1 5-CM ^ 3), 
they are seen by the CPU as two separate interrupt sources. 
Each channel also has its own vector register for identifying 
the source of the interrupt during an Interrupt Acknowledge 
interchange with the CPU. The Disable Lower Chain (DLC) 
and No Vector (NV) bits in the DTC's Master Mode register 
control this behavior for the entire chip. 

Once a channel issues an interrupt, it is desirable to allow the 
channel to proceed with the next DMA operation before the 
interrupt is acknowledged. This could lead to problems if the 
DTC channel attempted to chain reload the Vector register 
contents. In such a situation, it may not be clear whether 
the old or new vector would be returned during the 
acknowledge. This dilemma is resolved in the DTC by 
providing each channel with an Interrupt Save register. 
When the channel sets IP as part of the procedure followed 
to issue an interrupt, the contents of the vector register and 
some of the Status register bits are saved in an Interrupt Save 
register (Figure 9). When an Interrupt Acknowledge cycle is 
performed, the contents of the Interrupt Save register are 
driven onto the bus. Although the use of an Interrupt Save 
register allows the channel to proceed with a new task, 
problems can still arise if a second interrupt is to be issued 
by the channel before the first interrupt is acknowledged. To 
avoid conflicts between the first and second interrupt, each 
channel has a Second Interrupt Pending (SIP) bit in its Status 
register. When a second interrupt is issued before the first 
interrupt is acknowledged, the SIP bit is set and the channel 
relinquishes the bus until an acknowledge occurs. For 
compatibility with polled interrupt schemes, the Interrupt 
Save register can be read without wait states by the host 
CPU. As an aid to debugging a system's interrupt logic, 
whenever IP is set, the Interrupt Save register is loaded from 
the Vector and Status registers. 

Note that the SIP bit is transferred to the IP bit when IP is 
cleared by the host CPU. Whenever CIE is set, INT goes Low 
when IP is set. 

Base-to-Current Reloading. When a channel finishes a 
DMA operation, the user may select to perform a 



respectively, and the Current Operation Count register is 
loaded with the data in the Base Operation Count. The 
Base-to-Current reload operation facilitates repetitive DMA 
operations without the multiple memory accesses required 
by chaining. Although the channel must have bus control to 
perform Base-to-Current reloading, the complete reloading 
operation occurs in four clock cycles (TAU 1 through TAU4). If 
the channel has to relinquish the bus because two 
unacknowledged interrupts are queued, it has to regain bus 
control to perform any Base-to-Current reloading (or 
chaining). In this case it acquires the system bus once an 
interrupt acknowledge is received, even if it immediately 
afterward relinquishes the bus because no hardware or 
software request is present. 

Chaining. If the channel is programmed to chain at the end 
of a DMA operation, it uses the Chain Address register to 
point to a Chain Control Table in memory. The first word in 
the table is a Reload word, specifying the register(s) to be 
loaded. Following the Reload word are the data values to be 
transferred into the register(s). Chaining is described in 
detail in the Channel Initialization section. 

Because chaining occurs after Base-to-Current reloading, it 
is possible to reset the Current Address registers A and B 
and the Current Operation Count register to the values used 
for previous DMA operations and then chain reload one or 
two of these registers to some special value. If the Base 
values are not reloaded during chaining, the channel can 
revert back to the Base values at a later cycle. 

If an all zero Reload word is fetched during chaining, the 
chain operation does not reload any registers but performs 
like any other chaining operation. Thus, the Chain Address 
is incremented by 2 to point to the next word in memory and, 
at the end of the all Zero-Reload word chain operation, the 
channel is ready to perform a DMA operation. All zero 
Reload words are useful as "Stubs" to start or terminate 
linked lists of DMA operations traversed by chaining. Care 
must betaken in their use since the channel may perform an 
erroneous operation if it is unintentionally started after the 
chaining operation. 



409 



COMMANDS 

Table 5 shows a list of DTC commands. The commands are the DTC's Command register (Figure 26). A description of 
executed immediately after the host CPU writes them into each command follows. 

Table 5. DTC Command Summary 





Opcode Bits 


Example 








Command 


7654 


3210 


Code HEX 


Reset 


ooox 


xxxx 


00 


Start Chain Channel 1 


101X 


xxxo 


AO 


Start Chain Channel 2 


101X 


XXX1 


A1 


Set Software Request Channel 1 


01 ox 


XX10 


42 


Set Software Request Channel 2 


01 ox 


XX11 


43 


Clear Software Request Channel 1 


01 ox 


xxoo 


40 


Clear Software Request Channel 2 


01 ox 


XX01 


41 


Set Hardware Mask Channel 1 


100X 


XX10 


82 


Set Hardware Mask Channel 2 


100X 


XX11 


83 


Clear Hardware Mask Channel 1 


100X 


xxoo 


80 


Clear Hardware Mask Channel 2 


100X 


XX01 


81 


Set CIE. or IP Channel 1 


001 E 


XP10 


32 


Set CIE, or IP Channel 2 


001 E 


XP11 


33 


Clear CIE. or IP Channel 1 


001 E 


XPOO 


30 


Clear CIE, or IP Channel 2 


001 E 


XP01 


31 


Set Flip Bit Channel 1 


01 1X 


XX10 


62 


Set Flip Bit Channel 2 


011X 


XX11 


63 


Clear Flip Bit Channel 1 


011X 


XXOO 


60 


Clear Flip Bit Channel 2 


011X 


XX01 


61 



NOTES: E = Set to 1 to perform set/clear on CIE; clear to for no effect on CIE 
P = Set to 1 to perform set/clear on IP; clear to lor no effect on IP 
X = "dont't care" bit. This bit is not decoded and may be or 1 



Reset (00) 

This command causes the DTC to be set to the same state as 
a hardware reset. The Master Mode register is cleared to all 
Os, the CIE, IP, and SIP bits are cleared to 0, the NAC and CA 
bits in each channel's Status register are set to 1, and the 
channel activity is forbidden. The Chain Address must be 
programmed since its state may be indeterminate after a 
Reset. The lockout preventing channel activity is cleared by 
issuing a Start Chain command. 



Figure 26. Command Register 



I CHANNEL 2/CHANNEL 1 

I SET/CLEAR 

I INTERRUPT PENDING 

DONTCARE 

CHANNEL INTERRUPT ENABLE 












RESET 








1 


INTERRUPT CONTROL 





1 





SOFTWARE REQUEST 





1 


1 


FLIP BIT 


1 








HARDWARE MASK 


1 





] 


START CHAIN 


1 


1 





NOT RECOGNIZED 


1 


1 


1 


NOT RECOGNIZED 



410 



Start Chain Channel 1 /Channel 2 (A IA^) 

This command causes the selected channel to clear the No 
Auto-Reload or Chain (NAC) bit in the channel's Status 
register, and to start a chain reload operation of the 
channel's registers, as described in the Channel 
Initialization section. These effects take place even if the 
fetched Reload word is all zeros. This command is only 
honored if the Chain Abort (CA) bit and the Second Interrupt 
Pending (SIP) bit in the Channel's Status register are clear. If 
either the CA or SIP bit is set, this command is disregarded. 

When the Waiting For Bus (WFB) bit of the Status Register is 
set, if the "Start Chain" command is issued, the channel 
honors the command after one DMA iteration. It is nearly 
impossible for the CPU to issue a command when WFB = 1 
and the DTC is enabled. 

Software Request Channel 1 /Channel 2 
(Set: 42/43, Clear: 40/41) 

This command sets or clears the Software Request bit in the 
selected channel's Mode register. If the Second Interrupt 
Pending (SIP) bit and No Auto-Reload or Chain (NAC) bit in 
the channel's Status register are both cleared, the channel 
begins executing the programmed DMA operation. If either 
the SIP or NAC bit is set, the channel does not start 
executing a DMA operation. The SIP bit clears when the 
channel receives an interrupt acknowledge. One way to 
clear the NAC bit is to issue a Start Chain command to the 
channel. If the fetched Reload Word is all zeros, the 
channel's registers remain unchanged and the software 
request bit, if set earlier by command, causes the 
programmed DMA operation to start immediately. If during 
chaining, new information is loaded into the Channel Mode 
register, this new information overwrites the software request 
bit. 

Set/Clear Hardware Mask 1/Mask 2 
(Set: 82/83; Clear: 80/81) 

This command sets or clears the Hardware Mask in the 
selected channel's Mode register. This command always 
takes effect. The Hardware Mask bit inhibits recognition of 
an active signal on the channel's DREQ input; this bit does 



not affect recognition of a software request. If the channel is 
in single transfer mode, it perfo rms DMA operations upon 
receipt of a transition on DREQ rather than in response to a 
DREQ level. Transitions, occurring while the Hardware mask 
bit is set, are stored and serviced when the Hardware Mask 
is cleared, assuming the Channel has not chained. The DTC 
requests the system bus o ne and one half to two clock 
cycles after the receipt of any DREQ, after wh ich a minimum 
of one DMA iteration is unavoidable. DREQ transitions are 
stored only for the current DMA operation. If the channel 
perform s a chain operation of single transfer mode, any 
DREQ transition stored for later service is cleared. 

Figure s 1 5 and 1 6 show the minimum times when a new 
DREQ can be applied if it is to be serviced by the new DMA 
operation. First iteratio n and Last iteration in Figure 15 
mean, for example, that DREQ may be asserted during the 
write cycle T-, of a Flowthrough transaction, but may never 
be asserted during of a Flyby transaction since Flyby is 
done in one iteration. 

Set/Clear CIE, and IP Channel 1 /Channel 2 (Table 5) 

This command allows the user to set or clear any 
combination of the CIE and IP bits in the selected channel's 
Status register. These bits control the operation of the 
channel's interrupt structure and are described in the 
Interrupts section. Setting the IP bit causes the interrupt 
Save register to be loaded with the current vector and status. 
The IP bit is cleared to facilitate an efficient conclusion to the 
processing of an interrupt. 

Set/Clear Flip Bit Channel 1 /Channel 2 
(Set: 62/63; Clear 60/61) 

The Flip Bit in the selected channel's Mode register can be 
cleared and set by this command. This allows the user to 
reverse the source and destination and thereby reverse the 
data transfer direction without reprogramming the channel. 
This command is useful when repetitive DMA operations are 
performed by the channel, using this command to control 
the direction of transfer. Chaining new information into the 
Channel Mode register overwrites the Flip bit. 



411 



-®- 



-®- 



AD -AD,5 



cs 



DATA FROM DTC 



> 



— ® 



-ff- 



-®- 



X 



Figure 27. AC Timing when DTC is a Bus Slave 




Figure 28. AC Timing when DTC is a Bus Master 



412 





Figure 31 . Reset Timing 



A16-&22 



_ T 'P _ 
Taus 



IX 



IX 



X 



Taui _ 



7 



- CHAINING CYCLE - 



XX 



xz 

ADDRESs j 



XI 



N/S 



X 



X 



y 



7 



X 



Figure 32. Timing During Chaining 



414 




EOP 



INTERNAL 
EOP 



NOTES: 1 . State Trp is a pseudo-T, state, without active AS generated following termination ot any DMA operation. 

2. State Taui, is an auto-initialization state generated following the TC, MC. or EOP termination. 

3. Level DACK Rising Edge occurs as shown if auto-reloading is not programmed, otherwise it stays Low for three additional clock cycles. 

Figure 33. DACK Timing 



a) EOP SAMPLING AND GENERATION DURING DMA OPERATIONS 



CHANNEL HOLDS BUS 
-Thld «4" Thld- 



CHANNEL RELEASES BUS 
TIDLE «- 



EXTERNAL 
EOP 



b) SAMPLING OF EOP DURING BUS HOLD 



Notes: 

1. The diagram lists state names lor- both I/O and memory accesses. Sampling o( EOP will occur on the falling edge of state T 3 . 

2. State T 1P is a pseudo-T! state, without active AS generated following termination of any DMA operation. 

3. State TAUi is an auto-initialization state generated following the TC. MC. or EOP termination. 



\ / 



a r 



Figure 34. EOP Timing 




s. j \ / — r x 



Figure 35. WAIT Timing 



415 



ABSOLUTE MAXIMUM RATINGS 



Voltages on all pins with respect to GND . - 0.3 V to + 7.0 V 
Operating Ambient 

Temperature See ordering information 

Storage Temperature - 65 °C to + 1 50 °C 



Stresses greater than those listed under Absolute Maximum Ratings may 
cause permanent damage to the device. This is a stress rating only; 
operation ot the device at any condition above those indicated in the 
operational sections of these specifications is not implied. Exposure to 
absolute maximum rating conditions for extended periods may affect 
device reliability. 



STANDARD TEST CONDITIONS 

The DC Characteristics and Capacitance sections listed 
below apply for the following standard test conditions, 
unless otherwise noted. All voltages are referenced to GND. 
Positive current flows into the referenced pin. 



Standard condtions are as follows: 

■ + 4.75V <V CC < + 5.25V 

■ GND = 0V 

■ T A as specified in Ordering Information 

All ac parameters assume a load capacitance of 50 pf 
maximum. 




DC CHARACTERISTICS 



Symbol 


Parameter 


Min 


Max 


Unit 


Test Condition 


V C H 


Clock Input High Voltage 


Vcc-0.4 


Vcc + °3 


V 


Driven by External Clock Generator 


V C L 


Clock Input Low Voltage 


-0.3 


0.45 


V 


Driven by External Clock Generator 


VlH 


Input High Voltage 


2.0 


V CC + 0.3 


V 




V|L 


Input Low Voltage 


-0.3 


0.8 


V 




V H 


Output High Voltage 


2.4 




V 


l 0H = -250 (iA 


Vol 


Output Low Voltage 




0.4 


V 


l L= +2. 0mA 


IlL 


Input Leakage 




±10 


MA 


0.4 < V, N < V CC 


lOL 


Output Leakage 




±10 


XA 


0.4 < V| N < +Vcc 


ice 


Vcc Supply Current 




350 


mA 


T A = 0°C 



NOTE: Vcc = 5V ± 5% unless otherwise specified. 



CAPACITANCE 



Symbol 


Parameter 


Min 


Max 


Unit 


c CLOCK 


Clock 




40 


Pf 


C|N 


Input 




5 


Pf 


COUT 


Output 




10 


Pf 



NOTES: 
T A = 25°C,f = 1 MHz. 
Unmeasured pins returned to ground. 



416 



AC CHARACTERISTICS^ 

DTC AS BUS MASTER 









4MHz 


6MHz 


Number 


Symbol 


Parameter 


Min(ns) Max(ns) 


Min(ns) 


Max(ns) 


1 


TcC 


Clock Cycle Time 


250 2000 


165 


2